Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
  • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
  • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
  • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
  • H10D30/472—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having lower bandgap active layer formed on top of wider bandgap layer, e.g. inverted HEMT
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
  • H10D62/815—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW]
  • H10D62/8161—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices
  • H10D62/8162—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices having quantum effects only in the vertical direction, i.e. layered structures having quantum effects solely resulting from vertical potential variation
  • H10D62/8164—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices having quantum effects only in the vertical direction, i.e. layered structures having quantum effects solely resulting from vertical potential variation comprising only semiconductor materials 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
  • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
  • H10D64/311—Gate electrodes for field-effect devices
  • H10D64/411—Gate electrodes for field-effect devices for FETs
  • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
  • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
  • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates

Definitions

• the present disclosure is directed in general to the area of Ill-Nitride transistors and in particular to the design and fabrication of P-Channel GaN Transistors.
• GaN power integrated circuits have the potential of dramatically reducing the size and weight of power electronic systems, thereby substantially reducing the cost of power electronic devices.
• P-channel GaN-transistor is a critical component for making GaN power ICs.
• Such power electronic systems are widely needed in electric/hybrid vehicles, more-electric aircraft, as well as many consumer electronic products.
• GaN transistors include P-Channel transistors in conjunction with N-Channel transistors using an analog alloy to improve conductivity.
• a tertiary alloy such as AiGaN (Aluminum-GalUum-Nitride) is often referred to as analog alloy in the art.
• AiGaN Al-GalUum-Nitride
• the proposed technology overcomes mis limitation by proposing a hew way to increase channel conductivity while managing the stress related to lattice mismatch.
• a power handling device comprising, a III- nitride channel layer, a Ill-nitride cap layer on the channel layer, where the cap layer has higher level of p-type doping than the channel layer, and a IH-nitride digital alloy back barrier below the channel layer comprising a superiattice or superiattice structure.
• a superiattice is a layer consisting of at least three alternating layers of a material A and a material B; each layer of material A and each layer of material B having a thickness of less than 10 nanometer.
• Another embodiment described in this disclosure provides for a process of making a power handling device comprising die steps of depositing a buffer layer on a substrate, depositing a digital alloy back barrier layer on the burlier layer, depositing a IH-nitride channel on the digital alloy layer, depositing a ⁇ -nitride p-doped cap layer on the channel layer, etching a gate recess in the cap layer exposing the channel layer, depositing a gate dielectric inside the gate recess and depositing a gate metal inside the gate recess and on the gate dielectric wherein, the digital alloy layer is made up of superiattice structure.
• An embodiment of mis disclosure comprises a power handling device having: a Ill- nitride channel layer, a Ill-nitride cap layer on die channel layer, where the cap layer has higher level of p-type doping than the channel layer, and a Ill-nitride digital alloy back barrier below the channel layer; die Ill-nitride digital alloy back barrier comprising a superiattice structure.
• the power handling device further comprises a buffer layer below die digital alloy back barrier layer.
• the Ill-nitride channel layer is a Gallium Nitride (GaN) channel layer.
• GaN Gallium Nitride
• the cap layer is a Magnesium (Mg) doped GaN.
• the digital alloy back barrier is a binary alloy.
• die superiattice structure comprises alternating Aluminum Nitride (A1N) and GaN layers.
• the superiattice structure comprises ternary alloys.
• die superiattice structure comprises alternating GaN and Aluminum-Gallium-Nitride (AlGaN) layers.
• the superiattice structure comprises alternating AlGaN and AlGaN layers with different Aluminum percentages.
• the digital alloy is designed to mitigate strain due to lattice mismatch between the channel layer and the digital alloy back barrier layer.
• An embodiment of this disclosure also comprises a of making a power handling device comprising: depositing a buffer layer on a substrate; depositing a digital alloy back barrier layer on the butter layer, depositing a Hl-nitride channel on the digital alloy layer, depositing a Ill-nitride p-doped cap layer on the channel layer; etching a gate recess in the cap layer exposing the channel layer; depositing a gate dielectric inside the gate recess; and depositing the gate metal inside the gate recess and on the gate dielectric, wherein the digital alloy layer is made up of superlattice structure.
• the IH-mtride channel is GaN and the cap layer is a Magnesium (Mg) doped GaN.
• the digital alloy back barrier is a binary alloy.
• the superlattice structure comprises alternating Aluminum Nitride (AIN) and GaN layers.
• the superlattice structure comprises ternary alloys.
• the superlattice structure comprises alternating GaN and Aluminum-Gallium-Nitride (AlGaN) layers.
• the superlattice structure comprises alternating AlGaN and AlGaN layers with different Aluminum percentages.
• the digital alloy is designed to mitigate the strain due to lattice mismatch between the channel layer and the digital alloy back barrier layer.
• the digital alloy layer is between 1 micrometer and 2 micrometer thick.
• An embodiment of this disclosure comprises a P-channel IH-nitride transistor having: a Ill-mtride channel layer, and a Ill-mtride digital alloy back barrier below die channel layer, the ⁇ -nitride digital alloy back barrier comprising a superlattice structure.
• Certain embodiments may provide various technical advantages depending on the implementation.
• a technical advantage of some embodiments may include the use of binary digital alloy such as stacked up layers of Aluminum Nitride and Gallium Nitride.
• Other embodiments may use stack up of ternary digital alloys.
• specific advantages have been enumerated above, various embodiments may include some, none, or ail of the enumerated advantages. Additionally, other technical advantages may become readily apparent to one of ordinary skill in the art after review of the following figures and description.
• Figure 1 illustrates a conventional p-channel GaN structure with analog AlGaN back barrier
• Figure 2 illustrates a p-channel GaN device containing digital AlN-GaN super lattice structure alloys as the back barrier, according to an embodiment of the present disclosure
• Figures 3a, 3b and 3c illustrate the first set of steps involved in the fabrication of a p- channel GaN transistor containing digital AlN-GaN super lattice alloys as the back barrier, according to an embodiment of the present disclosure
• Figures 4a, 4b and 4c illustrate the next set of steps involved in the fabrication of a p- channel GaN transistor containing digital AlN-GaN super lattice alloys as the back barrier, according to an embodiment of the present disclosure
• Figure 5a illustrates a p-channel GaN transistor structure according to an embodiment of the present disclosure
• Figure Sb illustrates the channel conductivity characteristics for the p-channel GaN transistor structure illustrated in Figure Sa;
• Figure 5c illustrates a p-channel GaN transistor structure according to an embodiment of the present disclosure
• Figure 5d illustrates the channel conductivity characteristics for the p-channel GaN transistor structure illustrated in Figure Sc;
• Figure 6a illustrates a p-channel GaN transistor structure according to an embodiment of the present disclosure
• Figure 6b illustrates the channel conductivity characteristics for the p-channel GaN transistor structure illustrated in Figure 6a;
• J Figure 6c illustrates a p-channel GaN transistor structure according to an embodiment of the present disclosure.
• Figure 6d illustrates the channel conductivity characteristics for the p-channel GaN transistor structure illustrated in Figure 6c.
• GaN transistors have revolutionized high power and high speed switching electronics and mere is a constant push, driven by the application demands, for higher and higher power handling capacities.
• GaN transistor's power handling capacity depends directly on the channel conductivity.
• [004SJ HI-Nitride semiconductor materials (Aluminum, Indium, Gallium)Nitride are excellent wide band gap semiconductors very suitable for modern electronic and optoelectronic applications. Though this disclosure describes the technology using GaN, the proposed technology applies to any of the ⁇ -Nitride semiconductor materials.
• Figure I illustrates a conventional p-channel GaN transistor structure. It contains a ternary alloy (102) Aiuminum-Gallium Nitride (A!GaN), which is normally referred to as analog AIGaN, as the back barrier.
• AIGaN Aiuminum-Gallium Nitride
• This back barrier 102 is directly under the GaN channel 103 as the back barrier layer helps to improve the p-type carrier concentration in the GaN channel, utilizing the polarization effect introduced by the back barrier AIGaN layer 102.
• the higher conduction banding energy in the large bandgap AIGaN barrier layers improves the confinement of carriers in the low bandgap GaN channel compared to the same structure without the AIGaN barrier underneath the GaN channel.
• the AIGaN layer 102 is built on top of a buffer layer 101 and the buffer layer helps introducing more holes from the p-type GaN.
• a layer of GaN can serve as the buffer layer 101 and can be mounted on a substrate such as a Sapphire (not shown).
• a layer 104 of p-doped GaN, (such as Magnesium (Mg) doped GaN) on top of the GaN channel 103 completes the formation of a device mat can be used to make a typical GaN transistor.
• a typical GaN transistor using the structure illustrated in Figure 1 uses the polarization effect of the back barrier 102 to increase the channel conductivity. Polarization induced hole density is a known phenomenon in the ait, as the p-type earners tend to crowd near the polarized barrier.
• AlGaN With reasonable thickness is required.
• the AlGaN back barrier is grown on GaN buffer, which has a larger lattice constant compared to AlGaN. This introduces a tensile strain in the AlGaN film. Increasing the percentage of Aluminum leads to larger tensile strain, which eventually results in cracks in the AlGaN film.
• the use of AlGaN as a back barrier is often referred to as analog back barrier alloy.
• this disclosure proposes a new technology, where the back-barrier layers use digital alloy instead of the analog alloy to improve the channel conductivity while minimizing the stress related to the lattice mismatch.
• super lattices such as comprised of stacked up AlN/GaN (Aluminum nitride / Gallium Nitride) alternating layers are referred to as digital alloys.
• Figure 2 illustrates a GaN device 200, according to an embodiment of the present disclosure. It uses alternating AlN/GaN layers forming a superlartice structure 205, which is referred to as a digital AlGaN alloy, to serve as the back barrier.
• Superlartice structures help reduce the cracking issues due to lattice mismatches.
• superlattice structures can provide a polarization effect similar to what the p-type carrier requires to be formed in the GaN channel.
• the GaN device 200 comprises of a buffer layer 201, typically about 1.5 micrometer thick and a digital superlattice alloy 205 back barrier mounted over the buffer layer 201.
• the super lattice back barrier 205 comprises alternating layers of AIN (205bj. consultation) and GaN (205aj. folk). This structure is also called as binary alloy.
• Each of the AIN layers (205bi ⁇ ) are typically about 2 to 3 nanometer thick, while the GaN layers (205ai . folk) can each be typically 2 to 10 nanometer thick.
• the superlattice (SL) back barrier 205 typically has more than two; preferably 30 to 40 pairs of alternating A1N and GaN layers.
• An alternative SL structure is an alternating AlGaN and GaN stack up 205 or AlGaN/AlGaN stack up 205 where the AlGaN layers have different amount Aluminum percentages (by weight or volume).
• the super lattice comprises at least three alternating layers of A1N and GaN; each layer having a thickness of less than 10 nanometer.
• the GaN channel layer 203 is fabricated over the digital alloy layer 205.
• the GaN channel layer can be 50 nanometer to 300 nanometer thick.
• the Magnesium (Mg) doped GaN cap layer 204 serves to supply the holes to the channel and is fabricated on top of the GaN channel 203.
• the p-doped GaN cap layer 204 is typically about 100 nanometer to 200 nanometer thick. In this embodiment, the cap layer 204 can have much higher Mg doping due to the higher polarization effect of the digital alloy layer 205.
• the overall total device thickness is typically less than 3 micrometer.
• the buffer layer 201 can be GaN or AlGaN.
• the AlGaN/GaN high-electron-mobility transistor requires a thermally conducting, semi-insulating substrate to achieve the best possible performance.
• the semi-insulating SiC substrate is currently the best choice for this device technology; however, fringing fields which penetrate the GaN buffer layer at pinch-off introduce significant substrate conduction at modest drain bias if channel electrons are not well confined to the nitride structure.
• the addition of an insulating buffer on the semi-insulating SiC substrate suppresses this parasitic conduction, which results in dramatic improvements in the AIGaN/GaN transistor performance. A pronounced reduction in both the gate-lag and the gate-leakage current are observed for structures with the buffer layer.
• the digital SL alloy back barrier layer 205 provides the necessary polarization effect along the interface with the GaN channel layer 203. Holes crowd along this interface to provide for the necessary channel conductivity.
• the digital alloy helps providing a thick back barrier with a strong polarization maintained, which helps introduce more holes into the GaN channel layer 203.
• a transistor made using GaN device 200 was evaluated for performance and found to have substantially higher switching speeds, lower switching loss and a substantially reduced parasitic value.
• the process of making a transistor using the GaN device 200 can comprise fabricating the layers as structured in Figure 3b, followed by the process steps illustrated in Figure 3c and 4a through 4c.
• the digital alloy 305 can be fabricated as illustrated in Figure 3a.
• the alloy 305 can either be fabricated first or alternatively fabricated as part of fabricating the stack as illustrated in Figure 3b.
• the digital alloy 305 can be formed by stacking up alternative layers of GaN and A1N.
• a GaN layer is formed using one of many known techniques in the ait.
• One such technique is molecular beam epitaxy (MBE).
• MBE molecular beam epitaxy
• a GaN layer can also be formed by a sputtering process at a high substrate temperature ⁇ for example greater than 700-degree Celsius. Since Gallium is a l iquid at around 30-degree Celsius, initial nitridation of Gallium liquid metal surface needs to be done in this sputtering process using pure Ga as target surface.
• a horizontal water cooled stainless steel trough can be used for the growth of GaN epilayer.
• a reactive Direct Current (DC) magnetron sputter epitaxy can be used.
• a GaN layer is first formed to the required thickness of between 2 nanometer to 10 nanometer, followed by an A1N (Aluminum Nitride) layer formed on top of this GaN layer by several known techniques, such as sputtering, electroplating or MBE. Typically, a 2 nanometer to 3 nanometer thick AIN layer is formed. The process is repeated for subsequent pair of GaN and AIN layers. It is not unusual to form 30 to 40 pairs of GaN/AIN layers by repeating this process, yielding a digital alloy that is less than 3 micrometer thick.
• the process of making the device 200 comprises forming a buffer layer 301 on a substrate 306 of choice, such as Silicon Carbide (SiC) or Saphire, as illustrated in Figure 3b.
• the buffer layer 301 can be any suitable material, such as GaN or AlGaN.
• the buffer layer is typically about 1 to 2 micrometer thick and preferably 1.5 micrometer thick.
• the digital alloy 305 is formed on top of this buffer layer as described earlier.
• the digital alloy can be fabricated separately and deposited on top of the buffer layer by any known techniques such as MBE or a sputtering process.
• the digital alloy will be between 1 to 2 micrometer thick and preferably about 1.5 micrometer thick.
• the GaN channel is fabricated on top of the digital alloy using techniques described earlier.
• the GaN channel is typically between 50 nanometer to 300 nanometer thick, and preferably 100 nanometer thick.
• the p-doped GaN layer is formed on top of the GaN channel by any known process, such as MBE or sputtering.
• MBE Magnesium
• Magnesium (Mg) is used as the p-dopant
• the next step in the process is to etch a gate recess 307 that exposes the GaN channel 303 as illustrated in Figure 3c.
• This etching process typically comprises masking the area around and exposing the etching area and using known etching techniques (such as using chemical or gas or laser / molecular beams) to etch out the gate area and exposing a part of the GaN channel 303.
• a suitable gate dielectric 408 such as Silicon dioxide is deposited as illustrated in Figure 4a by any known techniques, such as depositing Silicon by sputtering followed by oxidation or any other suitable technique depending on the chosen gate dielectric.
• Figure 4b illustrates the next step of forming the ohmic contacts 409a and 409b on the p-channel.
• This step comprises of depositing the contact electrode of the device, such as gold, copper or silver and is typically done using electroplating or sputtering process.
• the final step is to form the gate metal in the cavity of the dielectric as illustrated in Figure 4c.
• the gate metal can be gold, silver or copper or any other suitable gate material. Depending on the chosen gate material, process such as electroplating or sputtering can be used.
• the surfaces can be polished, cleaned and separated from the substrate to form the device 200.
• any of the steps illustrated can be changed, modified or eliminated to better suit the materials chosen or as known to one in the art Additional steps may be added as needed to perfect the device fabrication per specification.
• Figure Sa illustrates a GaN transistor structure having an epi structure without the back barrier. It comprises of the Buffer layer 501 and having a GaN channel 503 on top. The p- doped GaN layer 504 using Mg as the dopant is deposited on top of the GaN channel 503.
• the ohmic contacts 509a and 509b is used to apply a voltage to the device and current through the structure is measured. On the right is the measured performance characteristics of this structure as shown in Figure 5b.
• the X-axis 512 is the voltage applied in Volts between the ohmic contacts 509a and 509b.
• the Y-axis 511 is the measured current through the device in ⁇ amps.
• Figure 5c illustrates a revised device structure where an analog alloy 502 is added to the device.
• This analog alloy 502 creates the polarization effect along the GaN channel boundary causing hole crowding and increased current flow.
• Figure 5d illustrates the performance of this structure in Figure 5c.
• the current increases to -410 ⁇ amps to + 410 ⁇ amps as shown by the performance curve 522. This is almost a threefold increase in the device conductivity, primarily caused by the introduction of the analog alloy 502.
• Figure 6c illustrates the digital ailoy layer 605 replacing the analog alloy 502, located between die Buffer layer 501 and the GaN channel 503.
• the corresponding performance curve 624 in Figure 6d shows the current through the device in the range of -1.0 milliamps to +1.0 milliamps as the applied voltage is varied between die same voltage range of -lOv to +1 Ov, as shown by Figure 6d. This is almost a 3X performance in device conductivity compared to the analog alloy performance 522 in Figure 5d.
• the AIN/GaN alloy to create the polarization effect to enhance hole crowding
• AIGaN/GaN alloy to create the polarization effect.
• the device stack up can be varied to suit the intended applications. Thickness of each layers as well as the digital alloy thickness can be varied to meet particular performance needs.
• this disclosure describes the technology using GaN, the proposed technology applies to any of the Ill-Nitride semiconductor materials (Al, In, Ga)N or the combinations thereof.
• a Ill-nitride power handling device and the process of making the Ill-nitride power handling device are disclosed mat use digital alloys as back barrier layer to mitigate the strain due to lattice mismatch between the channel layer and the back barrier layer and to provide increased channel conductivity.
• An embodiment discloses a GaN transistor using a superlattice binary digital alloy as back barrier comprising alternative layers of A1N and GaN.
• Other embodiments include using superlattice structures with layers of GaN and AlGaN as well as structures using AlGaN/AlGaN stackups that have different Aluminum concentrations.
• the disclosed device has substantially increased channel conductivity compared to traditional analog alloy back barrier devices.
• a power handling device comprising:
• Ill-nitride cap layer on the channel layer, where the cap layer has higher level of p-type doping than the channel layer, and
• the IH-nitride digital alloy back barrier comprising a superlattice structure
• the power handling device of Concept 1 further comprising a buffer layer below the digital alloy back barrier layer.
• the power handling device of Concept I wherein the 11 l-nitride channel layer is a Gallium Nitride (GaN) channel layer.
• GaN Gallium Nitride
• the power handling device of Concept 1 wherein the superlattice structure comprises alternating Aluminum Nitride (AM) and GaN layers.
• the superlattice structure comprises alternating GaN and Aluminum-Gallium-Nitride (AlGaN) layers.
• a process of making & power handling device comprising:
• the digital alloy layer is made up of superlattice structure.
• a P-channel Ill-nitride transistor comprising:
• the ⁇ -nitride digital alloy back barrier comprising a superiattice structure.

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• 2017
  • 2017-08-25 CN CN201780094188.2A patent/CN111033750B/zh active Active
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