EP3649833A1 - Procédé de réglage de température de couleur corrélée à large bande qui suit la ligne de corps noir à l'aide de deux canaux de courant commandés indépendamment et de trois températures de couleur corrélées - Google Patents

Procédé de réglage de température de couleur corrélée à large bande qui suit la ligne de corps noir à l'aide de deux canaux de courant commandés indépendamment et de trois températures de couleur corrélées

Info

Publication number
EP3649833A1
EP3649833A1 EP18738426.8A EP18738426A EP3649833A1 EP 3649833 A1 EP3649833 A1 EP 3649833A1 EP 18738426 A EP18738426 A EP 18738426A EP 3649833 A1 EP3649833 A1 EP 3649833A1
Authority
EP
European Patent Office
Prior art keywords
current
input current
voltage
led array
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP18738426.8A
Other languages
German (de)
English (en)
Other versions
EP3649833B1 (fr
Inventor
Yifeng QIU
Frederic S. Diana
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lumileds LLC
Original Assignee
Lumileds LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US15/640,549 external-priority patent/US10716183B2/en
Application filed by Lumileds LLC filed Critical Lumileds LLC
Publication of EP3649833A1 publication Critical patent/EP3649833A1/fr
Application granted granted Critical
Publication of EP3649833B1 publication Critical patent/EP3649833B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/20—Controlling the colour of the light
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/40—Details of LED load circuits
    • H05B45/44—Details of LED load circuits with an active control inside an LED matrix
    • H05B45/46—Details of LED load circuits with an active control inside an LED matrix having LEDs disposed in parallel lines

Definitions

  • Tunable white lighting is one of the biggest trends in commercial and home lighting.
  • a tunable-white luminaire is usually able to change its color and light output level along two independent axes.
  • An interface currents channeling circuit may be used to convert two current channels of a conventional two-channel driver into three driving currents for the three LED arrays. By doing so, the same two channel driver may be used for applications requiring just two LED arrays as well as three LED arrays.
  • FIG. 1 is a chromaticity diagram representing a color space
  • FIG. 2 is a diagram illustrating different correlated color temperatures (CCTs) and their relationship to a black body line (BBL) on the chromaticity diagram;
  • FIG. 3 is a block diagram illustrating hardware used in a tunable white light engine having a corresponding number of light emitting diode (LED) arrays and driver channels;
  • LED light emitting diode
  • FIG. 4 is a block diagram illustrating hardware used in tunable white light engine having a greater number of LED arrays than driver channels;
  • FIG. 5 is a circuit diagram of an interface currents channeling circuit
  • FIG. 6 is a flowchart illustrating a method for providing two-step linear CCT tunability in one or more LED arrays.
  • a color space is a three-dimensional space; that is, a color is specified by a set of three numbers that specify the color and brightness of a particular homogeneous visual stimulus.
  • the three numbers may be the International Commission on Illumination (CIE) coordinates X, Y, and Z, or other values such as hue, colorfulness, and luminance.
  • CIE International Commission on Illumination
  • a chromaticity diagram is a color projected into a two- dimensional space that ignores brightness.
  • the standard CIE XYZ color space projects directly to the corresponding chromaticity space specified by the two chromaticity coordinates known as x and y, as shown in FIG. 1.
  • Chromaticity is an objective specification of the quality of a color regardless of its luminance. Chromaticity consists of two independent parameters, often specified as hue and colorfulness, where the latter is alternatively called saturation, chroma, intensity, or excitation purity.
  • the chromaticity diagram may include all the colors perceivable by the human eye. The chromaticity diagram may provide high precision because the parameters are based on the spectral power distribution (SPD) of the light emitted from a colored object and are factored by sensitivity curves which have been measured for the human eye. Any color may be expressed precisely in terms of the two color coordinates x and y.
  • SPD spectral power distribution
  • MAE Modultude Matching in LED lighting uses deviations relative to MAEs to describe color precision of a light source.
  • the chromaticity diagram includes the Planckian locus, or the black body line (BBL) 106.
  • the BBL 106 is the path or locus that the color of an incandescent black body would take in a particular chromaticity space as the blackbody temperature changes. It goes from deep red at low temperatures through orange, yellowish white, white, and finally bluish white at very high temperatures. Generally speaking, human eyes prefer white color points not too far away from the BBL 106. Color points above the black body hne would appear too green while those below would appear too pink.
  • LEDs may be to additively mix red, green and blue colored lights. However, this method may require precise calculation of mixing ratios so that the resulting color point is on or close to the BBL 106.
  • Another method may be to mix two or more phosphor converted white LEDs of different correlated color temperatures (CCTs). This method is described in additional detail below.
  • LEDs having two different CCTs on each end of a desired tuning range may be used.
  • a first LED may have a CCT of 2700K, which is a warm white
  • a second LED may have a color temperature of 4000K, which is a neutral white.
  • White colors having a temperature between 2700K and 4000K may be obtained by simply varying the mixing ratio of power provided to the first LED through a first channel of a driver and power provided to the second LED through a second channel of the driver.
  • FIG. 2 a diagram illustrating different CCTs and their relationship to the BBL 106 is shown.
  • the achievable color points of mixing two LEDs with different CCTs may form a first straight line 202.
  • the color points of 2700K and 4000K are exactly on the BBL 106, the color points in between these two CCTs would be below the BBL 106. This may not be a problem, as the maximum distance of points on this line from the BBL 106 may be relatively small.
  • the first straight line 202 between the two colors may be far below the BBL 106. As shown in FIG. 2, the color point at 4000K may be very far away from the BBL 106.
  • a third channel of neutral white LEDs (4000K) may be added between the two LEDs and a 2 -step tuning process may be performed.
  • a first step line 204 may be between 2700K and 4000K and a second step line 206 may be between 4000K and 6500K.
  • This may provide 3 step MAE BBL color temperature tunability over a wide range of CCTs.
  • a first LED array having a warm white (WW) CCT, a second LED array having a neutral white (NW) CCT, and a third LED array having a cool white (CW) CCT and a two-step tuning process may be used to achieve three- step MAE BBL CCT tunability over a wide range of CCTs.
  • a two channel driver 302 may be used to power two LED arrays having CCTs at the ends of a desired tuning range.
  • the two channel driver 302 may be a conventional LED driver known in the art.
  • the two LED arrays may be mounted on an LED board 318.
  • a first channel 304 of the two channel driver 302 may power a first LED array 306 of a first CCT and a second channel 308 of the two channel driver 302 may power a second LED array 310 of a second CCT.
  • the two channel driver 302 may provide two driving currents to the LED board 318 over one or more electrical connections 312, such as wires or direct board to board connections.
  • the one or more electrical connections 312 may be connected to one or more solder points 316.
  • a three-channel driver may be used to control the three LED arrays in a similar manner.
  • a three-channel driver may be more complex and expensive than a conventional two channel driver. It may be desirable to multiply the output of a driver to power a greater number of LED arrays than channels, such that there is more than a 1: 1 ratio of driver channels to LED arrays.
  • FIG. 4 a block diagram illustrating hardware used in tunable white light engine having a greater number of LED arrays than driver channels is shown.
  • An interface currents channeling circuit may be used to convert two current channels of a two channel driver 402 into three driving channels in order to achieve 2-piece linear near BBL 106 color temperature tunability.
  • the interface currents channeling circuit may be mounted on a converter printed circuit board (PCB) 404 between the two channel driver 402 and a LED board 406.
  • the two channel driver 302 may be a conventional LED driver known in the art.
  • the interface currents channeling circuit may allow the two channel driver 402 to be used for applications requiring two LED arrays as well as applications with three LED arrays. Because the same two channel driver 402 may be used in both cases, circuit complexity, size, and expense may be reduced.
  • FIG. 3 shows an interface channeling circuit that may be used to power three LED arrays using a two- channel driver
  • the principles described below may be applied to any arrangement in which a driver is used to power a number of LED arrays that is greater than a number of output channels.
  • the follow description relates to the tunability of LED arrays having different CCTs, a person skilled in the art would understand that the embodiments described herein may apply to any desired tunable range, such as color ranges, infrared (IR) ranges, and ultraviolet (UV) ranges.
  • the interface currents channeling circuit mounted on the converter PCB 404 may enable the two channel driver 402 to power two LED arrays at the ends of a desired tunable range as well as an additional LED array in approximately the middle of the desired tunable range.
  • a first LED array 408 having a first CCT, a second LED array 410 having a second CCT, and a third LED array 412 having a third CCT may be mounted on the LED board 318.
  • a first channel 412 of the two channel driver 402 and a second channel 414 may be connected to the PCB 404 by a first set of connections 416, such as wires or direct board to board connections.
  • the first channel 412 and the second channel 414 may each have a positive and a negative output.
  • the converter PCB 404 may provide three driving currents to the
  • the LED board 406 over a second set of electrical connections 418, such as wires or direct board to board connections.
  • the second set of electrical connections 418 may be connected to one or more solder points 420 on the LED board 406.
  • the second set of electrical connections 418 may include three separate negative outputs for the first LED array 408, the second LED array 410, and the third LED array 412.
  • a LED+ output from the converter PCB 404 may be connected to a positive output of the two channel driver 402.
  • the LED+ output may be connected to anode ends of the first LED array 408, the second LED array 410, and the third LED array 412.
  • a first input current may be I I and a second input current may be 12.
  • the output currents may be Iww for warm white (WW) LEDs, INW for neutral white (NW) LEDs, and lew for cool white (CW) LEDs.
  • WW warm white
  • NW neutral white
  • CW cool white
  • the WW channel may receive a current equal to the difference between I I and 12, while the NW channel may receive twice the amount of current of 12.
  • the sum of Iww and INW may still be 11+12. It should be noted that the actual sum may be slightly less than 11+12 as part of the total current is used to power the interface currents channeling circuit.
  • the interface currents channeling circuit makes use of various analog techniques, such as voltage sensing, low-pass filter and analog signal subtraction. All voltages shown in the diagram refer to the ground.
  • the converter PCB may control currents flowing through WW LEDs and CW LEDs using voltage controlled current sources. In addition, the converter PCB may perform only on/off control on current flowing through NW LEDs.
  • the WW LEDs and the CW LEDs may have CCTs that are on the ends of a desired tunable range.
  • the NW LEDs may have a CCT that is located approximately in the middle of the desired tunable range.
  • the first input current I I may be connected to a first sense resistor (Rs) 502.
  • the second input current 12 may be connected to a second Rs 504.
  • the first Rs 502 and the second Rs 504 may have the same resistance value.
  • a first diode Dl 506 may prevent the first input current II from injecting into the second input current 12.
  • a second diode D2 508 may prevent the second input current 12 from injecting into the first input current II.
  • the first Rs 502 and the second Rs 504 may share one common terminal V c , which may be connected to the anodes of a first LED string 510 that includes WW LEDs, a second LED string 512 that includes NW LEDs, and a third LED string 514 that includes CW LEDs.
  • the voltages at V a and Vb are representative of the currents flowing through the first Rs 502 and the second Rs 504 with a common-mode component, which is the voltage at V c .
  • the voltage at Vb may be attenuated by a resistive divider that includes a first resistor (Rl) 516 and a second resistor (R2) 518.
  • the resulting signal may be sent through a first low-pass filter (LPF) 520 to generate Vbb in a low voltage domain.
  • Vbb may be defined as:
  • V bb LPF(V b x a), Equation (3) where a is an attenuation factor, which may be defined as:
  • the voltage at V a may be attenuated by a resistive divider that includes a first resistor (Rl) 522 and a second resistor (R2) 524.
  • the first resistor (Rl) 522 may be the same value as the first resistor (Rl) 516 and the second resistor (R2) may be the same value as the second resistor (R2) 518.
  • the resulting signal may be sent through a second LPF 526 to generate V aa in a low voltage domain.
  • the second LPF 526 may perform the same operations as the first LPF 520.
  • V aa may be defined as:
  • V aa LPF(V a x a), Equation (5) where a is the attenuation factor defined above in Equation (4).
  • Vbb may be fed to a first operational amplifier (opamp) 528 that is configured to perform subtraction between Vbb and V aa .
  • the outputs of the first opamp 528 may be Vww.
  • V aa may be fed to a second opamp 530 that is configured to perform subtraction between V aa and Vbb.
  • the output of the second opamp 530 may be Vcw.
  • Vcw may be defined as:
  • Vcw (Vbb - Vaa) x ⁇ , Equation (10) where ⁇ is defined above in Equation (7).
  • R3 and R4 may have the same values in the first computational circuit 560 and the second computational circuit 562.
  • Vcw may also be defined as:
  • V cw (72 - 71) x R s x a ⁇ ⁇ . Equation (11)
  • the current Iww may therefore be defined as:
  • the Vww may be fed to a voltage controlled current source, which may be implemented with a first amphfier (amp) 536.
  • the first amp 536 may output a voltage V gl .
  • the voltage V gl may be input to a first transistor Ml that is used to provide a driving current for the first LED string 510.
  • the first transistor Ml may be a conventional metal oxide semiconductor field effect transistor (MOSFET).
  • the first transistor Ml may be an n-channel MOSFET.
  • the first amp 536 may regulate the voltage V gl in a closed loop such that current flowing through the first transistor Ml is equal to Vww/Rs.
  • the inputs to the first amp 536 may be very close to each other in a closed loop regulation.
  • the first amp 306 may compare the value of Vww to the sensed voltage across Rs 564 at the source of the first transistor Ml.
  • the Rs 564 may have the same resistance value as the first Rs 502 and/or the second Rs 504.
  • the first amp 306 may raise V gl to increase the current in the first transistor Ml until the sensed voltage is approximately equal to Vww Likewise, if the sensed voltage is higher than Vww, the first amp 306 may reduce V gl , which may reduce the current in the first transistor Ml.
  • the Vcw may be fed to the voltage controlled current source, which may be implemented with a second amp 538.
  • the second amp 538 may output a voltage V g 2.
  • the voltage V g 2 may be input to a third transistor M3 that is used to provide a driving current for the third LED string 514.
  • the third transistor M3 may be a conventional metal oxide semiconductor field effect transistor (MOSFET).
  • the third transistor M3 may be an n-channel MOSFET.
  • the second amp 538 may regulate the voltage V g 2 in a closed loop such that current flowing through the third transistor M3 is equal to Vcw/Rs.
  • the inputs to the second amp 538 may be very close to each other in a closed loop regulation.
  • the second amp 538 may compare the value of Vcw to the sensed voltage across Rs 566 at the source of the third transistor M3.
  • the Rs 566 may have the same resistance value as the first Rs 502 and/or the second Rs 504.
  • the second amp 538 may raise V g 2 to increase the current in the third transistor M3 until the sensed voltage is approximate equal to Vcw Likewise, if the sensed voltage is higher than Vcw, the second amp 538 may reduce V g 2, which may reduce the current in the third transistor M3.
  • 538 may be clamped to zero when the difference between its inputs is negative.
  • a second transistor M2 may control power to the second LED string 512.
  • the second transistor M2 may be a conventional metal oxide semiconductor field effect transistor (MOSFET).
  • the second transistor M2 may be an n-channel MOSFET.
  • the second transistor M2 may only be switched on when both the first input current II and the second input current 12 are in regulation.
  • the second transistor M2 may have a pull up resistor (R7) 544 tied to Vc.
  • the pull up resistor (R7) 544 may be tied to the node Vc because, at startup, the low voltage supply VDD may not be available. As a result, the first transistor Ml and the third transistor M3 would be in an off state.
  • the second transistor M2 which provides a driving current for the second LED string 512, is also off, the whole circuit would appear as open- circuit to the current sources. This may trigger open-circuit protection and lead to a non-startup condition. By tying the gate of M2 to the node Vc, it may provide a current path available at startup.
  • the current produced by the voltage controlled current sources for the first LED string 510 and the third LED string 514 may be slightly larger than the absolute value of (11-12). This may ensure that the second LED string 512 is off when either II or 12 carries zero current. In other words, only one string of LEDs at either endpoint of the desired tuning range may be on at a time.
  • the AND logic of the switching transistor may be realized by the gate control block 532.
  • the gate control block 532 makes use of the fact that the output of the first amp 536 (V gl ) and the output of the second amp 538 (V g 2) in a voltage controlled current source may swing to its supply rail (VDD) if it is unable to maintain regulation.
  • the VDD may be chosen in such a way that the voltages V gl and V g 2 are significantly lower than VDD when the first amp 536 and the second amp 538 are in regulation under all operating conditions.
  • the V gl may be attenuated by resistive dividers that include a first resistor (R5) 540 and a second resistor (R6) 542, and then fed to a REF input of a first shunt regulator 570.
  • the V g 2 may be attenuated by resistive dividers that include a first resistor (R5) 574 and a second resistor (R6) 576, and then fed to a REF input of a second shunt regulator 572.
  • the first resistor (R5) 540 and the second resistor (R6) 542 may be the same value as the first resistor (R5) 574 and the second resistor (R6) 576 V g 2.
  • the first shunt regulator 570 and the second shunt regulator 572 may have an internal reference voltage of 2.5V. When the voltage applied at their REF nodes is higher than 2.5V, the first shunt regulator 570 and the second shunt regulator 572 may sink a large current. When the voltage applied at their REF nodes is lower than 2.5V, the first shunt regulator 570 and the second shunt regulator 572 may sink a very small quiescent current.
  • the large sinking current may pull the gate voltage of the second transistor M2 down to a level below its threshold, which may switch off the second transistor M2.
  • the first shunt regulator 570 and the second shunt regulator 572 may not be able to pull their cathodes more than the Vf of a diode below their REF nodes. Accordingly, the second transistor M2 may have a threshold voltage that is higher than 2V.
  • a shunt regulator with a lower internal reference voltage, such as 1.5V may be used.
  • Vgi and V g 2 would be maximum around 3V
  • the VDD may be set to be 5V and the attenuation factor may be set to 0.6.
  • the shunt regulator may draw a minimum current and the gate of the second transistor M2 may be pulled high towards the VDD. If either the first amp 536 or the second amp 538 is out of regulation, the shunt regulator may switch off the NMOS.
  • step 602 the first input current II may be received from the first channel 412 of the two channel LED driver 402.
  • step 604 a second input current 12 may be received from the second channel 414 of the two channel LED driver 402.
  • step 606 a ratio of the first input current II to the second input current 12 may be determined.
  • step 608 the first input current II and the second input current 12 may be converted to a first output current, a second output current, and a third output current based on the ratio.
  • the first output current may be provided to a first LED array 510 having a CCT at approximately an end of a desired CCT range
  • the second output current may be provided to a second LED array 516 having a CCT at approximately an opposite end of the desired CCT range
  • the third output current may be provided to a third LED array 514 having a CCT in approximately a middle of a desired CCT range.
  • the method shown in FIG. 6 may be performed by the interface currents channeling circuit.
  • the interface currents channeling circuit may include a first sense resistor 502 to sense a first input voltage from a first input current 12 from a first channel 412 of a two channel LED driver 402.
  • a second sense resistor 504 may sense a second input voltage of a second input current 12 from a second channel 414 of the two channel LED driver 402.
  • the first sense resistor 502 and the second sense resistor 504 are tied to a common node V c .
  • a first computational circuit 560 may be configured to subtract the second input voltage from the first input voltage to generate a first output voltage to power a first LED array 510 having a CCT at approximately an end of a desired CCT range.
  • a second computational circuit 562 may be configured to subtract the first input voltage from the second input voltage to generate a second output voltage to power a second LED array 516 having a CCT at approximately an opposite end of the desired CCT range.
  • a gate control block 532 may be configured to generate a third output voltage to power a third LED array 514 having a CCT in approximately a middle of a desired CCT range if the first input current 11 and the second input current 12 are both in regulation.
  • Examples of computer-readable storage media include, but are not limited to, a read only memory (ROM), a random access memory (RAM), a register, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, and optical media such as CD- ROM disks, and digital versatile disks (DVDs).
  • ROM read only memory
  • RAM random access memory
  • register cache memory
  • semiconductor memory devices magnetic media such as internal hard disks and removable disks, magneto-optical media, and optical media such as CD- ROM disks, and digital versatile disks (DVDs).

Landscapes

  • Circuit Arrangement For Electric Light Sources In General (AREA)

Abstract

Selon la présente invention, un circuit de canalisation de courants d'interface peut être utilisé pour convertir deux canaux de courant d'un circuit d'attaque à deux canaux classique en trois courants d'attaque pour les trois chapelets de DEL. Ainsi, le même circuit d'attaque à deux canaux peut être utilisé pour des applications nécessitant seulement deux réseaux de DEL ainsi que trois réseaux de DEL.
EP18738426.8A 2017-07-02 2018-06-29 Un procédé de syntonisation cct à large gamme qui suit la ligne de corps noirauxmoyen de deux canaux de courant commandés indépendamment et trois ccts Active EP3649833B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/640,549 US10716183B2 (en) 2017-07-02 2017-07-02 Method for wide-range CCT tuning that follows the black body line using two independently controlled current channels and three CCTs
EP17183711 2017-07-28
PCT/US2018/040217 WO2019010074A1 (fr) 2017-07-02 2018-06-29 Procédé de réglage de température de couleur corrélée à large bande qui suit la ligne de corps noir à l'aide de deux canaux de courant commandés indépendamment et de trois températures de couleur corrélées

Publications (2)

Publication Number Publication Date
EP3649833A1 true EP3649833A1 (fr) 2020-05-13
EP3649833B1 EP3649833B1 (fr) 2021-08-11

Family

ID=62846259

Family Applications (1)

Application Number Title Priority Date Filing Date
EP18738426.8A Active EP3649833B1 (fr) 2017-07-02 2018-06-29 Un procédé de syntonisation cct à large gamme qui suit la ligne de corps noirauxmoyen de deux canaux de courant commandés indépendamment et trois ccts

Country Status (6)

Country Link
EP (1) EP3649833B1 (fr)
JP (1) JP6903174B2 (fr)
KR (1) KR102216534B1 (fr)
CN (1) CN110999539B (fr)
TW (1) TWI756446B (fr)
WO (1) WO2019010074A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114271028B (zh) * 2019-06-27 2023-04-11 亮锐有限责任公司 调暗变暖led电路
CN115996499B (zh) * 2022-11-28 2025-12-09 杰华特微电子股份有限公司 Led驱动电路及led照明系统
WO2024113160A1 (fr) * 2022-11-29 2024-06-06 Bridgelux, Inc. Dispositifs d'éclairage accordables à température de couleur

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8796952B2 (en) * 2011-03-03 2014-08-05 Cree, Inc. Semiconductor light emitting devices having selectable and/or adjustable color points and related methods
US9232587B2 (en) * 2011-09-30 2016-01-05 Advanced Analogic Technologies, Inc. Low cost LED driver with integral dimming capability
DE102012207185A1 (de) * 2012-04-30 2013-10-31 Zumtobel Lighting Gmbh Anordnung zur Erzeugung von weißem Licht mit einstellbarer Farbtemperatur
EP2741582B1 (fr) * 2012-12-04 2017-08-09 LEDVANCE GmbH Circuit convertisseur
US9133990B2 (en) * 2013-01-31 2015-09-15 Dicon Fiberoptics Inc. LED illuminator apparatus, using multiple luminescent materials dispensed onto an array of LEDs, for improved color rendering, color mixing, and color temperature control
US9320097B2 (en) 2013-05-10 2016-04-19 Marvell World Trade Ltd. Multi-string dimmable LED driver
JP2015018693A (ja) * 2013-07-11 2015-01-29 パナソニック株式会社 照明器具、照明装置および発光モジュール
US9618162B2 (en) * 2014-04-25 2017-04-11 Cree, Inc. LED lamp
US10278250B2 (en) * 2014-05-30 2019-04-30 Cree, Inc. Lighting fixture providing variable CCT
CN205610985U (zh) * 2016-04-06 2016-09-28 普诚科技股份有限公司 电流控制电路

Also Published As

Publication number Publication date
CN110999539A (zh) 2020-04-10
KR102216534B1 (ko) 2021-02-16
KR20200016394A (ko) 2020-02-14
JP2020526876A (ja) 2020-08-31
CN110999539B (zh) 2021-04-06
TW201918119A (zh) 2019-05-01
EP3649833B1 (fr) 2021-08-11
WO2019010074A1 (fr) 2019-01-10
JP6903174B2 (ja) 2021-07-14
TWI756446B (zh) 2022-03-01

Similar Documents

Publication Publication Date Title
US11700679B2 (en) Method for wide-range CCT tuning that follows the black body line using two independently controlled current channels and three CCTs
US11172558B2 (en) Dim-to-warm LED circuit
US11240895B2 (en) Hybrid driving scheme for RGB color tuning
US8159125B2 (en) Color temperature adjustable lamp
US8319455B2 (en) Colorizer and method of operating the same
US10588194B1 (en) Arbitrary-ratio analog current division circuit
US20220369435A1 (en) Wireless color tuning for constant-current driver
EP3649833B1 (fr) Un procédé de syntonisation cct à large gamme qui suit la ligne de corps noirauxmoyen de deux canaux de courant commandés indépendamment et trois ccts
US9961739B2 (en) Controller for a lamp
US9603218B1 (en) Controlled color transition
CN114271028B (zh) 调暗变暖led电路
TW202027557A (zh) 任意比率類比電流分配電路及電流分配方法
JP2024030939A (ja) 発光装置
WO2020243202A1 (fr) Accord de couleur sans fil pour un conducteur à courant constant
Lee et al. Color enhancement of TV picture using RGB sensor

Legal Events

Date Code Title Description
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: UNKNOWN

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE

PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20200203

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

DAV Request for validation of the european patent (deleted)
DAX Request for extension of the european patent (deleted)
REG Reference to a national code

Ref country code: DE

Ref legal event code: R079

Ref document number: 602018021702

Country of ref document: DE

Free format text: PREVIOUS MAIN CLASS: H05B0033080000

Ipc: H05B0045200000

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: GRANT OF PATENT IS INTENDED

RIC1 Information provided on ipc code assigned before grant

Ipc: H05B 45/20 20200101AFI20210413BHEP

INTG Intention to grant announced

Effective date: 20210428

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE PATENT HAS BEEN GRANTED

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602018021702

Country of ref document: DE

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

Ref country code: AT

Ref legal event code: REF

Ref document number: 1420739

Country of ref document: AT

Kind code of ref document: T

Effective date: 20210915

REG Reference to a national code

Ref country code: LT

Ref legal event code: MG9D

REG Reference to a national code

Ref country code: NL

Ref legal event code: MP

Effective date: 20210811

REG Reference to a national code

Ref country code: AT

Ref legal event code: MK05

Ref document number: 1420739

Country of ref document: AT

Kind code of ref document: T

Effective date: 20210811

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210811

Ref country code: RS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210811

Ref country code: HR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210811

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210811

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210811

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20211213

Ref country code: NO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20211111

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210811

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210811

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20211111

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210811

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210811

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20211112

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210811

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210811

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602018021702

Country of ref document: DE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SM

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210811

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210811

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210811

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210811

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210811

Ref country code: AL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210811

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20220512

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210811

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210811

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210811

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

REG Reference to a national code

Ref country code: BE

Ref legal event code: MM

Effective date: 20220630

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20220629

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20220630

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20220629

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20220630

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20220630

P01 Opt-out of the competence of the unified patent court (upc) registered

Effective date: 20230530

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210811

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210811

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO

Effective date: 20180629

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210811

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210811

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20250626

Year of fee payment: 8

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20250617

Year of fee payment: 8

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20250624

Year of fee payment: 8