EP3593380A1 - Puce electronique - Google Patents
Puce electroniqueInfo
- Publication number
- EP3593380A1 EP3593380A1 EP17748817.8A EP17748817A EP3593380A1 EP 3593380 A1 EP3593380 A1 EP 3593380A1 EP 17748817 A EP17748817 A EP 17748817A EP 3593380 A1 EP3593380 A1 EP 3593380A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- bars
- buried
- detection circuit
- electronic chip
- chip according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims description 20
- 238000002347 injection Methods 0.000 claims description 13
- 239000007924 injection Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 3
- 230000008054 signal transmission Effects 0.000 claims description 3
- 238000010884 ion-beam technique Methods 0.000 description 7
- 230000010287 polarization Effects 0.000 description 5
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 239000002800 charge carrier Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/57—Protection from inspection, reverse engineering or tampering
- H01L23/576—Protection from inspection, reverse engineering or tampering using active circuits
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2607—Circuits therefor
- G01R31/2637—Circuits therefor for testing other individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
- H01L29/365—Planar doping, e.g. atomic-plane doping, delta-doping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
Definitions
- the present application relates to electronic chips, and in particular electronic chips secured against hacker attacks.
- Chips containing confidential information are susceptible to hacker attacks to determine the operation of the chip and to extract the confidential information. To make such attacks, the hacker has several methods.
- fault injection attack the pirate scans the surface of the chip in operation with a laser beam that disrupts the activity of the chip.
- the observation of the consequences of these disturbances, called faults, allows the pirate to carry out his attack.
- the hacker can also make contacts on the chip and apply potentials.
- the hacker may also have a coil near the surface of the chip to emit electromagnetic interference.
- the pirate can burn part of the back side of an electronic chip. From the engraved part, the pirate can use an ion beam to burn cavities of a few micrometers in diameter to circuit elements located on the front face. These elements may be components such as transistors, diodes, or conductive tracks connecting these components. After creating electrical contacts through these cavities, the pirate operates the chip to carry out its attack.
- an embodiment provides an electronic chip comprising a plurality of buried doped bars and comprising a circuit for detecting an anomaly of an electrical characteristic of the bars.
- the bars are of a first type of conductivity and are buried in a substrate of a second conductivity type under the lower level of boxes of the first conductivity type, electronic circuit elements being formed in and on the substrate and in and on the caissons.
- each end of each buried bar is provided with a contact.
- the bars are buried under an overdoped region of conductivity type opposite to the conductivity type of the bars.
- the buried bars are connected in series between first and second nodes, the chip further comprising a circuit for detecting an electrical discontinuity between the first and second nodes.
- the discontinuity detection circuit is adapted to apply a signal on the first node and to detect the absence of signal transmission on the second node.
- the chip comprises a carrier injection detection circuit adapted to bias the buried bars connected to each other and to detect an anomaly of the bias current of the buried bars.
- the chip comprises a resistive element traversed by the bias current and a circuit for detecting a voltage across the resistive element.
- the chip comprises a circuit for detecting a resistance value anomaly between two end contacts of each buried bar.
- each of the buried bars has a contact coupled to a source of current, a reference potential being applied to another contact of the bar, the chip further comprising for each of the bars a detection circuit of a anomaly of the voltage between the contacts of the bar.
- said detection circuit comprises a discontinuity detection circuit, a carrier injection detection circuit, and a resistance variation detection circuit.
- step a) comprises a boron implantation at a dose of between 1.5 * 10 12 and 2.5 * 10 12 ions / cm 2 with an energy greater than 3500 keV.
- the method further comprises a step a1) of forming, above the level of the buried bars, an overdoped region of the second type of conductivity.
- Figure 1 is a partial schematic perspective view of an embodiment of an electronic chip protected against attacks
- FIGS. 2 and 3 detail examples of detection circuits coupled to buried bars
- Figure 4 details a detection circuit connected to a buried bar
- FIG. 5 schematically represents a chip combining the detection circuits described with reference to FIGS. 2, 3 and 4.
- FIG. 1 is a partial schematic perspective view of an embodiment of an electronic chip protected against attacks.
- the chip comprises a p-type doped semiconductor substrate 3 including N-type doped portions.
- the other elements of the chip are not shown in FIG. 1.
- N-type doped boxes 5 are situated in the upper part of the substrate 3. In the example shown, the boxes 5 form parallel strips separated by P-type portions 7.
- the substrate 3 is connected to a ground GND whose potential serves as a reference.
- Unrepresented elements of electronic circuits of the chip, such as transistors interconnected by conductive tracks, are formed in and on the caissons 5 and the portions 7.
- the circuits are for example logic circuits which contain wished confidential information. by a pirate.
- the chip comprises N-type doped bars 9, buried in the substrate 3, parallel and arranged at regular intervals below the lower level of the boxes 5.
- the bars are separated from the boxes 5 by portions 10 of the substrate.
- Each buried bar 9 is thus separated from the other bars 9 and caissons 5 by P type doped portions.
- Each of the two ends of each bar 9 is surmounted by an N-type doped contact zone 11 which connects the bar to the upper surface of the substrate.
- Each contact zone 11 is provided with a contact 13.
- the buried bars 9 are arranged between two levels located at depths included between 1 and 5 ym below the upper surface.
- the bars 9 may be oriented in a direction perpendicular to the direction of the strips formed by the boxes or may be oriented in another direction.
- the bars 9 have a horizontal dimension perpendicular to their orientation, or width, between 1 and 5 ⁇ m.
- the width of the space between the bars 9 can be between 1 and 5 ⁇ m.
- the buried bars 9 may be formed by ion implantation before the contact zones 11 and the caissons 5 are formed.
- the buried bars 9 are obtained by implantation of boron at a dose of between 1 , 5 * 1 ⁇ 12 and 2.5 * 1 ⁇ 12 ions / cm 2 with an energy greater than 3500 keV.
- all of the parts 10 can be the target of an additional P-type doping for the buried regions are created on-doped P-type doping ⁇ portions 10 ensures more safety that the bars 9 are separated from the caissons 5 by P type doped regions.
- the additional doping can be obtained by ion implantation of phosphorus at a dose of between 1.5 * 10 12 and 2.5 * 10 12 ions / cm 2 and with an energy between 4500 and 5500 keV.
- the buried caissons can be connected to different detection circuits included in the chip. These detection circuits are detailed in the following figures.
- FIG. 2 details an example of a discontinuity detection circuit 17 coupled to the buried bars 9.
- the buried bars 9 are represented in plan view provided with the contact zones 11 and the contacts 13.
- the buried bars 9 are connected in series between 13A and 13B contacts by links 15 arranged between contacts 13 of neighboring bars 9.
- the detection circuit 17 comprises a flip-flop 20 whose clock input CLK is coupled to the contact 13A.
- a positive potential V DD is applied to the data input D of the flip-flop 20.
- the output Q of the flip-flop 20 is coupled to a Process circuit input (PROC) 22.
- Pulse generating circuit (PULSE) 24 has an output 26 coupled to contact 13B.
- the circuits 22 and 24 are activated by a TEST1 signal.
- the signal TEST1 is activated during a test phase.
- the test phase takes place for example during a boot phase of the chip.
- the output of the flip-flop 20 and the output of the pulse generation circuit 24 are at a low level.
- the pulse generation circuit 24 momentarily applies a high potential level to the contact 13A.
- the processing circuit 22 activates an alert signal A1 if the potential at the output of the flip-flop 20 is always at the low level.
- the high potential level momentarily applied to the contact 13A constitutes a pulse signal which is found on the clock input of the flip-flop.
- the potential at the output of the rocker goes to a high level and remains at this level in the rest of the test phase. No Al signal is therefore emitted during the test phase. Outside the test phase, the processing circuit 22 is deactivated and no signal A1 is emitted.
- the pirate makes an opening 28 of a few micrometers in width to access elements of the chip circuits located on the front side.
- the widths of the bars 9 and the spaces between the bars 9 are smaller than the width of the opening 28, and thus the opening 28 interrupts at least one of the buried bars 9 and creates a discontinuity therein.
- the pirate makes the chip work.
- the TEST1 signal is activated.
- the pulse signal is not transmitted to the negative input, which causes the transmission of a signal Al.
- the detection circuit 17 thus detects an electrical discontinuity in the bars 9 connected in series.
- the signal Al is used by the chip to take countermeasures such as suspending or stopping its activity or destroying confidential information contained therein.
- the chip is therefore protected against focused ion beam attacks.
- FIG. 3 details an example of a charge carrier injection detection circuit 32 coupled to buried bars 9 represented in a view from above.
- the buried bars 9 are connected in series by links 15 between contacts 13A and 13B.
- the contact 13B is not connected.
- the detection circuit 32 comprises:
- a switch 34 coupling the contact 13A with a node 36 and controlled by a signal TEST2;
- a resistor 35 located between the node 36 and a node 38 on which a VDD potential is applied;
- a comparator 42 whose positive input is coupled to node 36 and the negative input is coupled to node 38;
- a comparator 44 whose positive input is coupled to the node 38 and the negative input is coupled to the node 36;
- the comparators 42 and 44 being fed between the potential VDD and the mass.
- the signal TEST2 is activated.
- the switch 34 is on, and the buried bars 9 are biased to the potential VDD through the resistor 35.
- the substrate 3 is connected to ground, the PN junctions between the bars 9 and the substrate are blocked. As a result, no current flowing to or from the bars, or bias current, flows into the resistor 35.
- Each of the comparators 42 and 44 is designed so that its output is not activated when its inputs are at the same potential, and no signal A2 is produced.
- the laser beam causes photoinjection of carriers into an illuminated portion of PN junction between the bars 9 and the substrate 3.
- a bias current then flows through the resistor 35 and causes the emission of the alert signal A2.
- the alert signal A2 can be used to stop the chip or destroy confidential information.
- the operation of the carrier injection detection circuit 32 is identical to protect the chip against the injection of faults by a pirate who applies potentials to contacts added to the chip or which causes electromagnetic disturbances by means of a coil. .
- the comparators 42 and 44 detect a voltage across the resistor 35. When a fault produces a bias current from the bars 9, the comparator 42 is the origin of a signal A2. When a polarization current caused by a fault flows towards the bars 9, the comparator 44 detects this current and a signal A2 appears.
- the chip is advantageously protected against any type of fault injection attack carried out by the injection of charge carriers.
- FIG. 4 represents a buried bar 9 connected to a resistance variation detection circuit 50.
- the chip may comprise a detection circuit for each buried bar.
- the ends of the bar 9 are provided with 13C and 13D contacts.
- the detection circuit 50 comprises:
- a switch 52 coupling the contact 13C to ground GND;
- a switch 54 coupling the contact 13D to a node 56;
- a comparator 62 whose positive input is coupled to the node 56 and whose negative input is an application node of a threshold potential.
- the current source 58 and the switches 52 and 54 are controlled by a signal TEST3.
- the output of the comparator 62 corresponds to an alert signal A3.
- the comparator 62 detects an anomaly of the voltage between the end contacts of the bar.
- a test phase is planned during the start of the chip. During the test phase, each TEST3 signal is activated successively. When the signal TEST3 of a detection circuit is activated, a current is injected by the current source 58 into the buried bar 9 connected to the circuit.
- the resistance of the buried bar 9 is such that the voltage drop between the contacts 13C and 13D remains below the threshold. No signal is emitted.
- FIG. 5 shows buried bars 9 connected to a combination of the discontinuity detection, carrier injection and resistance value variation circuits previously described.
- Each buried bar 9 has its ends coupled to a detection circuit 50 (DET3) of a variation of the resistance of the bar.
- the buried bars 9 can be connected in series between a contact 13A and a contact 13B by a set of switches 72.
- the contact 13A is coupled to a detection circuit 32 (DET2) of an anomaly of the polarization current of the bars 9
- a switch 74 couples the contact 13B to a detection circuit 17 (DET1) of an electrical discontinuity of the bars 9 between the contacts 13A and 13B.
- the switches 72 When starting the chip, in a first step, the switches 72 are turned on and the TEST1 signal is activated. In a second step, the switches 72 are open to isolate each bar 9 and TEST3 signals are activated successively. During operation of the chip, the switches 72 are turned on and the test signal TEST2 is activated to protect the chip.
- the pirate modifies an electrical characteristic of all the bars or one of the bars, this characteristic being an electrical continuity, a polarization current or the value of a resistance.
- a detection circuit By detecting an anomaly of this electrical characteristic, a detection circuit emits an alert signal to counter the attempted attack.
- the chip is thus advantageously protected against all types of attacks by injection of faults and against attacks by focused ion beam.
- the elements dedicated to the security of the chip occupy the surface of two detection circuits 17 and 32 for the entire chip and a circuit 50 of very simple structure for each of the bars. So the part of the surface of the chip dedicated to security is advantageously reduced, and may represent less than 1% of the chip surface.
- detection circuits detect anomalies of electrical continuity, polarization current and electrical resistance.
- chips may be equipped with anomaly detection circuits of other electrical characteristics of the buried bars, which may be modified during attempted attacks.
- a P-type doped substrate contains N-type doped buried bars 9 located below the wells, it is possible to reverse the conductivity types. The essential thing is that each buried bar is separated from the other bars and caissons by regions of a conductivity type opposite to that of the bars.
- the circuit 32 detects an anomaly of the bias current of buried bars connected in series, it is possible, as an alternative, to connect together the buried bars of any what other way, for example in parallel.
- each buried bar 9 is connected to a dedicated detection circuit 50
- a common detection circuit is successively coupled to several bars. buried, or in which a detection circuit detects an anomaly of the resistance of several bars connected in series.
- a resistance anomaly is detected by a detection circuit 50 when the resistance of a buried bar 9 is greater than a threshold.
- a resistance anomaly is detected by a circuit common to two buried bars when the difference between the resistances of the two bars is greater than a threshold.
- the buried bars are connected in series by links.
- these bonds can be replaced by doped portions of the same type as the buried bars, these portions being able to be buried and formed simultaneously with the buried bars.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Automation & Control Theory (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/FR2017/050519 WO2018162805A1 (fr) | 2017-03-09 | 2017-03-09 | Puce electronique |
Publications (1)
Publication Number | Publication Date |
---|---|
EP3593380A1 true EP3593380A1 (fr) | 2020-01-15 |
Family
ID=59523172
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP17748817.8A Pending EP3593380A1 (fr) | 2017-03-09 | 2017-03-09 | Puce electronique |
Country Status (3)
Country | Link |
---|---|
US (1) | US10685923B2 (fr) |
EP (1) | EP3593380A1 (fr) |
WO (1) | WO2018162805A1 (fr) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR3081240B1 (fr) | 2018-05-15 | 2021-08-06 | St Microelectronics Rousset | Puce electronique |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20080007813A (ko) * | 2006-07-18 | 2008-01-23 | 삼성전자주식회사 | 박막 트랜지스터 어레이 기판 |
FR2946775A1 (fr) * | 2009-06-15 | 2010-12-17 | St Microelectronics Rousset | Dispositif de detection d'amincissement du substrat d'une puce de circuit integre |
EP2369622B1 (fr) | 2010-03-24 | 2015-10-14 | STMicroelectronics Rousset SAS | Procédé et dispositif de contremesure contre une attaque par injection d'erreur dans un microcircuit électronique |
JP2011258693A (ja) * | 2010-06-08 | 2011-12-22 | Panasonic Corp | 保護回路と半導体装置及び電子機器 |
FR2998419B1 (fr) * | 2012-11-21 | 2015-01-16 | St Microelectronics Rousset | Protection d'un circuit integre contre des attaques |
US9768128B2 (en) * | 2014-01-29 | 2017-09-19 | Infineon Technologies Ag | Chip and method for detecting an attack on a chip |
US9231403B2 (en) * | 2014-03-24 | 2016-01-05 | Texas Instruments Incorporated | ESD protection circuit with plural avalanche diodes |
FR3041814A1 (fr) | 2015-09-30 | 2017-03-31 | Stmicroelectronics Rousset | Circuit integre securise |
CN105575948A (zh) * | 2015-11-09 | 2016-05-11 | 北京中电华大电子设计有限责任公司 | 一种芯片保护方法和系统 |
FR3050317A1 (fr) * | 2016-04-19 | 2017-10-20 | Stmicroelectronics Rousset | Puce electronique |
-
2017
- 2017-03-09 EP EP17748817.8A patent/EP3593380A1/fr active Pending
- 2017-03-09 WO PCT/FR2017/050519 patent/WO2018162805A1/fr unknown
-
2018
- 2018-03-08 US US15/916,183 patent/US10685923B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
WO2018162805A1 (fr) | 2018-09-13 |
US20180261560A1 (en) | 2018-09-13 |
US10685923B2 (en) | 2020-06-16 |
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