EP3584971B1 - Procédé de codage, procédé de décodage, appareil et dispositif - Google Patents

Procédé de codage, procédé de décodage, appareil et dispositif Download PDF

Info

Publication number
EP3584971B1
EP3584971B1 EP18766823.1A EP18766823A EP3584971B1 EP 3584971 B1 EP3584971 B1 EP 3584971B1 EP 18766823 A EP18766823 A EP 18766823A EP 3584971 B1 EP3584971 B1 EP 3584971B1
Authority
EP
European Patent Office
Prior art keywords
bit
value
frozen
check
cyclic shift
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
EP18766823.1A
Other languages
German (de)
English (en)
Other versions
EP3584971A4 (fr
EP3584971A1 (fr
Inventor
Yue Zhou
Huazi ZHANG
Rong Li
Hejia LUO
Yunfei Qiao
Jun Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Publication of EP3584971A1 publication Critical patent/EP3584971A1/fr
Publication of EP3584971A4 publication Critical patent/EP3584971A4/fr
Application granted granted Critical
Publication of EP3584971B1 publication Critical patent/EP3584971B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0009—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the channel coding
    • H04L1/0013—Rate matching, e.g. puncturing or repetition of code symbols
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H04L1/0043—Realisations of complexity reduction techniques, e.g. use of look-up tables
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0052—Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H04L1/0058—Block-coded modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0064—Concatenated codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching

Definitions

  • This application relates to communications technologies, and in particular, to a coding method, a decoding method, an apparatus, and a device.
  • a polar code (Polar Codes) is a new type of channel coding proposed by E. Ankan in 2008.
  • the polar code is designed based on channel polarization (Channel Polarization), and is a first constructive coding scheme that can be proven, by using a strict mathematical method, to reach a channel capacity.
  • the polar code is a linear block code.
  • Polar codes for control channels are compared in QUALCOMM INCORPORATED, "Comparison of Polar codes for control channel", vol. RAN WG1, Athens, Greece; 20170213-20170217, (20170212), 3GPP DRAFT; R1-1702645 .
  • NTT DOCOMO "Discussion on Polar codes design", vol. RAN WG1, Spokane, USA; 20170116-20170120, (20170116), 3GPP DRAFT; Rl-1700867 discusses polar code designs.
  • the current invention provides a coding method, a decoding method, a coding apparatus, a decoding apparatus, and corresponding computer readable media, according to the independent claims, so that a receive end can perform error correction on a coded bit sequence through coding by using a polar code.
  • Advantageous embodiments of the current invention are specified in the dependent claims.
  • a first aspect of this application provides a coding method, according to independent claim 1.
  • the sending device namely, a coding side
  • a receiving device namely, a decoding side
  • This solution may be used for information exchange between a terminal and a network device, or may be used for information exchange between terminals. This is not limited in this solution.
  • PC coding and CRC coding are uniformly performed by using a common CRC hardware resource, to simplify time complexity, space complexity, and calculation complexity of a coding algorithm, and implement parallel coding.
  • the cyclic shift register is a CRC register.
  • each frozen check bit is a value of a bit in a cyclic shift process of the cyclic shift register, or a value of each frozen check bit is a preset value.
  • the value of the frozen check bit may be a value of a bit that is a most significant bit in the cyclic shift process of the cyclic shift register; or may be a value of any bit in the cyclic shift process of the cyclic shift register.
  • the coding, by the sending device, the to-be-encoded information bit includes: sequentially assigning, by the sending device, values to the coded bit sequence based on a location of the information bit, a location of the frozen bit, a location of the CRC check bit, and a location of the frozen check bit, where an operation is as follows:
  • the method when there is a CRC check bit before the frozen check bit, the method further includes: updating the cyclic shift feedback register based on a value of the CRC check bit.
  • the updating a value of a bit in the cyclic shift register based on a value of the information bit includes:
  • the method further includes: updating a value of a bit in the cyclic shift feedback register based on a value of the frozen check bit.
  • the method further includes: updating a value of a bit in the cyclic shift feedback register based on a value of the frozen bit.
  • the value of the bit in the cyclic shift process of the cyclic shift register is obtained from the cyclic shift register by using a multiplexer.
  • a value is obtained from the cyclic shift feedback register, and is used as a value of the frozen check bit for value assignment includes:
  • that the value of the frozen check bit is obtained from the cyclic shift register by using the multiplexer includes:
  • a second aspect of this application provides a decoding method, according to independent claim 4.
  • the receiving device may be a network device or may be a terminal.
  • CRC decoding and a PC check are uniformly performed by using a common CRC hardware resource, to simplify space complexity, time complexity, and calculation complexity of a decoding algorithm, and reduce a decoding latency.
  • the cyclic shift register is a CRC register.
  • each frozen check bit there is at least one frozen check bit, and a check value of each frozen check bit is a value of a bit in a cyclic shift process of the cyclic shift register, or a value of each frozen check bit is a preset value.
  • the decoding and checking, by the receiving device, the to-be-decoded sequence to obtain an information bit sequence includes: sequentially performing, by the receiving device, polar decoding and a check on the to-be-decoded sequence in order from a least significant bit to a most significant bit based on a location of the information bit, a location of the frozen bit, a location of the CRC check bit, and a location of the frozen check bit, where an operation is as follows:
  • the method when there is a CRC check bit before the frozen check bit, the method further includes: updating the cyclic shift feedback register based on a value that is of the CRC check bit and that is obtained through decoding.
  • the updating a value of a bit in the cyclic shift register based on a value that is of the information bit and that is obtained through decoding includes: updating values of bits in the cyclic shift register by using values that are of information bits and that are obtained through decoding in order from a least significant bit to a most significant bit.
  • the method further includes: updating the cyclic shift feedback register based on the value that is of the frozen check bit and that is obtained through decoding.
  • the method further includes: updating the cyclic shift feedback register based on the fixed frozen value obtained through decoding.
  • the value of the bit in the cyclic shift process of the cyclic shift register is obtained from the cyclic shift register by using a multiplexer.
  • the checking a value that is of the frozen check bit and that is obtained through decoding and an obtained check value of the frozen check bit when a to-be-decoded bit is a frozen check bit includes:
  • that the check value of the frozen check bit is obtained from the cyclic shift register by using the multiplexer includes:
  • a third aspect of this application provides a coding apparatus, according to independent claim 7.
  • the cyclic shift register is a CRC register.
  • each frozen check bit is a value of a bit in a cyclic shift process of the cyclic shift register, or a value of each frozen check bit is a preset value.
  • the processing module is specifically configured to: sequentially assign values to the coded bit sequence based on a location of the information bit, a location of the frozen bit, a location of the CRC check bit, and a location of the frozen check bit, where an operation is as follows:
  • the processing module when there is a CRC check bit before the frozen check bit, is further configured to update the cyclic shift feedback register based on a value of the CRC check bit.
  • the processing module is specifically configured to:
  • the processing module is further configured to update a value of a bit in the cyclic shift feedback register based on a value of the frozen check bit.
  • the processing module is further configured to update a value of a bit in the cyclic shift feedback register based on a value of the frozen bit.
  • the value of the bit in the cyclic shift process of the cyclic shift register is obtained from the cyclic shift register by using a multiplexer.
  • a fourth aspect of this application provides a decoding apparatus, according to independent claim 10.
  • the cyclic shift register is a CRC register.
  • each frozen check bit there is at least one frozen check bit, and a check value of each frozen check bit is a value of a bit in a cyclic shift process of the cyclic shift register, or a value of each frozen check bit is a preset value.
  • the processing module is specifically configured to: sequentially perform polar decoding and a check on the to-be-decoded sequence in order from a least significant bit to a most significant bit based on a location of the information bit, a location of the frozen bit, a location of the CRC check bit, and a location of the frozen check bit, where an operation is as follows:
  • the processing module when there is a CRC check bit before the frozen check bit, is further configured to update the cyclic shift feedback register based on a value that is of the CRC check bit and that is obtained through decoding.
  • the processing module is specifically configured to update values of bits in the cyclic shift register by using values that are of information bits and that are obtained through decoding in order from a least significant bit to a most significant bit.
  • the processing module is further configured to update the cyclic shift feedback register based on the value that is of the frozen check bit and that is obtained through decoding.
  • the processing module is further configured to update the cyclic shift feedback register based on the fixed frozen value obtained through decoding.
  • the value of the bit in the cyclic shift process of the cyclic shift register is obtained from the cyclic shift register by using a multiplexer.
  • the processing module may be specifically implemented as a processor, the sending module may be implemented as a transmitter, and the receiving module may be implemented as a receiver.
  • a fifth aspect of this application provides a storage medium including a readable storage medium and a computer program.
  • the computer program is used to implement the coding method according to any implementation of the first aspect.
  • a processor of a sending device the sending device further including a memory, a transmitter, and the computer program stored in the memory, runs the computer program, the sending device performs the coding method according to any implementation of the first aspect.
  • the sending device there is at least one processor, configured to execute an executable instruction, namely, the computer program, stored in the memory, so that the sending device exchanges data with a receiving device by using a communications interface, to perform the coding method according to the first aspect or the implementations of the first aspect.
  • the memory may be alternatively integrated into the processor.
  • a sixth aspect of this application provides a storage medium including a readable storage medium and a computer program.
  • the computer program is used to implement the coding method according to any implementation of the first aspect.
  • a processor of a receiving device the receiving device further including a memory, a receiver, and the computer program stored in the memory, runs the computer program, the receiving device performs the decoding method according to any implementation of the second aspect.
  • the receiving device there is at least one processor, configured to execute an executable instruction, namely, the computer program, stored in the memory, so that the receiving device exchanges data with a sending device by using a communications interface, to perform the decoding method according to the second aspect or the implementations of the second aspect.
  • the memory may be alternatively integrated into the processor.
  • a seventh aspect of this application provides a storage medium, including a readable storage medium and a computer program.
  • the computer program is used to implement the coding method according to any implementation of the first aspect.
  • An eighth aspect of this application provides a storage medium, including a readable storage medium and a computer program.
  • the computer program is used to implement the decoding method according to any implementation of the second aspect.
  • a ninth aspect of this application provides a program product, where the program product includes a computer program (namely, an executable instruction), and the computer program is stored in a readable storage medium.
  • At least one processor of a sending device may read the computer program from the readable storage medium, and the at least one processor executes the computer program, so that the sending device implements the coding method according to the first aspect or the implementations of the first aspect.
  • a tenth aspect of this application provides a program product, where the program product includes a computer program (namely, an executable instruction), and the computer program is stored in a readable storage medium.
  • At least one processor of a receiving device may read the computer program from the readable storage medium, and the at least one processor executes the computer program, so that the receiving device implements the decoding method according to the second aspect or the implementations of the second aspect.
  • the sending device obtains the to-be-encoded information bit sequence; the sending device codes the to-be-encoded information bit to obtain the coded bit sequence, where the coded bit sequence includes the information bit, the frozen bit, the CRC check bit, and the frozen check bit; and the value of the frozen check bit and the value of the CRC check bit are obtained by using a same cyclic shift register; the sending device performs polar coding and rate matching on the coded bit sequence to obtain the to-be-sent rate-matched sequence; and the sending device sends the rate-matched sequence.
  • the frozen check bit and a CRC are simultaneously coded by using a same cyclic shift register; and for corresponding decoding, decoding and a check may also be simultaneously performed by using a same cyclic shift register, to perform early path selection, thereby effectively reducing time and space for coding calculation and decoding calculation, and reducing calculation complexity.
  • the technical solutions of the embodiments of this application may be applied to a 5G communications system or a future communications system, and may also be applied to various other communications systems such as a global system for mobile communications (Global System for Mobile, GSM) system, a code division multiple access (CDMA, Code Division Multiple Access) system, a wideband code division multiple access (Wideband Code Division Multiple Access, WCDMA) system, a general packet radio service (General Packet Radio Service, GPRS) system, a long term evolution (Long Term Evolution, LTE) system, an LTE frequency division duplex (Frequency Division Duplex, FDD) system, an LTE time division duplex (Time Division Duplex, TDD) system, and a universal mobile telecommunications system (Universal Mobile Telecommunications System, UMTS).
  • GSM Global System for Mobile
  • CDMA Code Division Multiple Access
  • WCDMA Wideband Code Division Multiple Access
  • GPRS General Packet Radio Service
  • LTE Long Term Evolution
  • FDD Frequency Division Duplex
  • FIG. 1 is a basic schematic flowchart of commonly used wireless communication.
  • information from an information source is transmitted after source coding, channel coding, and digital modulation are sequentially performed.
  • the information is output from an information destination after digital demodulation, channel decoding, and source decoding are sequentially performed.
  • a polar code may be used for channel coding.
  • SC decoding, SCL decoding, or the like may be used for channel decoding.
  • CA-polar code a PC-polar code
  • CA+PC-polar code that are obtained through improvement based on the polar code are further proposed.
  • FIG. 2a is a schematic flowchart of commonly used coding performed by concatenating a CA-polar code and a PC-polar code. As shown in FIG. 2a , the following steps are sequentially performed: (1) Perform concatenated cyclic redundancy check (Cyclic Redundancy Check, CRC) coding on to-be-encoded information bits a 0 , a 1 , a 2 , ..., a A -1 to obtain b 0 , b 1 , ..., b B-1 ; (2) Perform PC coding, to be specific, set a value of an information bit, a value of a static frozen bit, and a value of a frozen check bit based on a determined location of the information bit, a determined location of the frozen bit, and a determined location of the frozen check bit, to generate a sequence c 0 , c 1 , ..., c C -1 ; (3) Perform polar coding (namely, polar coding) to obtain a sequence
  • a CRC coding matrix is uniquely determined by using the following parameters: a quantity of CRC check bits, a location of the CRC check bit, and a CRC check equation.
  • the PC coding is determined by using the following parameters: the location of the frozen check bit and a check equation.
  • Implementation steps of a polar coding method in which a CRC is concatenated are as follows: A location of an information bit, a location of a frozen bit, and a location of a check bit are first determined. Then CRC coding is performed on to-be-encoded information bits. In other words, CRC calculation is performed (A represents an information bit length, and B represents a sum of the information bit length and a CRC check bit length). For the CRC calculation, an input is information bits a 0 , a 1 , a 2 , ..., a A -1 , and generated check bits are p 0 , p 1 , p 2 , ..., p Kcrc -1 . The CRC coding is performed in the following manner to obtain b 0 , b 1 , ..., b B-1 , where
  • a value of the information bit, a value of the frozen bit, and a value of the frozen check bit are set in the CRC-coded sequence b 0 , b 1 , . , b B-1 obtained through CRC coding.
  • the value of the information bit, the value of the frozen bit, and the value of the frozen check bit may be set in the following manner, to obtain a sequence c 0 , c 1 , ..., c C -1 (C represents a sequence length obtained after the value of the information bit, the value of the frozen bit, and the value of the frozen check bit are set.
  • C is equal to a mother code length N)
  • rate matching is performed.
  • a sequence that is not to be transmitted is removed from the sequence d 0 , d 1 , d 2 , ..., d D -1 , to obtain a to-be-transmitted sequence e 0 , e 1 , e 2 , ..., e E -1 , where E represents a length of the rate-matched sequence, namely, a code length.
  • E represents a length of the rate-matched sequence, namely, a code length.
  • the CRC coding and the PC coding are separately performed, and there are the following several problems: (1) There is a sequence between operations, and this is inconvenient for parallel processing; (2) A check equation of each check bit and a value of the check bit need to be determined by a separate hardware unit; (3) Time complexity, space complexity, and calculation complexity of an algorithm are affected.
  • FIG. 2b is a schematic diagram of decoding of commonly used coding performed by concatenating a CA-polar code and a PC-polar code.
  • an SCL first decodes a polar code and outputs L survivor paths (L is a parameter); then a CRC check is performed on the survivor paths; and a path on which the CRC succeeds is selected as a decoding output. If there is no path on which the CRC check succeeds, the decoding fails, and a path having a maximum probability may be selected as an output; and if there is more than one path on which the CRC check succeeds, a path having a maximum probability is selected from the path as an output.
  • L is a parameter
  • this application provides a technical solution for resolving the problems in coding and decoding.
  • the coding method and the decoding method provided in this application are described below in detail with reference to the accompanying drawings.
  • FIG. 3 is a schematic diagram of an application system of a coding method and a decoding method according to this application. As shown in FIG. 3 , this solution is applied to an information exchange process between a network device and a terminal.
  • a coding side may be the network device or the terminal; and correspondingly, a decoding side may be the terminal or the network device.
  • this solution may alternatively be applied to an information exchange process between terminals. This is not limited in this solution.
  • FIG. 4 is an interaction flowchart of a coding method and a decoding method according to this application. As shown in FIG. 4 , specific implementation steps of the coding method and the decoding method are as follows:
  • the sending device codes the obtained information bit sequence in same hardware (cyclic shift register), to be specific, assigns values to the CRC check bit, the frozen check bit, and the frozen bit when coding the information bit, to obtain the coded sequence.
  • S103 The sending device performs polar coding and rate matching on the coded bit sequence to obtain a to-be-sent rate-matched sequence.
  • S104 The sending device sends the rate-matched sequence.
  • the sending device sends the rate-matched sequence that is obtained after performing polar coding and rate matching on the coded sequence that is obtained after assigning the values to the CRC check bit, the frozen check bit, and the frozen bit.
  • a receiving device receives the rate-matched sequence sent by the sending device.
  • S105 The receiving device performs rate de-matching processing on the rate-matched sequence to obtain a to-be-decoded sequence.
  • the receiving device decodes and checks the to-be-decoded sequence to obtain an information bit sequence, where the to-be-decoded sequence includes an information bit, a frozen bit, a CRC check bit, and a frozen check bit; and a check value of the frozen check bit and a check value of the CRC check bit are obtained by using a same cyclic shift register.
  • the receiving device performs polar decoding on the to-be-decoded sequence obtained after rate de-matching processing.
  • the receiving device may check, based on a location of the frozen check bit and a location of the CRC check bit, the check value of the frozen check bit and the check value of the CRC check bit that are obtained by using the same cyclic shift register, to complete early selection of a decoding path without performing checks one by one after decoding.
  • frozen check bit coding and CRC coding are performed simultaneously by using a same cyclic shift register; and for corresponding decoding, decoding and a check are also simultaneously performed by using a same cyclic shift register, to perform early path selection, thereby effectively reducing time and space for coding calculation and decoding calculation, and reducing calculation complexity.
  • FIG. 5 is a specific schematic flowchart of a coding method according to this application.
  • a coding side device namely, a sending device, may perform coding by using the following several steps.
  • Step 1 Determine a location.
  • the coding side device determines a location of an information bit, a location of a frozen bit, and a location of an assistant bit based on an obtained to-be-encoded information length K (namely, a length of a to-be-encoded information bit sequence), a coded information length M, and an assistant bit length.
  • Assistant bits include a CRC bit and a PC bit.
  • a J-bit CRC used for error detection and error correction, a J' 1-bit CRC only used for error correction, and a J' 2-bit PC only used for error correction may be selected based on an actual application situation.
  • step 1 becomes optional. In other words, the coding side device may not perform step 1.
  • Step 2 Set a value of an information bit, a value of a frozen bit, and a value of an assistant bit.
  • a value of an information bit, a value of a frozen bit, and a value of an assistant bit in a to-be-encoded information bit sequence a 0 , a 1 , ..., a A-1 are set based on a determined location of the information bit, a determined location of the frozen bit, and a determined location of the assistant bit, to obtain a sequence b 0 , b 1 , ..., b B -1 .
  • the sequence b 0 , b 1 , ..., b B -1 in this solution is different from the bits b 0 , b 1 , ..., b B -1 in FIG. 2a .
  • the sequence b 0 , b 1 , ..., b B -1 in this solution is a sequence obtained after CRC coding and PC coding. Specifically, coding may be performed in the following manner:
  • Assistant bits (such as a CRC bit or a frozen check bit) are uniformly set by using a unified hardware resource (for example, a cyclic shift feedback register).
  • a unified hardware resource for example, a cyclic shift feedback register.
  • An implementation form of the hardware resource also determines a check equation of the frozen check bit.
  • Step 3 Perform polar coding (polar coding) on a sequence b 0 , b 1 , ..., b B -1 obtained after assisted coding, to obtain a sequence c 0 , c 1 , ..., c C -1 .
  • Step 4 Perform rate matching on the polar-coded sequence c 0 , c 1 , ..., c C -1 , to obtain a sequence d 0 , d 1 , ..., d D -1 .
  • the coding side device may send the obtained rate-matched sequence to a receiving device, namely, a decoding side device for decoding.
  • FIG. 6 is a specific schematic flowchart of a decoding method according to this application.
  • a decoding side device namely, a receiving device, may perform decoding by using the following several steps.
  • Step 1 Perform rate de-matching.
  • Rate de-matching processing is performed based on a sequence d 0 , d 1 , ..., d D -1 and a puncturing scheme, to recover a sequence c 0 , c 1 , ..., c C -1 .
  • Step 2 Determine a location.
  • a location of an information bit, a location of a frozen bit, and a location of an assistant bit are determined.
  • Assistant bits include a CRC bit and a PC bit. This step may be performed before a rate-matched sequence is received, or may be performed after a rate-matched sequence is received. This is not limited in this solution.
  • Step 3 Perform decoding.
  • the decoding side device when performing bit-by-bit decoding by using polar decoding (polar decoding) based on the determined location of the information bit, the determined location of the frozen bit, and the determined location of the assistant bit, decoding side device decodes and checks the assistant bit by using a unified hardware resource (for example, a cyclic shift feedback register), to implement early selection, early termination, and final screening of a decoding path, and obtain an information bit sequence a 0 , a 0 , ..., a A -1 .
  • a unified hardware resource for example, a cyclic shift feedback register
  • PC coding and CRC coding are uniformly performed by using a common CRC hardware resource, to simplify time complexity, space complexity, and calculation complexity of a coding algorithm, and implement parallel coding.
  • CRC decoding and a PC check are uniformly performed by using a common CRC hardware resource, to simplify space complexity, time complexity, and calculation complexity of a decoding algorithm and reduce a decoding latency.
  • Step S102 shown in FIG. 4 may be specifically implemented as follows:
  • the sending device sequentially assigns values to the coded bit sequence based on a location of the information bit, a location of the frozen bit, a location of the CRC check bit, and a location of the frozen check bit.
  • An operation is as follows:
  • the cyclic shift register is a shift register corresponding to a predetermined polynomial.
  • the polynomial is preconfigured in the sending device and the receiving device, or the polynomial is a polynomial determined by the sending device and the receiving device based on an agreement. A same polynomial is used for coding and decoding.
  • the polynomial is used to represent an operation structure of a cyclic shift feedback register that performs an assistant bit operation.
  • a CRC check value obtained from the cyclic shift register is assigned to the CRC check bit.
  • a value corresponding to a bit in the cyclic shift feedback register is assigned to the frozen check bit.
  • a to-be-encoded bit is a frozen bit
  • a fixed value is assigned to the frozen bit.
  • the cyclic shift feedback register is any one of a plurality of cyclic shift feedback registers (also referred to as cyclic feedback shift registers) corresponding to the polynomial.
  • the cyclic shift feedback register may be a register that performs calculation by using only an input, or may be a register that performs calculation by using both an input and an output, or may be a register that performs calculation by using an output.
  • the cyclic shift feedback register is unique in a processing procedure. The same is true for the receiving device side.
  • the cyclic shift feedback register needs to be consistent with a cyclic shift feedback register used by the receiving device.
  • the cyclic shift feedback register is a CRC register.
  • each frozen check bit is a value of a bit in a cyclic shift process of the cyclic shift register, or a value of each frozen check bit is a preset value.
  • the sending device when the to-be-encoded bit is the CRC check bit, and the CRC check bit is interleaved with the frozen check bit, in other words, there is one or more CRC check bits before the frozen check bit, the sending device further updates the cyclic shift feedback register based on a value that is of the CRC check bit and that is obtained through coding, in other words, uses the value of the CRC check bit as an input into the cyclic shift feedback register for updating.
  • the value of the bit in the cyclic shift register is updated based on the value of the information bit
  • Information values start to be filled into the information bit sequence from a most significant bit or a least significant bit, and the cyclic shift feedback register is updated based on the information values. This is specifically implemented in the following two manners:
  • Implementation 1 Update values of bits in the cyclic shift register in order from the most significant bit to the least significant bit based on the information bit. This means that the information bit sequence starts to be coded from the most significant bit, and when each information value is input, the cyclic shift feedback register shifts from the least significant bit to the most significant bit.
  • Implementation 2 Update values of bits in the cyclic shift register in order from the least significant bit to the most significant bit based on the information bit. This means that the information bit sequence starts to be coded from the least significant bit, and when each information value is input, the cyclic shift feedback register shifts from the most significant bit to the least significant bit.
  • the sending device may further update a value of a bit in the cyclic shift feedback register based on a value of the frozen check bit.
  • the sending device may further update a value of a bit in the cyclic shift feedback register based on a value of the frozen bit.
  • a value is obtained from the cyclic shift feedback register and is used as a value of the frozen check bit, and there are at least the following several implementations:
  • each frozen check bit is the value of the bit in the cyclic shift process of the cyclic shift register, or the value of each frozen check bit is a preset value, for example, 0 or 1.
  • the value of the bit in the cyclic shift process of the cyclic shift register is obtained from the cyclic shift register by using the multiplexer.
  • the sending device starts to sequentially read a value from the least significant bit in the cyclic shift feedback register by using the multiplexer, and uses the value as the value of the frozen check bit; or starts to sequentially read a value from the most significant bit in the cyclic shift feedback register by using the multiplexer, and uses the value as the value of the frozen check bit; or starts to sequentially read a value from a data input bit in the cyclic shift feedback register by using the multiplexer, and uses the value as the value of the frozen check bit; or starts to sequentially read a value from a preset bit in the cyclic shift feedback register by using the multiplexer, and uses the value as the value of the frozen check bit; or obtains a value from the cyclic shift feedback register in a pseudo-random form by using the multiplexer and an interleaved sequence, and uses the value as the value of the frozen check bit.
  • which manner is to be used may be preconfigured or pre-agreed on.
  • Step S106 shown in FIG. 4 may be specifically implemented as follows:
  • the receiving device sequentially performs polar decoding and a check on the to-be-decoded sequence in order from a least significant bit to a most significant bit based on a location of the information bit, a location of the frozen bit, a location of the CRC check bit, and a location of the frozen check bit.
  • An operation is as follows:
  • a value of a bit in the cyclic shift register is updated based on a value that is of the information bit and that is obtained through decoding.
  • a polynomial is a polynomial preconfigured in the sending device and the receiving device, or a polynomial determined by the sending device and the receiving device based on an agreement.
  • a same polynomial is used for coding and decoding, and an operation structure of a cyclic shift feedback register that performs an assistant bit operation may be represented by using a polynomial.
  • a to-be-decoded bit is a CRC check bit
  • a CRC check value obtained through decoding and a check value that is of the CRC bit and that is obtained from the cyclic shift register are checked.
  • a to-be-decoded bit is a frozen check bit
  • a value that is of the frozen check bit and that is obtained through decoding and an obtained check value of the frozen check bit are checked, and the check value of the frozen check bit is a value corresponding to a bit in the cyclic shift feedback register.
  • a to-be-decoded bit is a frozen bit
  • a fixed frozen value is obtained through decoding.
  • the cyclic shift feedback register is any one of a plurality of cyclic shift feedback registers (also referred to as cyclic feedback shift registers) corresponding to a preset polynomial.
  • cyclic shift feedback registers also referred to as cyclic feedback shift registers
  • the cyclic shift feedback register is unique in a processing procedure.
  • the cyclic shift feedback register needs to be consistent with a cyclic shift feedback register used by the sending device.
  • the cyclic shift feedback register is a CRC register.
  • an information value obtained through decoding is filled into the cyclic shift feedback register corresponding to the polynomial, and the cyclic shift feedback register is updated based on the information value.
  • An assistant decoding sequence starts to be decoded from the least significant bit, and when each information value is filled, the information value is used as an input into the cyclic shift feedback register, so that the cyclic shift feedback register shifts from the most significant bit to the least significant bit.
  • another possible implementation of updating the cyclic shift feedback register based on the information value is: starting to decode an assistant decoding sequence from a most significant bit, and when each information value is filled, using the information value as an input into the cyclic shift feedback register, so that the cyclic shift feedback register shifts from a least significant bit to the most significant bit.
  • the receiving device updates the cyclic shift feedback register based on the value that is of the CRC check bit and that is obtained through decoding.
  • the receiving device may further update the cyclic shift feedback register based on the value that is of the frozen check bit and that is obtained through decoding.
  • the cyclic shift feedback register is updated based on the fixed frozen value obtained through decoding.
  • each frozen check bit is a value of a bit in a cyclic shift process of the cyclic shift register, or a value of each frozen check bit is a preset value.
  • the check value of the frozen check bit may be a value of a bit that is a most significant bit in the cyclic shift process of the cyclic shift register; or may be a value of any bit in the cyclic shift process of the cyclic shift register.
  • the value of the bit in the cyclic shift process of the cyclic shift register is obtained from the cyclic shift register by using a multiplexer.
  • the value that is of the frozen check bit and that is obtained through decoding and the obtained check value of the frozen check bit are checked in at least the following several implementations:
  • the receiving device checks the value that is of the frozen check bit and that is obtained through decoding and a check value that is of the frozen check bit and that is obtained by starting to sequentially read from the least significant bit in the cyclic shift feedback register by using the multiplexer; or checks the value that is of the frozen check bit and that is obtained through decoding and a check value that is of the frozen check bit and that is obtained by starting to sequentially read from the most significant bit in the cyclic shift feedback register by using the multiplexer; or checks the value that is of the frozen check bit and that is obtained through decoding and a check value that is of the frozen check bit and that is obtained by starting to sequentially read from the data input bit in the cyclic shift feedback register by using the multiplexer; or checks the value that is of the frozen check bit and that is obtained through decoding and a check value that is of the frozen check bit and and
  • a process in which a selected cyclic shift feedback register (for example, a CRC register) performs coding on a coding side is used as an example to describe the solutions provided in this application in the following.
  • a selected cyclic shift feedback register for example, a CRC register
  • step 2 on a coding side in FIG. 5 may be described as follows:
  • Assistant bits include a J 2 ⁇ bit ′ PC and a ( J + J 1 ′ )-bit CRC, where J bits are used for error correction and error detection, ( J + J 1 ′ ) bits are only used for error correction, and J, J' 1 , and J' 2 are nonnegative integers.
  • a unified coder of a sending device sequentially assigns values to a sequence b from a least significant bit to a most significant bit.
  • This implementation may be implemented by using a plurality of types of program code, and this is not limited in this solution.
  • the foregoing solution is described below by using a specific implementation. Pseudo code of this implementation is described as follows:
  • FIG. 7 is a schematic diagram of an information bit input into a CRC register according to an example of this application.
  • a CRC polynomial X16+X12+X5+1 is used as an example.
  • a structure of a CRC register corresponding to the polynomial is shown in FIG. 7 .
  • a to-be-input information bit starts to be input from a most significant bit.
  • the CRC register cyclically shifts from a least significant bit to the most significant bit.
  • the example CRC polynomial in FIG. 7 is corresponding to a plurality of CRC registers.
  • a specific structure of a register may be pre-agreed on by a sending device and a receiving device; or a configuration in which any CRC register is selected as a register used in a coding process and a decoding process is provided in a sending device and a receiving device.
  • the sending device performs coding from the most significant bit to the least significant bit (optionally, from the least significant bit to the most significant bit) based on the information bit.
  • a to-be-encoded bit is an information bit
  • a value of the information bit is used as an input into the register in FIG.
  • an exclusive OR operation is performed based on the structure of the register, and the register shifts forward, to be specific, the register shifts from the least significant bit to the most significant bit.
  • a to-be-encoded bit is a frozen check bit
  • a value is read from any location in the CRC register and is used as a value of the frozen check bit.
  • a value assignment operation is performed by reading the value from the most significant bit 15 in the CRC register and using the value as the frozen check value.
  • FIG. 8 is a schematic diagram of another information bit input into a CRC register according to an example of this application.
  • An information bit starts to be input from a least significant bit, and the CRC register shifts from a most significant bit to the least significant bit.
  • a CRC polynomial is an inverse form of an original polynomial.
  • an inverse form of X16+X12+X5+1 is X16+X10+X3+1.
  • the CRC register is shown in FIG. 8 .
  • a value is read from any location in the CRC register and is used as the frozen check value.
  • a value assignment operation is performed by reading the value from the most significant bit 15 in the CRC register and using the value as the frozen check value.
  • FIG. 9 is a schematic diagram of a frozen check bit input into a CRC register according to an example of this application.
  • FIG. 10 is a schematic diagram of another frozen check bit input into a CRC register according to an example of this application.
  • the CRC register is defined by using an inverse CRC polynomial X16+X10+X3+1, and a value of the 12 th bit in the register is permanently selected as a frozen check value.
  • the CRC register is defined by using a CRC polynomial X16+X12+X5+1, and a value of the eighth bit in the register is permanently selected as a frozen check value.
  • FIG. 11 is a schematic diagram of selecting a frozen check bit input into a CRC register by using a multiplexer according to an example of this application.
  • a multiplexer Multiple User Experiment, MUX
  • the multiplexer may use without limitation to the following methods:
  • Round-robin may be expressed as follows: When a first bit that needs to be fed back is encountered, a value is obtained from a specified location in the register, and then a next value in the register is obtained in sequence (or in an inverse sequence) for a subsequent bit that needs to be fed back. If the most significant bit (Most Significant bit, MSB) (in the inverse sequence, the least significant bit (Least Significant Bit, LSB)) is encountered, a next location in the register is set to the LSB (in the inverse sequence, a next location in the register is set to the MSB).
  • MSB most significant bit
  • LSB least significant bit
  • the interleaved sequence is a sequence of selecting values from the register based on a sequence S, and S may be a pseudo-random sequence.
  • FIG. 12 to FIG. 14 are schematic diagrams of a general-purpose register according to an example of this application.
  • the CRC register in any one of the foregoing implementations may be a general-purpose polynomial register, and features of the CRC register may be described as follows:
  • a value of a most significant bit is input, the input value may be fed back, and a value of the most significant bit may be fed back to a non-least significant bit.
  • a polynomial X16+X12+X5+1 is still used as an example, and an implementation form is shown in FIG. 12 .
  • a value of a least significant bit is input, the input value may participate in an exclusive OR XOR operation, and a value of the most significant bit cannot be fed back to a non-least significant bit.
  • a polynomial X16+X12+X5+1 is still used as an example, and an implementation form is shown in FIG. 13 .
  • a value of a least significant bit is input, the input value may participate in an exclusive OR XOR operation, and a value of the most significant bit may be fed back to a non-least significant bit.
  • a polynomial X16+X12+X5+1 is still used as an example, and an implementation form is shown in FIG. 14 .
  • FIG. 15 is a schematic diagram of a shift signal generation apparatus of a register according to an example of this application.
  • shifting may occur only in a process of interaction with an information bit and a CRC bit.
  • a shifting action of the shift register needs to be triggered by a clock signal.
  • a determining module first determines whether interaction data is an information bit. If the interaction data is an information bit, the clock signal normally passes through an AND (AND) gate, and a shifting operation of the shift register is triggered; or if the interaction data is not an information bit, the clock signal cannot pass through an AND gate, and the register performs no shifting operation.
  • AND AND
  • FIG. 16 is a schematic diagram of a shift signal generation apparatus of another register according to an example of this application.
  • a difference from the solution shown in FIG. 15 is that in this solution, in a coding process or a decoding process, a structure of the polynomial register shifts when the register interacts with any bit.
  • a shifting action is performed on the structure of the polynomial cyclic shift feedback register, for example, according to the solution in FIG. 16 .
  • the polynomial cyclic shift feedback register interacts with an information bit, the information bit is input into an input location to participate in an exclusive OR operation.
  • a value of a frozen bit is selected according to the foregoing solutions shown in FIG. 9 to FIG. 11 , and the value is fed back to an input end of the polynomial cyclic shift feedback register to participate in an exclusive OR operation.
  • FIG. 17 is a schematic diagram of another frozen check bit input into a register according to an example of this application.
  • the eighth bit in the register is permanently selected as a value of a frozen check bit.
  • the frozen check bit interacts with a polynomial cyclic shift feedback register, a value of a fixed bit is filled into the frozen check bit, and participates in an exclusive OR operation of an input into the cyclic feedback shift register.
  • a method for filling the frozen check bit is a distributed CRC generation method.
  • a manner of interaction with a polynomial register in a decoding process is similar to that on a coding side.
  • the distributed CRC may be used to perform an early check, to implement early path screening and early path termination.
  • a 16-bit register is used as an example to describe the coding method and the decoding method provided in this application.
  • a quantity of bits in the register may be 1 to infinity
  • a commonly used coding register and a commonly used decoding register may be 16-bit to 24-bit cyclic feedback shift registers.
  • PC coding and CRC coding are uniformly performed by using a common CRC hardware resource, to simplify time complexity, space complexity, and calculation complexity of a coding algorithm, and implement parallel coding.
  • CRC decoding and a PC check are uniformly performed by using a common CRC hardware resource, to simplify space complexity, time complexity, and calculation complexity of a decoding algorithm, and reduce a decoding latency.
  • a CRC-polar code in which a CRC is used for error detection and error correction and a PC-polar code in which a CRC is only used for error detection and a PC is used only for error correction are used together, to not only implement early path screening and termination of polar decoding, but also ensure FAR performance of decoding.
  • the PC is used to set an assistant check bit and a CRC register is used to generate check bit information, so that a distributed CRC can be quickly generated.
  • FIG. 18 is a schematic structural diagram of a coding apparatus according to this application. As shown in FIG. 18 , the coding apparatus 10 includes a processing module 11 and a sending module 12.
  • the processing module 11 is configured to obtain a to-be-encoded information bit sequence.
  • the processing module 11 is further configured to code the to-be-encoded information bit to obtain a coded bit sequence.
  • the coded bit sequence includes the information bit, a frozen bit, a cyclic redundancy check CRC check bit, and a frozen check bit; and a value of the frozen check bit and a value of the CRC check bit are obtained by using a same cyclic shift register.
  • the processing module 11 is further configured to perform polar coding and rate matching on the coded bit sequence to obtain a to-be-sent rate-matched sequence.
  • the sending module 12 is configured to send the rate-matched sequence.
  • the coding apparatus provided in this embodiment is configured to implement the technical solutions on a sending device side in any one of the foregoing method embodiments. Implementation principles and technical effects thereof are similar. Details are not described herein again.
  • the cyclic shift register is a CRC register.
  • each frozen check bit is a value of a bit in a cyclic shift process of the cyclic shift register, or a value of each frozen check bit is a preset value.
  • the processing module 11 is specifically configured to: sequentially assign values to the coded bit sequence based on a location of the information bit, a location of the frozen bit, a location of the CRC check bit, and a location of the frozen check bit, where an operation is as follows:
  • the processing module 11 is further configured to update the cyclic shift feedback register based on a value of the CRC check bit.
  • processing module 11 is specifically configured to:
  • the processing module 11 is further configured to update a value of a bit in the cyclic shift feedback register based on a value of the frozen check bit.
  • the processing module 11 is further configured to update a value of a bit in the cyclic shift feedback register based on a value of the frozen bit.
  • the value of the bit in the cyclic shift process of the cyclic shift register is obtained from the cyclic shift register by using a multiplexer.
  • the coding apparatus provided in any one of the foregoing embodiments is configured to implement the technical solutions on the sending device side in any one of the foregoing method embodiments. Implementation principles and technical effects thereof are similar. Details are not described herein again.
  • FIG. 19 is a schematic structural diagram of a decoding apparatus according to this application. As shown in FIG. 19 , the decoding apparatus 20 includes:
  • the processing module 22 is further configured to decode and check the to-be-decoded sequence to obtain an information bit sequence, where the to-be-decoded sequence includes an information bit, a frozen bit, a cyclic redundancy check CRC check bit, and a frozen check bit; and a check value of the frozen check bit and a check value of the CRC check bit are obtained by using a same cyclic shift register.
  • the decoding apparatus provided in this embodiment is configured to implement the technical solutions on a receiving device side in any one of the foregoing method embodiments. Implementation principles and technical effects thereof are similar. Details are not described herein again.
  • the cyclic shift register is a CRC register.
  • each frozen check bit is a value of a bit in a cyclic shift process of the cyclic shift register, or a value of each frozen check bit is a preset value.
  • the processing module 22 is specifically configured to: sequentially perform polar decoding and a check on the to-be-decoded sequence in order from a least significant bit to a most significant bit based on a location of the information bit, a location of the frozen bit, a location of the CRC check bit, and a location of the frozen check bit, where an operation is as follows:
  • the processing module 22 is further configured to update the cyclic shift feedback register based on a value that is of the CRC check bit and that is obtained through decoding.
  • the processing module 22 is specifically configured to update values of bits in the cyclic shift register by using values that are of information bits and that are obtained through decoding in order from a least significant bit to a most significant bit.
  • the processing module 22 is further configured to update the cyclic shift feedback register based on the value that is of the frozen check bit and that is obtained through decoding.
  • the processing module 22 is further configured to update the cyclic shift feedback register based on the fixed frozen value obtained through decoding.
  • the value of the bit in the cyclic shift process of the cyclic shift register is obtained from the cyclic shift register by using a multiplexer.
  • the decoding apparatus provided in any one of the foregoing embodiments is configured to implement the technical solution on the receiving device side according to any one of the foregoing method embodiments. Implementation principles and technical effects thereof are similar. Details are not described herein again.
  • the processing module may be specifically implemented as a processor, the sending module may be implemented as a transmitter, and the receiving module may be implemented as a receiver.
  • This application further provides a sending device, including a memory, a processor, a transmitter, and a computer program.
  • the computer program is stored in the memory, and the processor runs the computer program to perform the coding method provided in any one of the foregoing embodiments.
  • the sending device there is at least one processor, and the processor is configured to execute an executable instruction, namely, the computer program, stored in the memory, so that the sending device exchanges data with a receiving device through a communications interface, to perform the coding method provided in any one of the foregoing implementations.
  • the memory may be further integrated into the processor.
  • This application further provides a receiving device, including a memory, a processor, receiver, and a computer program.
  • the computer program is stored in the memory, and the processor runs the computer program to perform the decoding method provided in any one of the implementations.
  • the receiving device there is at least one processor, and the processor is configured to execute an executable instruction, namely, the computer program, stored in the memory, so that the receiving device exchanges data with a sending device through a communications interface, to perform the decoding method provided in any one of the foregoing implementations.
  • the memory may be further integrated into the processor.
  • This application further provides a storage medium, including a readable storage medium and a computer program.
  • the computer program is used to implement the coding method provided in any one of the foregoing embodiments.
  • This application further provides a storage medium, including a readable storage medium and a computer program.
  • the computer program is used to implement the decoding method provided in any one of the foregoing embodiments.
  • This application further provides a program product, the program product includes a computer program (namely, an executable instruction), and the computer program is stored in a readable storage medium.
  • At least one processor of a sending device may read the computer program from the readable storage medium, and the at least one processor executes the computer program, so that the sending device implements the coding method provided in the foregoing implementations.
  • This application further provides a program product, the program product includes a computer program (namely, an executable instruction), and the computer program is stored in a readable storage medium.
  • At least one processor of a receiving device may read the computer program from the readable storage medium, and the at least one processor executes the computer program, so that the receiving device implements the decoding method provided in the foregoing implementations.
  • the processor may be a central processing unit (English: Central Processing Unit, CPU for short), or may be another general-purpose processor, a digital signal processor (English: Digital Signal Processor, DSP for short), an application-specific integrated circuit (English: Application Specific Integrated Circuit, ASIC for short), or the like.
  • the general-purpose processor may be a microprocessor, or the processor may be any conventional processor, or the like.
  • the steps of the methods disclosed with reference to this application may be directly implemented by a hardware processor, or may be implemented by a combination of hardware in the processor and a software module.
  • the memory includes: a read-only memory (English: read-only memory, ROM for short), a RAM, a flash memory, a hard disk, a solid state disk, a magnetic tape (English: magnetic tape), a floppy disk (English: floppy disk), an optical disc (English: optical disc), and any combination thereof.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Error Detection And Correction (AREA)

Claims (14)

  1. Procédé de codage, comprenant :
    l'obtention (S101) d'une séquence de bits d'informations à coder ;
    le codage (S102) de la séquence de bits d'informations à coder pour obtenir une séquence de bits codée, dans lequel la séquence de bits codée comprend un bit d'information, un bit gelé, un bit de contrôle de redondance cyclique, CRC, et un bit de contrôle gelé ; et une valeur du bit de contrôle CRC est obtenue en utilisant un registre à décalage cyclique ;
    un codage polaire (S103) et une adaptation de débit sur la séquence binaire codée pour obtenir une séquence à débit adapté à envoyer ; et
    l'envoi (S104) de la séquence à débit adapté,
    caractérisé en ce que
    une valeur du bit de contrôle gelé est obtenue en utilisant le même registre à décalage cyclique dans lequel le bit de contrôle gelé et le bit CRC sont codés simultanément en utilisant le même registre à décalage cyclique.
  2. Procédé selon la revendication 1, dans lequel il existe au moins un bit de contrôle gelé, et une valeur de chaque bit de contrôle gelé est une valeur d'un bit dans un processus de décalage cyclique du registre à décalage cyclique.
  3. Procédé selon les revendications 1 ou 2, dans lequel le codage (S102) de la séquence de bits d'informations à coder comprend : l'attribution séquentielle de valeurs à la séquence de bits codée sur la base d'un emplacement du bit d'information, d'un emplacement du bit gelé, d'un emplacement du bit de contrôle CRC et d'un emplacement du bit de contrôle gelé, dans lequel une opération est la suivante :
    lorsqu'un bit à coder est un bit d'information, la mise à jour d'une valeur d'un bit dans le registre à décalage cyclique sur la base d'une valeur du bit d'information ; ou
    lorsqu'un bit à coder est un bit de contrôle CRC, l'affectation, au bit de contrôle CRC, d'une valeur de contrôle CRC obtenue à partir du registre à décalage cyclique ; ou
    lorsqu'un bit à coder est un bit de contrôle gelé, l'affectation, au bit de contrôle gelé, d'une valeur correspondant à un bit dans le registre de rétroaction à décalage cyclique ; ou
    lorsqu'un bit à coder est un bit gelé, l'affection d'une valeur fixe au bit gelé.
  4. Procédé de décodage, comprenant :
    la réception (S104) d'une séquence à débit adapté ;
    une désadaptation de débit (S105) sur la séquence à débit adapté pour obtenir une séquence à décoder ; et
    le décodage et le contrôle (S106) de la séquence à décoder pour obtenir une séquence de bits d'informations, dans lequel la séquence à décoder comprend un bit d'information, un bit gelé, un bit de contrôle de redondance cyclique, CRC, et un bit de contrôle gelé ; et une valeur de contrôle du bit de contrôle CRC est obtenue en utilisant un registre à décalage cyclique,
    caractérisé en ce que
    une valeur de contrôle du bit de contrôle gelé est obtenue en utilisant le même registre à décalage cyclique dans lequel le bit de contrôle gelé et le bit CRC sont décodés et contrôlés simultanément en utilisant le même registre à décalage cyclique.
  5. Procédé selon la revendication 4, dans lequel il existe au moins un bit de contrôle gelé, et une valeur de chaque bit de contrôle gelé est une valeur de contrôle d'un bit dans un processus de décalage cyclique du registre à décalage cyclique.
  6. Procédé selon les revendications 4 ou 5, dans lequel le décodage et le contrôle (S106) de la séquence à décoder pour obtenir une séquence de bits d'informations comprend :
    la réalisation séquentielle d'un décodage polaire et d'un contrôle de la séquence à décoder dans l'ordre d'un bit le moins significatif à un bit le plus significatif sur la base d'un emplacement du bit d'information, d'un emplacement du bit gelé, d'un emplacement du bit de contrôle CRC, et d'un emplacement du bit de contrôle gelé, dans lequel une opération est la suivante :
    lorsqu'un bit à décoder est un bit d'information, la mise à jour d'une valeur d'un bit dans le registre à décalage cyclique sur la base d'une valeur qui est du bit d'information et qui est obtenue par décodage ; ou
    lorsqu'un bit à décoder est un bit de contrôle CRC, le contrôle d'une valeur de contrôle CRC obtenue par décodage et d'une valeur de contrôle qui est du bit CRC et qui est obtenue à partir du registre à décalage cyclique ; ou
    lorsqu'un bit à décoder est un bit de contrôle gelé, le contrôle d'une valeur qui est du bit de contrôle gelé et qui est obtenue par décodage et d'une valeur de contrôle obtenue du bit de contrôle gelé, dans lequel la valeur de contrôle du bit de contrôle gelé est une valeur correspondant à un bit dans le registre de rétroaction à décalage cyclique ; ou
    lorsqu'un bit à décoder est un bit gelé, l'obtention d'une valeur gelée fixe par décodage.
  7. Appareil de codage (10), comprenant :
    un module de traitement (11), configuré pour obtenir une séquence de bits d'informations à coder, dans lequel
    le module de traitement (11) est en outre configuré pour coder la séquence de bits d'information à coder pour obtenir une séquence de bits codée, dans lequel la séquence de bits codée comprend un bit d'information, un bit gelé, un bit de contrôle de contrôle de redondance cyclique, CRC, et pour obtenir une valeur du bit de contrôle gelé et une valeur du bit de contrôle CRC en utilisant un registre à décalage cyclique ; et
    le module de traitement (11) est en outre configuré pour effectuer un codage polaire et une adaptation de débit sur la séquence de bits codée pour obtenir une séquence à débit adapté à envoyer ; et
    un module d'envoi (12), configuré pour envoyer la séquence à débit adapté,
    caractérisé en ce que
    le module de traitement (11) est en outre configuré pour obtenir une valeur du bit de contrôle gelé en utilisant le même registre à décalage cyclique dans lequel le module de traitement (11) est configuré pour coder simultanément le bit de contrôle gelé et le bit CRC en utilisant le même registre à décalage cyclique.
  8. Appareil selon la revendication 7, dans lequel il existe au moins un bit de contrôle gelé, et une valeur de chaque bit de contrôle gelé est une valeur d'un bit dans un processus de décalage cyclique du registre à décalage cyclique.
  9. Appareil selon la revendication 7 ou 8, dans lequel le module de traitement (11) est configuré spécifiquement pour :
    attribuer séquentiellement des valeurs à la séquence de bits codée sur la base d'un emplacement du bit d'information, d'un emplacement du bit gelé, d'un emplacement du bit de contrôle CRC et d'un emplacement du bit de contrôle gelé, dans lequel le module de traitement (11) est en outre configuré pour effectuer les opérations suivantes :
    lorsqu'un bit à coder est un bit d'information, mettre à jour une valeur d'un bit dans le registre à décalage cyclique sur la base d'une valeur du bit d'information ; ou
    lorsqu'un bit à coder est un bit de contrôle CRC, affecter, au bit de contrôle CRC, une valeur de contrôle CRC obtenue à partir du registre à décalage cyclique ; ou
    lorsqu'un bit à coder est un bit de contrôle gelé, affecter, au bit de contrôle gelé, une valeur correspondant à un bit dans le registre de rétroaction à décalage cyclique ; ou
    lorsqu'un bit à coder est un bit gelé, affecter une valeur fixe au bit gelé.
  10. Appareil de décodage (20), comprenant :
    un module de réception (21), configuré pour recevoir une séquence à débit adapté ; et
    un module de traitement (22), configuré pour effectuer un traitement de désadaptation de débit sur la séquence à débit adapté pour obtenir une séquence à décoder, dans lequel
    le module de traitement (22) est en outre configuré pour décoder et contrôler la séquence à décoder pour obtenir une séquence de bits d'informations, dans lequel la séquence à décoder comprend un bit d'information, un bit gelé, un bit de contrôle de redondance cyclique, CRC, et un bit de contrôle gelé ; et pour obtenir une valeur de contrôle du bit de contrôle CRC en utilisant un registre à décalage cyclique,
    caractérisé en ce que
    le module de traitement (22) est en outre configuré pour obtenir une valeur de contrôle du bit de contrôle gelé en utilisant le même registre à décalage cyclique dans lequel le module de traitement (22) est en outre configuré pour décoder et contrôler simultanément le bit de contrôle gelé et le bit CRC en utilisant le même registre à décalage cyclique.
  11. Appareil selon la revendication 10, dans lequel il existe au moins un bit de contrôle gelé, et une valeur de contrôle de chaque bit de contrôle gelé est une valeur d'un bit dans un processus de décalage cyclique du registre à décalage cyclique.
  12. Appareil selon la revendication 10 ou 11, dans lequel le module de traitement (22) est configuré spécifiquement pour :
    réaliser séquentiellement un décodage polaire et un contrôle de la séquence à décoder dans l'ordre d'un bit le moins significatif à un bit le plus significatif sur la base d'un emplacement du bit d'information, d'un emplacement du bit gelé, d'un emplacement du bit de contrôle CRC, et d'un emplacement du bit de contrôle gelé, dans lequel le module de traitement (22) est en outre configuré pour réaliser les opérations suivantes :
    lorsqu'un bit à décoder est un bit d'information, la mise à jour d'une valeur d'un bit dans le registre à décalage cyclique sur la base d'une valeur qui est du bit d'information et qui est obtenue par décodage ; ou
    lorsqu'un bit à décoder est un bit de contrôle CRC, le contrôle d'une valeur de contrôle CRC obtenue par décodage et d'une valeur de contrôle qui est du bit CRC et qui est obtenue à partir du registre à décalage cyclique ; ou
    lorsqu'un bit à décoder est un bit de contrôle gelé, le contrôle d'une valeur qui est du bit de contrôle gelé et qui est obtenue par décodage et d'une valeur de contrôle obtenue du bit de contrôle gelé, dans lequel la valeur de contrôle du bit de contrôle gelé est une valeur correspondant à un bit dans le registre de rétroaction à décalage cyclique ; ou
    lorsqu'un bit à décoder est un bit gelé, l'obtention d'une valeur gelée fixe par décodage.
  13. Support de stockage lisible par ordinateur, comprenant un programme informatique qui, lorsqu'il est exécuté par un processeur, amène le processeur à mettre en oeuvre le procédé de codage selon l'une quelconque des revendications 1 à 3.
  14. Support de stockage lisible par ordinateur, comprenant un programme informatique qui, lorsqu'il est exécuté par un processeur, amène le processeur à mettre en oeuvre le procédé de décodage selon l'une quelconque des revendications 4 à 6.
EP18766823.1A 2017-03-13 2018-03-13 Procédé de codage, procédé de décodage, appareil et dispositif Active EP3584971B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710147552.9A CN108574560B (zh) 2017-03-13 2017-03-13 一种编码方法、译码方法、装置和设备
PCT/CN2018/078787 WO2018166431A1 (fr) 2017-03-13 2018-03-13 Procédé de codage, procédé de décodage, appareil et dispositif

Publications (3)

Publication Number Publication Date
EP3584971A1 EP3584971A1 (fr) 2019-12-25
EP3584971A4 EP3584971A4 (fr) 2020-02-26
EP3584971B1 true EP3584971B1 (fr) 2023-11-15

Family

ID=63522758

Family Applications (1)

Application Number Title Priority Date Filing Date
EP18766823.1A Active EP3584971B1 (fr) 2017-03-13 2018-03-13 Procédé de codage, procédé de décodage, appareil et dispositif

Country Status (4)

Country Link
US (1) US11184028B2 (fr)
EP (1) EP3584971B1 (fr)
CN (1) CN108574560B (fr)
WO (1) WO2018166431A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113381838A (zh) * 2020-03-09 2021-09-10 华为技术有限公司 数据传输方法及通信装置
CN113472475B (zh) * 2020-03-30 2022-08-02 大唐移动通信设备有限公司 一种解速率匹配的方法及装置
CN111900999B (zh) * 2020-07-16 2022-11-18 北京航空航天大学 一种面向卫星非连续通信的高性能极化编码方法及编码器
KR102629309B1 (ko) 2021-11-24 2024-01-24 경북대학교 산학협력단 커패시터 리플 감소를 위한 지그재그 변압기를 이용한 3레벨 npc 컨버터
CN117376071A (zh) * 2022-07-08 2024-01-09 华为技术有限公司 调制编码的方法和装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3614592A1 (fr) * 2017-05-02 2020-02-26 Huawei Technologies Co., Ltd. Dispositif et procédé de codage

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9176927B2 (en) * 2011-11-08 2015-11-03 The Royal Institution For The Advancement Of Learning/Mcgill University Methods and systems for decoding polar codes
CN103220001B (zh) * 2012-01-20 2016-09-07 华为技术有限公司 与循环冗余校验级联的极性码的译码方法和译码装置
CN103368583B (zh) * 2012-04-11 2016-08-17 华为技术有限公司 极性码的译码方法和译码装置
KR101710025B1 (ko) * 2013-01-24 2017-02-24 캘리포니아 인스티튜트 오브 테크놀로지 재기록 불능 메모리에서의 결합 재기록 및 에러 정정
US9467164B2 (en) * 2013-10-01 2016-10-11 Texas Instruments Incorporated Apparatus and method for supporting polar code designs
US10135460B2 (en) * 2013-10-01 2018-11-20 Texas Instruments Incorporated Apparatus and method for multilevel coding (MLC) with binary alphabet polar codes
EP3079290B1 (fr) 2014-02-21 2019-04-10 Huawei Technologies Co., Ltd. Procédé et appareil d'adaptation de débit de code polaire
RU2571587C2 (ru) * 2014-04-10 2015-12-20 Самсунг Электроникс Ко., Лтд. Способ и устройство кодирования и декодирования данных в скрученном полярном коде
US9954645B2 (en) * 2014-12-05 2018-04-24 Lg Electronics Inc. Method and device for providing secure transmission based on polar code
CN105227189B (zh) * 2015-09-24 2019-01-01 电子科技大学 分段crc辅助的极化码编译码方法
US10623142B2 (en) * 2015-10-30 2020-04-14 Huawei Technologies Canada Co., Ltd. Method for determining an encoding scheme and symbol mapping
EP3381128B1 (fr) * 2015-11-24 2020-01-01 Coherent Logix, Incorporated Gestion de mémoire et tri de chemins dans un décodeur de codes polaires avec décodage à liste par annulations successives
CN106253913B (zh) * 2016-07-29 2019-02-22 山东科技大学 极化码的块编码器及其编码方法
CN106230555B (zh) * 2016-07-29 2019-02-19 西安电子科技大学 极化码的分段循环冗余校验方法
US10277252B2 (en) * 2017-01-09 2019-04-30 At&T Intellectual Property I, L.P. Encoding data with polar codes for control channels

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3614592A1 (fr) * 2017-05-02 2020-02-26 Huawei Technologies Co., Ltd. Dispositif et procédé de codage

Also Published As

Publication number Publication date
US11184028B2 (en) 2021-11-23
EP3584971A4 (fr) 2020-02-26
US20200007164A1 (en) 2020-01-02
EP3584971A1 (fr) 2019-12-25
WO2018166431A1 (fr) 2018-09-20
CN108574560B (zh) 2020-07-24
CN108574560A (zh) 2018-09-25

Similar Documents

Publication Publication Date Title
EP3584971B1 (fr) Procédé de codage, procédé de décodage, appareil et dispositif
EP3371890B1 (fr) Codeur et décodeur polaires activés par signature
EP3562071B1 (fr) Procédé et dispositif de codage et de décodage de code polaire
EP3579468B1 (fr) Procédé et dispositif de mise en correspondance de débit de code polaire
CN108540141B (zh) Polar码编译码方法及装置
CN107659381B (zh) 编译码方法及装置
JP4875055B2 (ja) 線形抹消コードを提供する方法と装置
US10498496B2 (en) Retransmission technique
CN110719141A (zh) 一种信息的传输方法、译码方法和装置
CN108540259B (zh) 一种极化码编译码方法及装置
US11025366B2 (en) Channel encoding method and apparatus in wireless communications
US11075715B2 (en) Encoding method and apparatus
CN109474379B (zh) 编码方法及装置
JP7375111B2 (ja) 符号化方法および装置
CN109474383B (zh) 编码方法及装置
CN109474378B (zh) 编码方法及装置
CN109474376B (zh) 编码方法及装置
CN109474380B (zh) 编码方法及装置
EP3667965A1 (fr) Procédé et dispositif de codage

Legal Events

Date Code Title Description
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE

PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20190920

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

A4 Supplementary search report drawn up and despatched

Effective date: 20200127

RIC1 Information provided on ipc code assigned before grant

Ipc: H04L 1/00 20060101AFI20200121BHEP

Ipc: H03M 13/00 20060101ALI20200121BHEP

Ipc: H03M 13/09 20060101ALI20200121BHEP

Ipc: H03M 13/29 20060101ALI20200121BHEP

Ipc: H03M 13/05 20060101ALI20200121BHEP

DAV Request for validation of the european patent (deleted)
DAX Request for extension of the european patent (deleted)
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

17Q First examination report despatched

Effective date: 20210902

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: GRANT OF PATENT IS INTENDED

RIC1 Information provided on ipc code assigned before grant

Ipc: H03M 13/13 20060101ALI20230531BHEP

Ipc: H03M 13/09 20060101ALI20230531BHEP

Ipc: H03M 13/00 20060101ALI20230531BHEP

Ipc: H03M 13/29 20060101ALI20230531BHEP

Ipc: H03M 13/05 20060101ALI20230531BHEP

Ipc: H04L 1/00 20060101AFI20230531BHEP

INTG Intention to grant announced

Effective date: 20230614

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE PATENT HAS BEEN GRANTED

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602018061136

Country of ref document: DE

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: LT

Ref legal event code: MG9D

REG Reference to a national code

Ref country code: NL

Ref legal event code: MP

Effective date: 20231115

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20240216

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20240315

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231115

REG Reference to a national code

Ref country code: AT

Ref legal event code: MK05

Ref document number: 1632722

Country of ref document: AT

Kind code of ref document: T

Effective date: 20231115

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231115

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231115

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231115

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231115

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231115

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20240315

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20240216

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231115

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20240215

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231115

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20240315

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20240201

Year of fee payment: 7

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231115

Ref country code: RS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231115

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231115

Ref country code: NO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20240215

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231115

Ref country code: HR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20231115