EP3523898A1 - Segmentation en blocs de code pour codage et décodage dans un appareil sans fil - Google Patents

Segmentation en blocs de code pour codage et décodage dans un appareil sans fil

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Publication number
EP3523898A1
EP3523898A1 EP16918143.5A EP16918143A EP3523898A1 EP 3523898 A1 EP3523898 A1 EP 3523898A1 EP 16918143 A EP16918143 A EP 16918143A EP 3523898 A1 EP3523898 A1 EP 3523898A1
Authority
EP
European Patent Office
Prior art keywords
code
code blocks
subset
block
parallel processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP16918143.5A
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German (de)
English (en)
Other versions
EP3523898A4 (fr
Inventor
Yi Zhang
Keeth Saliya JAYASINGHE
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Technologies Oy
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Nokia Technologies Oy
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Publication date
Application filed by Nokia Technologies Oy filed Critical Nokia Technologies Oy
Publication of EP3523898A1 publication Critical patent/EP3523898A1/fr
Publication of EP3523898A4 publication Critical patent/EP3523898A4/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/003—Arrangements for allocating sub-channels of the transmission path
    • H04L5/0053—Allocation of signaling, i.e. of overhead other than pilot signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1145—Pipelined decoding at code word level, e.g. multiple code words being decoded simultaneously
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6561—Parallelized implementations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/02—Arrangements for detecting or preventing errors in the information received by diversity reception
    • H04L1/06—Arrangements for detecting or preventing errors in the information received by diversity reception using space diversity
    • H04L1/0618—Space-time coding
    • H04L1/0637—Properties of the code
    • H04L1/0643—Properties of the code block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/003—Arrangements for allocating sub-channels of the transmission path
    • H04L5/0044—Arrangements for allocating sub-channels of the transmission path allocation of payload

Definitions

  • the invention relates to a solution for forming code blocks for block encoding in a source device and for performing block decoding in a sink device in a wireless communication system.
  • Some channel coding schemes employ block-coding where a code block of determined length is formed from systematic bits and parity bits.
  • Systematic bits represent data to be transferred over a channel, and the parity bits contain redundant information that is used to facilitate decoding of the systematic bits in a decoder.
  • Low-Density Parity Check (LDPC) are an example of block codes that have been used in wireless systems.
  • LDPC codes as such are well known in coding theory and known to approach the Shannon channel capacity limit when utilized properly in data transmission.
  • Irregular LDPC codes are known from the fact that input bits may be encoded with different degrees of coding strength, i.e. each input bit may be protected by a different number of parity check equations.
  • Regular LDPC codes employ the same number of parity check equations for each systematic bit.
  • An LDPC code can be represented by a bipartite graph, which consists of variable nodes, check nodes and a certain number of edges between these two types of nodes.
  • Each variable node represents a bit of a codeword and each check nodes represents a parity check of the code.
  • An edge exist between a variable node and a check node only if this bit is checked by this edge-connected parity check equation.
  • the degree of a node is the number of edges connected to this node.
  • An irregular LDPC code has a bipartite graph in which the bit nodes (check nodes) have different degrees. A higher variable node degree means that a bit is protected by more parity check equations, which implies to a lower bit error probability. In this manner, a parity check matrix may be constructed.
  • the parity check matrix defines how parity check bits should be calculated. That is, each parity check bit is calculated from given one or more systematic data bits and parity bits.
  • Quasi-cyclic LDPC (QC-LDPC) codes have been designed to provide efficient implementations.
  • the parity check matrix is constructed by a plurality of sub-matrices, wherein at least some of the sub-matrices are circulant permutation matrices. Some of the other sub-matrices may have another constructions, e.g. a zero matrix construction.
  • the LDPC codes form an efficient solution for forward error correction.
  • the success of decoding the codeword may be verified by using a cyclic redundancy check (CRC) , and the result of the CRC check indicates whether or not the decoded codeword includes residual, post-decoding errors.
  • CRC cyclic redundancy check
  • block-coding schemes other than the LDPC, similar encoding and decoding principles may be employed.
  • Figure 1 illustrates some wireless communication scenarios to which embodiments of the invention may be applied
  • Figures 2 and 3 illustrate flow diagrams of processes for employing knowledge of processing capability of a sink device in segmentation of a transport block according to some embodiments of the invention
  • FIG. 4 illustrate an effect of the embodiments of Figures 2 and 3;
  • Figure 5 illustrates a flow diagram of a process for reducing the need for padding bits according to an embodiment of the invention
  • Figure 6 illustrate a plurality of code block subsets with different sets of code block sizes for use in the embodiment of Figure 5;
  • FIG. 7 illustrates efficient use of hardware resources in the sink device according to an embodiment of the invention
  • Figures 8 and 9 illustrate processes for minimizing the number of padding bits while providing efficient usage of hardware resources in the sink device according to some embodiments of the invention.
  • FIGS 10 and 11 illustrate block diagrams of apparatuses according to some embodiments of the invention.
  • Embodiments described may be implemented in a radio system, such as in at least one of the following: Universal Mobile Telecommunication System (UMTS, 3G) based on basic wideband-code division multiple access (W-CDMA) , high-speed packet access (HSPA) , Long Term Evolution (LTE) , LTE-Advanced, a system based on IEEE 802.11 specifications, a system based on IEEE 802.15 specifications, and/or a fifth generation (5G) mobile or cellular communication system.
  • UMTS Universal Mobile Telecommunication System
  • W-CDMA basic wideband-code division multiple access
  • HSPA high-speed packet access
  • LTE Long Term Evolution
  • LTE-Advanced Long Term Evolution-Advanced
  • a system based on IEEE 802.11 specifications a system based on IEEE 802.11 specifications
  • a system based on IEEE 802.15 specifications and/or a fifth generation (5G) mobile or cellular communication system.
  • 5G fifth generation
  • 5G has been envisaged to use multiple-input-multiple-output (MIMO) multi-antenna transmission techniques, more base stations or nodes than the current network deployments of LTE, by using a so-called small cell concept including macro sites operating in co-operation with smaller local area access nodes and perhaps also employing a variety of radio technologies for better coverage and enhanced data rates.
  • MIMO multiple-input-multiple-output
  • 5G will likely be comprised of more than one radio access technology (RAT) , each optimized for certain use cases and/or spectrum.
  • RAT radio access technology
  • 5G system may also incorporate both cellular (3GPP) and non-cellular (e.g. IEEE) technologies.
  • 5G mobile communications will have a wider range of use cases and related applications including video streaming, augmented reality, different ways of data sharing and various forms of machine type applications, including vehicular safety, different sensors and real-time control.
  • 5G is expected to have multiple radio interfaces, including apart from earlier deployed frequencies below 6GHz, also higher, that is cmWave and mmWave frequencies, and also being integratable with existing legacy radio access technologies, such as the LTE. Integration with the LTE may be implemented, at least in the early phase, as a system, where macro coverage is provided by the LTE and 5G radio interface access comes from small cells by aggregation to the LTE.
  • 5G is planned to support both inter-RAT operability (such as LTE-5G) and inter-RI operability (inter-radio interface operability, such as inter-RI operability between cmWave and mmWave) .
  • inter-RAT operability such as LTE-5G
  • inter-RI operability inter-radio interface operability, such as inter-RI operability between cmWave and mmWave
  • One of the concepts considered to be used in 5G networks is network slicing in which multiple independent and dedicated virtual sub-networks (network instances) may be created within the same infrastructure to run services that have different requirements on latency, reliability, throughput and mobility.
  • NFV network functions virtualization
  • a virtualized network function may comprise one or more virtual machines running computer program codes using standard or general type servers instead of customized hardware.
  • Cloud computing or cloud data storage may also be utilized.
  • radio communications this may mean node operations to be carried out, at least partly, in a server, host or node operationally coupled to a remote radio head. It is also possible that node operations will be distributed among a plurality of servers, nodes or hosts. It should also be understood that the distribution of labour between core network operations and base station operations may differ from that of the LTE or even be non-existent.
  • SDN Software-Defined Networking
  • Big Data Big Data
  • all-IP all-IP
  • FIG. 1 illustrates an example of a communication system to which some embodiments of the invention may be applied.
  • the system may comprise one or more access nodes 110 providing and managing respective cells 100.
  • the cell 100 may be, e.g., a macro cell, a micro cell, femto, or a pico cell, for example. From another point of view, the cell may define a coverage area or a service area of the access node.
  • the access node 110 may be an evolved Node B (eNB) as in the LTE and LTE-A, an access point of an IEEE 802.11-based network (Wi-Fi or wireless local area network, WLAN) , or any other apparatus capable of controlling radio communication and managing radio resources within a cell.
  • eNB evolved Node B
  • the access node may provide radio connection to a wireless terminal device need for any intermediate device. In other embodiments, there may be relaying node (s) between the access node and the wireless terminal device. For 5G solutions, the implementation may be similar to LTE-A, as described above.
  • the access node may be called a base station or a network node.
  • the system may be a wireless communication system composed of a radio access network of access nodes, each controlling a respective cell or cells.
  • the access nodes may provide terminal devices (UEs) 120 with wireless access to other networks such as the Internet.
  • one or more local area access nodes may be arranged within a control area of a macro cell access node.
  • the local area access node may provide wireless access within a sub-cell that may be comprised within a macro cell.
  • the sub-cell may include a micro, pico and/or femto cell.
  • the sub-cell provides a hot spot within the macro cell.
  • the operation of the local area access node may be controlled by an access node under whose control area the sub-cell is provided. In some scenarios, a plurality of local area access nodes may be controlled by a single macro cell access node.
  • the access nodes may be connected to each other with an interface.
  • LTE specifications call such an interface as X2 interface.
  • IEEE 802.11 networks a similar interface may be provided between access points.
  • Other wired or wireless communication methods between the access nodes may also be possible.
  • the access nodes may be further connected via another interface to a core network 130 of the cellular communication system.
  • the LTE specifications specify the core network as an evolved packet core (EPC) , and the core network may comprise a mobility management entity (MME) 132 and a gateway (GW) node 134.
  • the MME may handle mobility of terminal devices in a tracking area encompassing a plurality of cells and also handle signalling connections between the terminal devices and the core network 130.
  • the gateway node 134 may handle data routing in the core network 130 and to/from the terminal devices.
  • the different access nodes may be connected to different core networks.
  • the different core networks may be operated by the same operator or by different operators.
  • the radio system of Figure 1 may support Machine Type Communication (MTC) .
  • MTC may enable providing service for a large amount of MTC capable devices, such as the at least one terminal device 120.
  • the at least one terminal device 120 may comprise a mobile phone, smart phone, tablet computer, laptop or other devices used for user communication with the radio communication network, such as an MTC network. These devices may provide further functionality compared to the MTC scheme, such as communication link for voice, video and/or data transfer.
  • the at least one terminal device 120 may be understood as a MTC device.
  • the at least one terminal device 120 may also comprise another MTC capable device, such as a sensor device providing position, acceleration and/or temperature information to name a few examples.
  • Some embodiments of the invention may thus be applicable to Internet of Things (IoT) systems, e.g. a radio access technology supporting a narrowband IoT (NB-IoT) communication scheme.
  • IoT Internet of Things
  • NB-IoT narrowband IoT
  • Figure 1 illustrates an infrastructure-based communication scenario with a fixed access node 110 providing a mobile terminal device 120 with radio access.
  • the devices 120, 122 may be peer devices in the sense that the devices 120, 122 may be the end points of the connection.
  • one of the devices 120 may provide the other device 120 with wireless access to the infrastructure. Accordingly, the device providing the access may be understood as a mobile access node.
  • Such a scheme is sometimes called tethering.
  • the mobile devices 120, 122 may form a mobile ad hoc network having no fixed infrastructure and not necessarily an access node at all.
  • the embodiments of the invention described below are applicable to any system that employs channel coding to compensate for error caused by a communication channel such as a radio channel.
  • Channel encoding is commonly in wireless communication links to combat signal degradation in a radio channel.
  • the channel encoding is typically based on processing data bits in a channel encoder and outputting encoded data bits to further processing in a radio transmitter.
  • the channel encoder typically outputs bits at a higher data rate than a data rate at its input. In other words, the channel encoder computes additional information from the data bits.
  • a systematic channel coding scheme maintains the original data bits at its output and, additionally, outputs parity bits that may be used as additional information in a channel decoder.
  • the low-density parity check (LDPC) codes described in the Background section are an example of such channel codes. Embodiments of the invention described in this document may employ the LDPC codes.
  • an error detection procedure may be executed, wherein the decoded code block is scanned for remaining erroneous bits. Cyclic redundancy check (CRC) bits or other error detection bits may be added to the code block to enable the error detection. If the decoded code block is detected to contain errors in the error detection procedure, the decoding may be deemed unsuccessful. If the decoded code block is detected to contain no errors in the error detection procedure, the decoding may be deemed successful.
  • CRC Cyclic redundancy check
  • an automatic repeat request (ARQ) scheme is also used for retransmissions related to data not being successfully decoded in a receiver.
  • the ARQ scheme is based on the receiver acknowledging (ACK) successful decoding of the data to the transmitter.
  • Some systems employ also negative acknowledgments (NACK/NAK) for the receiver to indicate the failed decoding of the data.
  • NACK/NAK negative acknowledgments
  • Other systems do not employ the NACK/NAK.
  • the transmitter upon not receiving the ACK within a determined time window from the transmission, the transmitter carries out a retransmission.
  • a transport block of a determined length (in terms of a number of bits) is segmented into a plurality of code blocks, and each of the code blocks is encoded by using a block-coding scheme such as LDPC.
  • a CRC portion may have been appended to the transport block before the segmentation. Due to the limitations set by the size of the transport block and a limited number of available code block sizes, the size of the transport block in terms of a number of bits may not be a multiple of a selected code block size, which results in that padding bits are appended to at least one code block to reach the selected code block size for all code blocks.
  • the padding bits may be defined as bits that have no information value what so ever but are needed only to reach a certain size for the code block.
  • the padding bits may have an arbitrary value, e.g. they may be zero bits.
  • the conventional system may be sub-optimal in many ways, and embodiments of the present invention address these inefficiencies of the conventional system.
  • FIGS. 2 and 3 illustrate some embodiments of processes for a source device and the sink device of a transport block, respectively.
  • the source device may refer to a transmitter or an originator of the transport block, while the sink device may refer to a receiver of the transport block.
  • a process comprises as performed by an apparatus suitable for the source device: receiving (block 200) , from the sink device, a message indicating a first number of code blocks the sink device is capable of decoding in parallel processing; generating (block 202) a transport block to be transmitted to the sink device; forming (block 204) , from the transport block on the basis of the received message, a second number of code blocks such that the second number of code blocks is a multiple of the first number of code blocks the sink device is capable of decoding in the parallel processing; and causing (block 206) transmission of the formed code blocks from the first apparatus to the sink device.
  • a process comprises as performed by an apparatus suitable for the sink device: transmitting (block 300) , to the source device, a message indicating a number of code blocks the sink device is capable of decoding in parallel processing; receiving (block 302) , from the source device, a plurality of code blocks of a transport block; distributing (block 304) the received plurality of code blocks into parallel processing pipelines, wherein a number of the parallel processing pipelines is equal to the number indicated to the source device in block 300; decoding (block 306) the plurality of code blocks in the parallel processing pipelines and, after decoding, forming said transport block from the decoded plurality of code blocks.
  • the source device is the access node 110 and the sink device is the mobile device 120. In another embodiment, the source device is the mobile device 120, and the sink device is the access node 110. In yet another embodiment, the source device is one of the mobile devices 120, 122 and the sink device is the other of the mobile devices 120, 122.
  • code blocks 410, 411, 412, 413, 414, and 415 are generated from the transport block 400.
  • the code blocks 410 to 415 have the same size.
  • padding bits may be appended to at least one of the code blocks 410 to 415 to reach the equal size for all the code blocks 410 to 415. Since the number of code blocks is six and, thus, a multiple of the number of pipelines, the sink device may distribute the received code blocks uniformly into the pipelines. Accordingly, efficient decoding in the sink device is enabled, wherein the efficiency may be considered from the viewpoint of processing resource usage and processing delay.
  • the other example represents the conventional solution where code blocks 420, 422, 424, and 426 are generated from the transport block 400.
  • the conventional solution does not consider the processing resources of the sink device, the number of generated code blocks is not the multiple of the number of processing pipelines. Accordingly, the sink device cannot distribute the received code blocks 420 to 426 uniformly to the processing pipelines which results in that at least one processing pipeline is provided with a lower number of code blocks.
  • the number of code blocks C formed in block 204 is defined as follows:
  • L is the number of parallel processing pipelines in the sink device
  • B is the size of the transport block including the possible CRC bits
  • K max is the size of the code blocks.
  • a temporal length for a code block may be derived from and in an embodiment
  • K’ is selected for the code block size.
  • r 1, 2, ..., max ⁇ .
  • Kr may be a code block size amongst the available code block sizes ⁇ K 1 , K 2 , ..., K max ⁇ and, furthermore, K’-K r > 0.
  • the latter embodiment is applicable to a case where there are a limited set of available code blocks sizes, and the selected code block size K n may be the next available code block size that is larger than K’ . This may be equally implemented by rounding up to the next available code block size.
  • the source device may employ a further criterion when selecting the number of code blocks C.
  • a further criterion is that the size of the code blocks K max is selected such that every code block contains information bits (systematic bits) . This enables reduction in the number of padding bits.
  • This embodiment enables the source device to scale the size of the code blocks to match with the number of parallel processing pipelines in the sink device such that the decoding is efficient.
  • the source device may have, before the segmentation, information on a block coding matrix to be used for the block encoding, e. g. the parity check matrix H described below. Additionally, the source device has knowledge on a code rate to be used, e. g. from a modulation and coding scheme parameter.
  • Figure 5 illustrates another embodiment for improving the conventional system.
  • Figure 5 illustrates a process for providing multiple code block lengths for the code blocks formed of the transport block. The process may be carried out in the source device.
  • the process comprises: providing a pool of a plurality of code block subsets (block 500) , the pool comprising at least a first code block subset and a second code block subset, wherein the first code block subset defines a first set of available code block sizes, and wherein the second code block subset defines a second set of available code block sizes different from the first set of available code block sizes; generating a transport block to be transmitted to the sink device (block 202) ; selecting from the pool a code block subset that provides a minimum number of additional padding bits amongst code block subsets of the pool (block 502) ; forming a plurality of code blocks from the transport block according to the selected code block subset (block 504) ; encoding the plurality of code blocks and causing transmission of the plurality of encoded code blocks to the
  • a code block subset may be considered as a tool bag for generating the code blocks in the segmentation of the transport block, wherein the tool bag defines the available code block sizes for the segmentation.
  • the source device may first select the tool bag that is considered to provide the minimum number of padding bits (block 502) and, then, use multiple code block sizes of the selected tool bag in the segmentation (block 504) .
  • a mapping table may be preconfigured and stored in the source device, and block 502 may comprise determining the length of the transport block and selecting a code block subset associated with the determined length.
  • LDPC codes may be constructed for fixed dimensions where an LDPC parity check matrix H is defined as (N-K) ⁇ N matrix,
  • N is the number of columns in the parity check matrix H
  • N*z is the coded block sizes after encoding
  • Q*z is the size of a block of systematic bits (the above-mentioned code block)
  • (N-Q) *z is the size of a block of parity bits.
  • the supported code block size is often limited to Q*z or some other limited value where z is allowed to vary. To guarantee a lower memory usage, the realization complexity and performance robustness, the variation of this so-called lifting value z may be limited.
  • a set of lifts may be defined by by a k ⁇ 2 i , wherein a k ⁇ ⁇ a 1 , a 2 , ..., a K , ⁇ and 0 ⁇ i ⁇ M, wherein K and M are non-zero integers. Both K and M are limiting factors that limit the number of available code block sizes. K and M may be preconfigured in system specifications of the wireless network of the source device and the sink device. Each subset k ⁇ [1: K] is defined by its leader a k that is multiplied by powers of 2 until the maximum power M, thus providing M values in each subset k. Thus, altogether there are (M+1) Klifting values and associated code block sizes that are available to the source device.
  • Some examples of the size of the transport block may include 15 000 bits, 75376 bits (a value in an LTE system) , or even higher....With this restriction of granularity, the overhead of padding bits will be large in some cases, and the embodiment of Figure 5 addresses this issue.
  • Figure 5 illustrates an example of this scheme.
  • Information (systematic) bits for a block encoder may be segmented according to the following equation using the lifting factor z described above:
  • K s is the number of bits in the transport block 400 (see Figure 6)
  • q k is the number of padding bits needed in the code block subset k
  • a k multiplied by 2 M , ... 2 0 is as described above in a case where i was used as an index having values from 0 to M
  • p k, i (0 ⁇ i ⁇ M) indicates a number of code blocks having the size a k ⁇ 2 i
  • N is the number of columns in the block-coding matrix, e.g. the LDPC parity check matrix
  • R is a code rate (a number of systematic bits per a total number of bits after encoding) .
  • a maximum code block size K max may be defined as a k ⁇ 2 M ⁇ N.
  • the code block sizes may be defined by a k ⁇ 2 i ⁇ N, and the code block sizes are thus proportional to a k ⁇ 2 i .
  • p k, M is a positive (or non-negative) integer. In an embodiment, p k, M is higher than one so that the number of code blocks having the maximum size is higher than one.
  • p k, i (0 ⁇ i ⁇ M-1) is either 0 or 1, depending on whether or not the code blocks segmented from the transport block 400 include a code block of size a k ⁇ 2 i .
  • the transport block 400 may be segmented into code blocks 410 to 415 of the maximum code block size K max of a first code block subset and, furthermore, into one or more code blocks 600, 602, 604, 606 of a code block size smaller than K max .
  • Each of the code blocks 600 to 606 may be employed at maximum only once for the remaining systematic bits that are not included in the code blocks 410 to 415.
  • the selection of the code blocks 600 to 606 may be carried out by using Equation (1) such that the number of padding bits is minimized.
  • the code blocks 602 and 606 are selected, and the number of needed padding bits may be computed according to Equation (1) above. This forms the optimal candidate solution for the first code block subset.
  • Similar procedure may be carried out for the other K-1 code block subsets that each define a unique set of available code block sizes.
  • the K th code block subset employs a larger K max than the first code block subset and, accordingly, a lower number of code blocks 420, 422, 424, 426 of the maximum size is segmented.
  • the sizes for the smaller code blocks 610, 612, 614, 616 may also be unique amongst the code block subsets.
  • Example 1 provides a lower number of padding bits in this case.
  • the source device may determine which one of the code block groups requires the lowest number of padding bits, and the corresponding optimal candidate solution is selected for the block-encoding.
  • the resulting code blocks segmented from the transport block may have multiple sizes.
  • Figure 7 illustrates an embodiment of distribution of such code blocks into the parallel processing pipelines 1 to 4.
  • the encoded code blocks 700 to 714 received at the sink device comprises a first subset 700 to 710 having a first size and at least a second subset 712 and/or 714 having a second size different from the first size.
  • the second subset may comprise both code blocks 712 and 714 and, in general, all code blocks smaller than the code blocks of the first subset.
  • the sink device may now distribute the first subset of encoded code blocks 700 to 710 as uniformly as possible to the parallel processing pipelines, as illustrated in Figure 7. This may be understood such that each pipeline is allocated with no more than one code block more than another pipeline. If the number of encoded code blocks in the first subset is a multiple of the number of pipelines in the sink device, each pipeline is provided with the same number of encoded code blocks.
  • the total processing delay may be defined by the number of encoded code blocks of the first subset and the size of the largest encoded code block of the second subset.
  • Figure 7 illustrates an embodiment where at least one of the parallel processing pipelines is provided with a lower number of encoded code blocks of the first subset than another parallel processing pipeline.
  • the sink device may distribute encoded code blocks of the second subset to the at least one of the parallel processing pipelines.
  • the encoded code block (s) of the second subset may be distributed to that/those pipeline (s) that are provided with the lowest number of encoded code blocks of the first subset.
  • those pipelines may by utilized instead of keeping them idle, thus optimizing the resource usage and processing delay.
  • the code blocks of the second subset are distributed uniformly to the at least one of the parallel processing pipelines provided with the lowest number of encoded code blocks of the first subset.
  • This solution is illustrated in Figure 7 where the encoded code blocks 712 and 714 are both allocated to the different pipelines 3 and 4.
  • This solution may be feasible in a case where the number of code blocks of the second subset is lower than or equal to the number of parallel processing pipelines provided with the lowest number of encoded code blocks of the first subset.
  • the code blocks of the second subset are distributed non-uniformly to the at least one of the parallel processing pipelines provided with the lowest number of encoded code blocks of the first subset. This may be optimal, for example, in a case where the number of the parallel processing pipelines provided with the lowest number of encoded code blocks of the first subset is two or higher and the number of encoded code blocks in the second subset is higher than the number of parallel processing pipelines provided with the lowest number of encoded code blocks of the first subset. For example, if the second subset includes two small blocks and one larger block, and if the number of idle pipelines is two, it may be feasible to allocate the two small blocks to one pipeline and the one larger to the other pipeline to optimize the resource usage and the processing delay.
  • the source device may use the procedure of Figure 2 in connection with the process of Figure 5 such that block 502 uses as a further criterion the number of parallel processing pipelines in the sink device according to block 204.
  • the source device may limit the total number of code blocks to multiples of the number of the parallel processing pipelines in the sink device. Accordingly, the options for generating different candidate solutions from the code block sizes of each code block subset are limited but the decoding efficiency may be improved.
  • Figure 8 illustrates a flow diagram of a process for optimizing the usage of the parallel pipelines of the sink device while providing the multiple granularity for the code block sizes in the source device.
  • the process may be executed in the source device.
  • the total number of generated encoded code blocks for the selected code block subset k may be limited, as described above:
  • the source device may execute blocks 200, 202, 502, and 504 in the above-described manner. Blocks 502 and 504 may be carried out without using the knowledge of the parallel processing pipelines in the sink device at this stage. Blocks 800 and 802 adapt the total number of encoded code blocks to match with C.
  • the source device determines whether or not the number of code blocks smaller than K max of the selected code block subset k (Y in Figure 8) is higher than a remainder (X in Figure 8) of the number of code blocks with size K max (of the selected code block subset k) divided by the number of pipelines in the sink device. If there exists a lower number of smaller code blocks than the number of remaining pipelines (NO in block 800) , the process may end and the sink device may allocate the smaller code blocks into the remaining (idle) pipelines according to Figure 7, for example.
  • the process may proceed to block 802 in which the source device aggregates a plurality of smaller code blocks into a larger code block for encoding.
  • Figure 9 illustrates this process in which the number of parallel pipelines is now three and the number code blocks of size K max is five, thus providing only a single remaining pipeline (pipeline #3) with a lower number of allocated encoded code blocks.
  • the source device may combine the code blocks 912 and 914 into a single code block, or logically form the single code block instead of the two smaller code blocks 912 and 914.
  • a limitation to the combining is that the resulting code block shall be smaller than K max .
  • This aggregated code block may then be allocated to the remaining pipeline by the sink device, as illustrated in Figure 9.
  • the source device may first find x k th non-zero p k, i (the x k th largest code block having non-zero p k,i ) having a lifting value z i . Then, the segmentation may be updated according to the following principle such that the number of generated code blocks matches with the number of the pipelines of the sink device:
  • the next, larger code block size having a zero value of p k, i for the x k th non-zero p k, i in Equation (1) is selected and this code block size is selected for the aggregated code block. This complies with the rule that the transmit block will be contained by the newly multiple code blocks with different code block size. If no such zero-valued larger code block size exists, one more code block of the maximum size is selected for the aggregation.
  • Steps i. and ii. increase the selected code block sizes which enables the reduced number of code blocks generated in the segmentation so that a match is provided between the number of generated code blocks and the number of pipelines. Additionally, the number of padding bits may be optimized.
  • the segmentation of the transport block may be carried out by using the selected new code block sizes.
  • Figures 10 and 11 illustrate block diagrams of apparatuses according to some embodiments of the invention.
  • Figure 10 illustrates the source device comprising an encoder
  • Figure 11 illustrates the sink device comprising a decoder.
  • an apparatus comprises both the encoder and the decoder so the apparatus may be considered as a combination of the embodiments of Figures 10 and 11. Since the description of embodiments in this document uses the viewpoint of the source device and the sink device, the same form of description is maintained with Figures 10 and 11.
  • the apparatus of Figure 10 and/or 11 may be any one of the above-described apparatuses, e.g.
  • the access node 110 or a terminal device 120 or a peer device 122 may be comprised in any one of the above-described apparatuses 110, 120, 122.
  • the apparatus may be, for example, a circuitry or a chipset in any one of the apparatuses 110, 120, 122.
  • the apparatus may be an electronic device comprising electronic circuitries.
  • the apparatus may comprise a communication control circuitry 10 such as at least one processor, and at least one memory 20 including a computer program code (software) 22 wherein the at least one memory and the computer program code (software) are configured, with the at least one processor, to cause the apparatus to carry out any one of the embodiments of the source device described above.
  • a communication control circuitry 10 such as at least one processor, and at least one memory 20 including a computer program code (software) 22 wherein the at least one memory and the computer program code (software) are configured, with the at least one processor, to cause the apparatus to carry out any one of the embodiments of the source device described above.
  • the memory 20 may be implemented using any suitable data storage technology, such as semiconductor based memory devices, flash memory, magnetic memory devices and systems, optical memory devices and systems, fixed memory and removable memory.
  • the memory may comprise a configuration database 24 for storing configuration data for processing transport blocks for block encoding.
  • the configuration database 24 may store information on the number of processing pipelines in the sink device and/or the above-described mapping table mapping the transport block sizes to the number of padding bits for each code block group.
  • the apparatus may further comprise a communication interface (TX/RX) 26 comprising hardware and/or software for realizing communication connectivity according to one or more communication protocols.
  • the communication interface 26 may provide the apparatus with communication capabilities to communicate in the cellular communication system and/or in another wireless network. Depending on whether the apparatus is configured to operate as a terminal device, a peer device, or an access node, and depending on a radio access technology, the communication interface may provide different functions.
  • the communication interface 26 may comprise standard well-known components such as an amplifier, filter, frequency-converter, (de) modulator, and encoder/decoder circuitries and one or more antennas.
  • the communication interface 26 may comprise radio interface components providing the apparatus with radio communication capability in one or more wireless networks and enable radio communication with one or more sink devices.
  • the communication control circuitry 10 may comprise a transmission controller 12 configured to carry out control plane signalling such as transmission and reception of control or management messages. Such messages may include link establishment messages, link management messages, link termination messages, handover messages, measurement messages, beacon or pilot signals, etc.
  • the communication control circuitry 10 may further comprise a data communication circuitry 16 configured to carry out user plane or data plane communication with the terminal devices.
  • the communication control circuitry 10 may further comprise a block encoder 18 configured to encode control plane and/or data plane messages before transmission through the communication interface 26.
  • the block encoder 18 may perform channel encoding by employing LDPC channel codes, for example.
  • the block encoder 18 may comprise a segmentation circuitry 14 configured to segment the transport blocks and generate code blocks according to any one of the above-described embodiments for encoding in the block encoder.
  • the segmentation circuitry 14 may be configured to carry out the embodiment of Figure 2 and/or 5 or any one of their embodiments.
  • the segmentation circuitry 14 may comprise a code block group (CBG) selection circuitry 15 configured to carry out block 502.
  • CBG code block group
  • the apparatus of Figure 10 comprises at least one processor 10 and at least one memory 20 including a computer program code 22, wherein the at least one memory and the computer program code are configured, with the at least one processor, to cause the apparatus to carry out the functionalities of the source device according to any one of the embodiments of Figures 2, 4 to 6, 8, and 9.
  • the computer program code when the at least one processor 10 executes the computer program code, the computer program code causes the apparatus to carry out the functionalities according to any one of the embodiments of Figures 2, 4 to 6, 8, and 9.
  • the apparatus comprises the at least one processor 10 and at least one memory 20 including a computer program code 22, wherein the at least one processor 10 and the computer program code 22 perform the at least some of the functionalities of the source device according to any one of the embodiments of Figures 2, 4 to 6, 8, and 9.
  • the at least one processor, the memory, and the computer program code form processing means for carrying out embodiments of the present invention in the source device.
  • the apparatus carrying out the embodiments of the invention in the source device comprises a circuitry including at least one processor 10 and at least one memory 20 including computer program code 22. When activated, the circuitry causes the apparatus to perform the at least some of the functionalities of the source device according to any one of the embodiments of Figures 2, 4 to 6, 8, and 9.
  • the apparatus may comprise a communication control circuitry 50 such as at least one processor, and at least one memory 60 including a computer program code (software) 62 wherein the at least one memory and the computer program code (software) are configured, with the at least one processor, to cause the apparatus to carry out any one of the embodiments of the sink device described above.
  • a communication control circuitry 50 such as at least one processor
  • at least one memory 60 including a computer program code (software) 62 wherein the at least one memory and the computer program code (software) are configured, with the at least one processor, to cause the apparatus to carry out any one of the embodiments of the sink device described above.
  • the memory 60 may be implemented using any suitable data storage technology, such as semiconductor based memory devices, flash memory, magnetic memory devices and systems, optical memory devices and systems, fixed memory and removable memory.
  • the memory may comprise a configuration database 64 for storing configuration data for decoding encoded code blocks.
  • the configuration database 64 may store information on how to distribute code blocks of smaller size than the maximum size K max to the parallel pipelines, e.g. as described in connection with Figure 7.
  • the apparatus may further comprise a communication interface (TX/RX) 66 comprising hardware and/or software for realizing communication connectivity according to one or more communication protocols.
  • the communication interface 66 may provide the apparatus with communication capabilities to communicate in the cellular communication system and/or in another wireless network. Depending on whether the apparatus is configured to operate as a terminal device, a peer device, or an access node, and depending on a radio access technology, the communication interface may provide different functions.
  • the communication interface 66 may comprise standard well-known components such as an amplifier, filter, frequency-converter, (de) modulator, and encoder/decoder circuitries and one or more antennas.
  • the communication interface 26 may comprise radio interface components providing the apparatus with radio communication capability in one or more wireless networks and with one or more source devices.
  • the communication control circuitry 50 may comprise a transmission controller 52 configured to carry out control plane signalling such as transmission and reception of control or management messages. Such messages may include link establishment messages, link management messages, link termination messages, handover messages, measurement messages, beacon or pilot signals, etc.
  • the communication control circuitry 50 may further comprise a data communication circuitry 56 configured to carry out user plane or data plane communication with the terminal devices.
  • the communication control circuitry 50 may further comprise a block decoder 58 configured to decode control plane and/or data plane messages received through the communication interface 66.
  • the block decoder 58 may perform channel decoding by employing LDPC channel codes, for example.
  • the block decoder may comprise a pipeline distributor configured to distribute received encoded code blocks into parallel decoding pipelines of the block decoder 58 according to a determined criterion, e.g. as defined by the configuration database 64.
  • the apparatus of Figure 11 comprises at least one processor 50 and at least one memory 60 including a computer program code 62, wherein the at least one memory and the computer program code are configured, with the at least one processor, to cause the apparatus to carry out the functionalities of the sink device according to any one of the embodiments of Figures 3, 4, 7, and 9.
  • the computer program code when the at least one processor 50 executes the computer program code, the computer program code causes the apparatus to carry out the functionalities according to any one of the embodiments of Figures 3, 4, 7, and 9.
  • the apparatus comprises the at least one processor 50 and at least one memory 60 including a computer program code 62, wherein the at least one processor 50 and the computer program code 62 perform the at least some of the functionalities of the sink device according to any one of the embodiments of Figures 3, 4, 7, and 9.
  • the at least one processor, the memory, and the computer program code form processing means for carrying out embodiments of the present invention in the sink device.
  • the apparatus carrying out the embodiments of the invention in the sink device comprises a circuitry including at least one processor 50 and at least one memory 60 including computer program code 62. When activated, the circuitry causes the apparatus to perform the at least some of the functionalities of the sink device according to any one of the embodiments of Figures 3, 4, 7, and 9.
  • circuitry refers to all of the following: (a) hardware-only circuit implementations, such as implementations in only analog and/or digital circuitry, and (b) combinations of circuits and soft-ware (and/or firmware) , such as (as applicable) : (i) a combination of processor (s) or (ii) portions of processor (s) /software including digital signal processor (s) , software, and memory (ies) that work together to cause an apparatus to perform various functions, and (c) circuits, such as a microprocessor (s) or a portion of a microprocessor (s) , that require software or firmware for operation, even if the software or firmware is not physically present.
  • circuitry would also cover an implementation of merely a processor (or multiple processors) or a portion of a processor and its (or their) accompanying software and/or firmware.
  • circuitry would also cover, for example and if applicable to the particular element, a baseband integrated circuit or applications processor integrated circuit for a mobile phone or a similar integrated circuit in a server, a cellular network device, or another network device.
  • the techniques and methods described herein may be implemented by various means. For example, these techniques may be implemented in hardware (one or more devices) , firmware (one or more devices) , software (one or more modules) , or combinations thereof.
  • the apparatus (es) of embodiments may be implemented within one or more application-specific integrated circuits (ASICs) , digital signal processors (DSPs) , digital signal processing devices (DSPDs) , programmable logic devices (PLDs) , field programmable gate arrays (FPGAs) , processors, controllers, micro-controllers, microprocessors, other electronic units designed to perform the functions described herein, or a combination thereof.
  • ASICs application-specific integrated circuits
  • DSPs digital signal processors
  • DSPDs digital signal processing devices
  • PLDs programmable logic devices
  • FPGAs field programmable gate arrays
  • processors controllers, micro-controllers, microprocessors, other electronic units designed to perform the functions described herein, or a combination
  • the implementation can be carried out through modules of at least one chipset (e.g. procedures, functions, and so on) that perform the functions described herein.
  • the software codes may be stored in a memory unit and executed by processors.
  • the memory unit may be implemented within the processor or externally to the processor. In the latter case, it can be communicatively coupled to the processor via various means, as is known in the art.
  • the components of the systems described herein may be rearranged and/or complemented by additional components in order to facilitate the achievements of the various aspects, etc., described with regard thereto, and they are not limited to the precise configurations set forth in the given figures, as will be appreciated by one skilled in the art.
  • Embodiments as described may also be carried out in the form of a computer process defined by a computer program or portions thereof. Embodiments of the methods described in connection with Figures 2 to 9 may be carried out by executing at least one portion of a computer program comprising corresponding instructions.
  • the computer program may be in source code form, object code form, or in some intermediate form, and it may be stored in some sort of carrier, which may be any entity or device capable of carrying the program.
  • the computer program may be stored on a computer program distribution medium readable by a computer or a processor.
  • the computer program medium may be, for example but not limited to, a record medium, computer memory, read-only memory, electrical carrier signal, telecommunications signal, and software distribution package, for example.
  • the computer program medium may be a non-transitory medium. Coding of software for carrying out the embodiments as shown and described is well within the scope of a person of ordinary skill in the art.

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Abstract

La présente invention concerne une solution destinée à optimiser la segmentation d'un bloc de transport en une pluralité de blocs de code appelés à être codés et émis sur un canal radio. Selon un aspect, un procédé comporte les étapes consistant à: recevoir au niveau d'un premier appareil, en provenance d'un deuxième appareil, un message indiquant un premier nombre de blocs de code que le deuxième appareil est capable de décoder lors d'un traitement parallèle; générer, au niveau du premier appareil, un bloc de transport à envoyer au deuxième appareil; former, au niveau du premier appareil, à partir du bloc de transport d'après le message reçu, un deuxième nombre de blocs de code de telle façon que le deuxième nombre de blocs de code soit un multiple du premier nombre de blocs de code que le deuxième appareil est capable de décoder lors du traitement parallèle; et provoquer l'envoi des blocs de code formés du premier appareil au deuxième appareil.
EP16918143.5A 2016-10-08 2016-10-08 Segmentation en blocs de code pour codage et décodage dans un appareil sans fil Withdrawn EP3523898A4 (fr)

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WO2009122307A2 (fr) * 2008-03-31 2009-10-08 Marvell Israel ( Misl) Ltd. Procédé et appareil de décodage
US20110280133A1 (en) * 2010-05-11 2011-11-17 Qualcomm Incorporated Scalable scheduler architecture for channel decoding
EP2579468B1 (fr) * 2011-10-05 2020-05-06 Telefonaktiebolaget LM Ericsson (publ) Procédé et dispositif pour décoder un bloc de transport d'un signal de communication
US10075266B2 (en) * 2013-10-09 2018-09-11 Qualcomm Incorporated Data transmission scheme with unequal code block sizes
CN105515733B (zh) * 2014-09-24 2019-03-12 中兴通讯股份有限公司 一种反馈方法及装置
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