EP3449366A1 - Procédé de fonctionnement synchronisé de processeurs multicoeurs - Google Patents

Procédé de fonctionnement synchronisé de processeurs multicoeurs

Info

Publication number
EP3449366A1
EP3449366A1 EP17733365.5A EP17733365A EP3449366A1 EP 3449366 A1 EP3449366 A1 EP 3449366A1 EP 17733365 A EP17733365 A EP 17733365A EP 3449366 A1 EP3449366 A1 EP 3449366A1
Authority
EP
European Patent Office
Prior art keywords
core
processor
processor core
mci
main processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP17733365.5A
Other languages
German (de)
English (en)
Inventor
Uwe Eckelmann-Wendt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Mobility GmbH
Original Assignee
Siemens Mobility GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Mobility GmbH filed Critical Siemens Mobility GmbH
Publication of EP3449366A1 publication Critical patent/EP3449366A1/fr
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5066—Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/82—Architectures of general purpose stored program computers data or demand driven
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/546—Message passing systems or structures, e.g. queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G06F11/1683—Temporal synchronisation or re-synchronisation of redundant processing components at instruction level

Definitions

  • the invention relates to a method for the synchronized operation of a plurality of multi-core processors. Further, the invention relates to a multi-core processor system configured to perform the method of synchronized operation of a plurality of multi-core processors.
  • Voterbaustein be compared.
  • each producing separate outputs (three Kanae ⁇ le) can then be a deviation of an output to be detected and excluded in a result of this special processor or the corresponding channel.
  • two processors are excluded and separated from the periphery, since it is not possible to decide which of the two generates the correct outputs.
  • Interrupts refer to interruptions of a running program, for example, to execute programs or tasks with higher priority. For this purpose, the running program is interrupted at a certain point and continued after processing of the interrupt at this point again.
  • interrupts are fed in such a way that for each processor of the interrupt in exactly interrupts the same machine command of the executed program. Furthermore, the inputs are so distributed over the Prozes ⁇ sensors that the various processors always get exactly identical input data.
  • the runtime differences of the channels or processors must be compensated by latencies of the faster processor for the slower processor.
  • the synchronization is triggered as a side effect of I / O commands or after a certain number of memory accesses.
  • the object is, therefore, to develop a method which enables a hardware-synchronous operation using multi-core processors, in which the computing power of the additional processor cores does not remain unused.
  • the inventive method for the synchronized operation of a plurality of multi-core processors basically comprises the following steps: a) providing a first multi-core processor and a second multi-core processor each comprising a main processor core and at least one Ne- benskeletonn, which serves for the processing of utility programs.
  • a) providing a first multi-core processor and a second multi-core processor each comprising a main processor core and at least one Ne- benskeletonn, which serves for the processing of utility programs.
  • the Synchronisie ⁇ ren of the first multi-core processor with the second multi-core processor is such that only the respective main processor core of the first multi-core processor with the main processor core of second multi-core processor synchronized.
  • the at least one secondary processor core is controlled by the respective main processor core in each multi-core processor.
  • step d) the Nutzprogramme be processed by the at least one slave processor core and generates outputs that are provided to the respective Hauptpro ⁇ zessorkern of the same multi-core processor is available.
  • step e) the synchronous output of outputs of the plurality of multi-core processors is realized by the respective main processor core.
  • the method has the advantage that the synchronization is done only by the main processor core of each multi-core processor and the one or more sub-processor cores do not interfere with this synchronization.
  • the respective main processor cores thus act as synchronization masters.
  • the subprocessor cores serve only as slave computation, d. H. the pending utility programs are passed to the subprocessor cores, processed, and then the outputs are returned to the respective main processor core
  • input / output takes place only via the respective main processor cores.
  • the Maupro ⁇ zessorkerne only be made controllable by the main processor cores. Only the main processor cores "communicate" with the periphery.
  • the communication between the Hauptprozes ⁇ sorkern and the at least one slave processor core takes place by messages by means of a shared memory
  • the slave processors cores can be operated as virtual processor cores, which can be provided on these cores, an operating system that allows communication between processor cores by means of message exchange.
  • the transfer of messages can be done, for example, by means of locking Protocol on ge ⁇ my same memory areas (shared memory areas) to avoid access conflicts.
  • the main processor core has set up the memory allocation here.
  • the main processor core preferably deliver to the at least ei ⁇ NEN respective secondary processor core of the corresponding multi-core processor, a Uhrzeitinkrement.
  • the time increment is to be understood as a clock updated at regular time intervals or time intervals.
  • the slave processor cores per main processor core thus have the same time increment synchronously available. This can be done for example every 20ms.
  • the slave processors cores the processing of pending, computational tasks or programs are granted at regular intervals.
  • These can be distributed from the main processor core to the slave processor cores to be ⁇ agreed manner, whereby this distribution takes place in each ⁇ the multi-core processor in the same way. Preference is implemented in the utility programs or operating systems such ⁇ recastender system call.
  • such a system call may be a synchronization stimulus.
  • a first processing phase is preferably carried out by the system call in the jewei ⁇ then at least one secondary processor core, in which the receiving and transmitting of messages between the at least one slave processor core and the respective main processor core is performed, and is thereby interrupted, a second processing phase in which the Nutzprogramme are processed in the at least one secondary processor core.
  • the first processing phase thus takes place in the interruption of the second processing phase.
  • the actual Abar ⁇ processing of the programs will take place, in which also the respective Be ⁇ operating system of slave processor cores running.
  • the second Bear ⁇ beitungsphase gets thus of the respective first processing stage with nothing.
  • the receiving and sending of messages between the at least one slave processor core and the respective main processor core are preferably performed at a synchronous time.
  • the output can be present at the same time in each main processor core and processed further without producing undesired deviations.
  • the synchronous timing can be achieved by actively War ⁇ th a Uhrzeitinkrement. This can be done game, every 100 ms or every 200 ms at ⁇ .
  • the first processing phase can produce a delay of Reakti ⁇ on a Uhrzeitinkrement in the at least one Volunteerpro ⁇ zessorkern based on the counted within a time between two Uhrzeitinkremente system calls.
  • runtime differences are advantageously compensated and the secondary processor cores run correspondingly more concurrently.
  • kill ⁇ operates in the slave processors whose outputs are synchronously transferred after a delay time, which is greater than the duration of the Nutzprogramme to the main processor cores.
  • the delay ⁇ time should be selected accordingly so that the calculation to ⁇ nenden issues present in the delay time, that a synchronous handover to the main processor core ⁇ Lich mög.
  • the runtimes of the utility programs may be known in advance. The expiration of the delay ⁇ time is actively waiting.
  • At least one processor core of the at least one slave processor core can be designed as a hyperthreading core.
  • the method can also be applied to hyper thread-enabled Prozes ⁇ sors therefore, provide the virtual processor cores available.
  • a multi-core processor system comprising a plurality of multi-core processors, each comprising a main processor core and at least one slave processor core serving for executing useful programs, characterized in that the multi-core processor system is designed such that the method for synchronized operation of a plurality of multi-core processors according to one of above to execute described embodiments.
  • a computer program which allows a data processing device, after being loaded into a storage means of the data processing device, to perform a method for the synchronized operation of a plurality of multi-core processors according to one of the embodiments described above.
  • a computer readable storage medium in which a program is stored which enables a ve ⁇ rarbeitungs worn after it has been loaded into storage means of the data processing device to perform a method for synchronized operation of a plurality of multi-core processors of any of embodiments above described.
  • Figure 1 is a schematic representation of an inventive ⁇ SEN multi-core processor system
  • Figure 2 is a schematic representation of the inventive method for synchronized operation of a plurality of multi-core processors.
  • FIG. 1 shows a schematic representation of a multi-core processor system (10) according to the invention purely by way of example. Based on this representation, the method according to the invention for the synchronized operation of a plurality of multi-core processors (MCI, MC2) will also be described, which is summarized schematically in FIG. It should be ⁇ noted that in Figure 1 are particularly relevant only for the invention technical characteristics are displayed and these features are not exhaustive and other technical features that are known in the art may be included such. B. further memory structures, corresponding bus systems, timers, schedulers, peripheral units etc ..
  • the multi-core processor system (10) comprises by way of example a first multi-core processor (MCI) and a second multi-core processor (MC2).
  • MCI multi-core processor
  • MC2 multi-core processor
  • any number of processors Mehrkernpro ⁇ (MCI, MC2) may be provided, but at least two, which corresponds therefore to a plurality of multi-core processors (MCI, MC2).
  • Particularly preferred are three Mehrkern perspectiveso ⁇ ren, since a deviation in the outputs or a failure of a multi-core processor can be compensated for safety.
  • Each multi-core processor comprises exactly one main processor core (AI, A2), here by way of example the main processor core (AI) in the first multi-core processor (MCI) and the main processor core (A2) in the second multi-core processor (MC2) are installed.
  • the first Multi-core processor MCI
  • the second multi-core processor MC2
  • the second multi-core processor MC2
  • the invention is not limited to two sub-processor cores (Bl, B2, B3, B4), but only one sub-processor core or more than two sub-processor cores per main processor core may be provided.
  • Utilization programs include applications, application software, computation programs, tasks and any form of programs that can be processed by processor cores.
  • the utility programs that are processed by the respective multi-core processors (MCI, MC2) are identical in this case, ie they consist of the same sequence of machine instructions.
  • the main processor cores (AI, A2) of the various multi-core processors (MCI, MC2) are synchronized with one another, which is represented schematically in FIG. 1 by a synchronization unit (SE).
  • SE synchronization unit
  • Such synchronization between the main processor cores (Al, A2) for example, by synchronizing views, ie special Clicks of the Pro ⁇ programs or certain accesses such as Spei ⁇ cherzugriffe by the hardware.
  • the outputs of the main processor cores (Al, A2) are preferably such ⁇ syn chronized that their outputs made within ys and for example, a trailing Voterbaustein (V) during output can be compared.
  • the slave processor cores (Bl, B2, B3, B4) are not included in this Syn ⁇ chronization, but run essentially self-sufficient to himself. Thus, only the respective main processor cores (AI, A2) of the various multi-core processors (MCI, MC2) synchronize with one another.
  • the Volunteerrete-cores (Bl, B2, B3, B4) serve to abar ⁇ the Nutzprogramme and are controlled by the respective main processor core (AI, A2).
  • the control ie the distribution of the programs, subprograms or tasks to the respective secondary Processor cores (Bl, B2, B3, B4) is similar in each Mehrkernpro ⁇ processor (MCI, MC2), ie, in other words runs in each multi-core processor (MCI, MC2) from the same procedure.
  • outputs are generated, which are the respective main processor core (AI, A2) of the same multi-core processor (MCI, MC2) are provided. Subsequently, synchronous output of outputs of the plurality of multi-core processors (MCI, MC2) is effected by the respective main processor core (AI, A2).
  • the main processor core (AI, A2) thus acts as a synchronization master, while the sub-processor cores (Bl, B2, B3, B4) act as slave computation.
  • the additional secondary processor cores (Bl, B2, B3, B4) do not disturb this synchronization since they do not participate in the synchronization.
  • the computing power of the sub-processor cores (Bl, B2, B3, B4) can be used from ⁇ without it comes to synchronization interference, because this task is only exerted by the respec ⁇ gene main processor core (AI, A2). Due to the functional distribution of the utility programs over several processor cores and the corresponding concurrency (parallel processing), a linear increase of the computing power can take place according to the number of processor cores.
  • Input / output takes place via an input / output unit (El, E2), whereby only respective main processor cores have corresponding input / output units (El, E2). Input / output are also included in the synchronization of the main processor cores (AI, A2).
  • the respective subprocessor cores (Bl, B2, B3, B4) do not have input / output units. This also means that the secondary processor cores (Bl, B2, B3, B4) are decoupled from interrupts of the input / output units (El, E2).
  • the communication between the main processor core (AI, A2) and the at least one slave processor core (B1, B2, B3, B4) is realized by messages using a shared memory (M1, M2).
  • the sub-processor cores (Bl, B2, B3, B4) can be operated as virtual processor cores by virtue of virtualization support.
  • An operating system can then be provided on these processor cores, which enables communication between processor cores by means of message exchange with the respective main processor core (AI, A2).
  • the transfer of the messages can take place via the shared memory areas (M1, M2) (shared memory areas) by means of locking protocols in order to avoid access conflicts to the shared memory (M1, M2).
  • the main processor core (AI, A2) has set up the memory allocation here.
  • the main processor core (AI) of the first multi-core processor (MCI) passes on its time increment (II) to the two slave processor cores (Bl, B2).
  • the main processor core (A2) of the second multi-core processor (MC2) likewise passes on its time increment (12) to the associated two secondary processor cores (B3, B4).
  • the time increments (II, 12) for example, every 20 ms and are synchronous zueinan ⁇ the.
  • the time increments (II, 12) can be used to provide compiler programs or intermediate processing tasks that are sorted according to priorities or other criteria in a queue, for example. This corresponds to a preemptive multitasking system with priority-driven methodology.
  • the processing of the clock time increments is described in more detail in the following sections.
  • system calls are functions of the operating system.
  • the system calls can be, for example Synchronisati ⁇ onsanstShe that are not used for synchronization.
  • this first processing phase of the cyclic process is performed in the respective sub-processor cores (Bl, B2, B3, B4).
  • the incoming messages and outgoing messages are guided by waiting lists and transmitted at certain synchronous times between slave processors cores (Bl, B2, B3, B4) and main processor cores (AI, A2) by accessing the common memory area (M1, M2). This can be done, for example, every 100 ms or every 200 ms at synchronous times.
  • the synchronous time by actively waiting for a Uhrzeitinkrement (II, 12) scored the ⁇ .
  • the first processing phase it is also checked whether a corresponding time increment (II, 12) is pending or it is actively waiting for the next time increment (II, 12) for coarse synchronization of the slave processors cores (Bl, B2, B3, B4) small differences in runtime make it easier for a task change to take place, for example.
  • the first processing phase updates a possibly existing time counter, e.g. B. a ms time counter, which is primarily responsible for the determination of time differences, and jumps back to the call point.
  • the processing of the utility programs is part of the second processing phase, the actual computing phase of Maupro ⁇ zessorkerne (Bl, B2, B3, B4).
  • the operating system of the sub-processor cores also runs.
  • the second processing phase ie the pure processing phase se, is independent of the first processing phase, ie it gets nothing from the processes of the first processing phase.
  • the first processing phase also records the number of
  • Main processor cores do not have to occur after each time increment (II, 12), but can also be done at coarsened time intervals, for example all
  • cycles are only at or above the increased time interval, for example at 100 ms, 200 ms or even 500 ms.
  • the invention also includes that the secondary processor cores (B1, B2, B3, B4) can also be designed as hyperthreading cores.
  • the process is therefore fundamentally ⁇ additionally executed well on hyperthreading-enabled processors.
  • B4 Bl, B2, B3 can at Nutzprogrammen with, for example, well-known ter maturity that the slave processors are processed, where neither an operating system for multitasking nor a Uhrzeitinkrement (12 II) required ⁇ to, a delay time which is greater than the runtime of the utility programs, can be implemented, after which the calculated outputs are transferred synchronously to the main processor cores (AI, A2).
  • the delay time is to be chosen entspre ⁇ accordingly so that to be calculated expenditure NEN upon expiration of the delay time in the different Maureaorker- (Bl, B2, B3, B4) are present, so that a synchronous over- were despite possible propagation time differences to the respective main processor core (AI, A2) becomes possible.
  • the expiry of the delay time is actively maintained.
  • the method is basically also operable with only a multi-core processor and therefore included by the invention, for. B. development and test runs simplified to un ⁇ support. Then correspondingly eliminates the synchronization with other channels, as they are not available.
  • the subprocessor cores Bl, B2, B3, B4
  • the subprocessor cores B1, B2 , B3, B4 are continuously formed over the memory used a hash value and transferred to the adjustment to the associated main processor core (AI, A2).
  • the respective main processor core (AI, A2) does not need to receive any project-specific applications or utility programs, since the computing power for the specific
  • FIG. 2 schematically summarizes the method according to the invention for the synchronized operation of a plurality of multi-core processors.
  • a first step (S1) provision is made of a plurality of multi-core processors (MCI, MC2), each comprising a main processor core (AI, A2), at least one slave processor core (B1, B2, B3, B4), which serves to process useful programs .
  • a second step (S2) is carried out to synchronize the first multi-core processor (MCI) to the second multi-core processor (MC2), such that only the respective main processor core (AI) of the first multi-core processor (MCI) to the main processor ⁇ core (A2) of the second multi-core processor (MC2) synchronized.
  • a third step (S3) the at least one slave processor core (Bl, B2, B3, B4) is controlled by the respective main processor core (AI, A2) in each multi-core processor (MCI, MC2).
  • the control of the at least one secondary processor core (Bl, B2, B3, B4) takes place in each multi-core ⁇ processor (MCI, MC2) in the same way.
  • the outputs of the plurality of outputs are output synchronously
  • Multi-core processors MCI, MC2 through the respective main processor core (AI, A2).
  • a method for synchronized operation of a plurality of multi-core processors (MCI, MC2) in which synchronized outputs are generated, whereby the computing capacities of the multi-core processors (MCI, MC2) are utilized to execute programs in parallel.
  • the task areas between the different processor cores are hierarchized within a multi-core processor (MCI, MC2), one main processor core (AI, A2) acting as synchronization master and the secondary processor cores (B1, B2, B3, B4) being assigned to slave processors.
  • Calculating cowmen are graded, which do not interfere with the synchronization of the Hauptsprozes ⁇ sorkerne (AI, A2).
  • MCI MCI, MC2 multi-core processor

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)

Abstract

La présente invention concerne un procédé de fonctionnement synchronisé d'une pluralité de processeurs multicoeurs (MC1, MC2), un premier (MC1) et un deuxième processeur multicoeur (MC2) comprenant chacun un noyau de processeur maître (A1, A2) et au moins un noyau de processeur esclave (B1, B2, B3, B4) étant fourni, lequel sert à l'exécution de programmes informatiques utilitaires. Seuls les coeurs des processeurs maîtres (A1, A2) des différents processeurs multicoeurs (MC1, MC2) synchronisent les uns avec les autres. L'au moins un noyau de processeur esclave (B1, B2, B3, B4) est commandé par le noyau de processeur maître (A1, A2) respectif dans chaque processeur multicoeur (MC1, MC2). Les programmes informatiques utilitaires sont exécutés par l'au moins un noyau de processeur esclave (B1, B2, B3, B4) et des sorties, lesquelles correspondent au noyau de processeur maître (A1, A2) respectif du même processeur multicoeur (MC1, MC2), sont mises à la disposition. Les sorties de la pluralité de processeurs multicoeurs (MC1, MC2) sont ensuite fournies synchroniquement au moyen du noyau de processeur maître (A1, A2) respectif.
EP17733365.5A 2016-06-23 2017-06-01 Procédé de fonctionnement synchronisé de processeurs multicoeurs Ceased EP3449366A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102016211286.4A DE102016211286A1 (de) 2016-06-23 2016-06-23 Verfahren zum synchronisierten Betrieb von Mehrkernprozessoren
PCT/EP2017/063260 WO2017220305A1 (fr) 2016-06-23 2017-06-01 Procédé de fonctionnement synchronisé de processeurs multicoeurs

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US (1) US11301308B2 (fr)
EP (1) EP3449366A1 (fr)
CN (1) CN109313581B (fr)
DE (1) DE102016211286A1 (fr)
WO (1) WO2017220305A1 (fr)

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CN109313581B (zh) 2022-06-24
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DE102016211286A1 (de) 2017-12-28
US11301308B2 (en) 2022-04-12

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