EP3398408B1 - Optoelektronische schaltung mit leuchtdioden - Google Patents
Optoelektronische schaltung mit leuchtdioden Download PDFInfo
- Publication number
- EP3398408B1 EP3398408B1 EP16829294.4A EP16829294A EP3398408B1 EP 3398408 B1 EP3398408 B1 EP 3398408B1 EP 16829294 A EP16829294 A EP 16829294A EP 3398408 B1 EP3398408 B1 EP 3398408B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- circuit
- light
- module
- emitting diodes
- elementary
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Not-in-force
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/40—Details of LED load circuits
- H05B45/44—Details of LED load circuits with an active control inside an LED matrix
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/40—Details of LED load circuits
- H05B45/44—Details of LED load circuits with an active control inside an LED matrix
- H05B45/48—Details of LED load circuits with an active control inside an LED matrix having LEDs organised in strings and incorporating parallel shunting devices
Definitions
- the present description relates to an optoelectronic circuit, in particular an optoelectronic circuit comprising light-emitting diodes.
- an optoelectronic circuit For certain applications, it is known to successively activate sets of light-emitting diodes of an optoelectronic circuit.
- One example relates to the power supply of an optoelectronic circuit comprising light-emitting diodes with an alternating voltage, in particular a sinusoidal voltage, for example the mains voltage.
- the figure 1 represents an example of an optoelectronic circuit 10 comprising input terminals IN 1 and IN 2 between which an AC voltage V IN is applied.
- the optoelectronic circuit 10 further comprises a rectifying circuit 12 comprising a diode bridge 14, receiving the voltage V IN and providing a rectified voltage V ALIM which supplies N sets of elementary light-emitting diodes, called global light-emitting diodes D i , where i is a whole number ranging from 1 to N.
- the elementary light emitting diodes of each global light emitting diode D i are preferably in series.
- the optoelectronic circuit 10 comprises a current source 22, one terminal of which is connected to the node A 2 and the other terminal of which is connected to a node A 3 .
- the circuit 10 comprises a device 24 for switching the global light-emitting diodes D i , i ranging from 1 to N.
- the switching device 24 makes it possible to progressively increase the number of global light-emitting diodes receiving the supply voltage V ALIM during an increasing phase of the supply voltage V ALIM and gradually reduce the number of global light emitting diodes receiving the supply voltage V ALIM during a decreasing phase of the supply voltage V ALIM . This makes it possible to reduce the duration during which no light is emitted by the optoelectronic circuit 10.
- the device 24 comprises N controllable switches SW 1 to SWN.
- Each switch SW i , i ranging from 1 to N, is mounted between the node A 3 and the cathode of the global light emitting diode D i and is controlled by a control module 26 as a function of signals provided by a sensor 28.
- the order of closing and opening of the switches SW i is fixed by the structure of the optoelectronic circuit 10 and is repeated for each cycle of the supply voltage V ALIM .
- the figure 2 is a timing diagram of the supply voltage V ALIM in the case where the alternating voltage V IN corresponds to a sinusoidal voltage and for an example in which the optoelectronic circuit 10 comprises four global light-emitting diodes D 1 , D 2 , D 3 and D 4 .
- the respective emission phases P 1 , P 2 , P 3 and P 4 of the global light emitting diodes D 1 , D 2 , D 3 and D 4 are represented schematically.
- the conduction time of the global light-emitting diode D 4 is much shorter than that of the global light-emitting diode D 1 .
- a disadvantage of the optoelectronic circuit 10 is that, according to the configuration of the optoelectronic circuit 10, an observer can perceive an inhomogeneity of the light power emitted by the optoelectronic circuit 10, especially when the global light emitting diodes are distant from each other.
- the figure 3 represents, partially and schematically, a top view of the optoelectronic circuit 10 comprising a zone 30 in which are formed the global light emitting diodes D 1 to D 4 and a zone 32 in which are formed the other elements of the optoelectronic circuit 10.
- the global light emitting diodes D 1 to D 4 are substantially aligned and arranged next to each other.
- an observer can perceive, in particular when the global light-emitting diodes are large or spaced apart, a light power emitted by the area 30 of the optoelectronic circuit 10 which is larger on the side of the global light-emitting diode D 1 , whose light emission duration is the largest, that the side of the global light emitting diode D 4 , whose light emission time is the lowest.
- An object of an embodiment is to overcome all or part of the disadvantages of the optoelectronic circuits described above comprising global light emitting diodes and a switching device of light emitting diodes.
- Another object of an embodiment is to improve the homogeneity of light emission by the optoelectronic circuit.
- Another object of an embodiment is that the number of elementary light-emitting diodes of each global light-emitting diode of the optoelectronic circuit can be modified simply.
- an embodiment provides an optoelectronic circuit comprising series-connected assemblies of electroluminescent diodes and a control module of said sets, the light-emitting diode assemblies being arranged on a support and being distributed on a succession of elementary circuits aligned and located on the support, each elementary circuit comprising at least one light-emitting diode of each set.
- each set comprises groups, connected in parallel, of light-emitting diodes.
- each elementary circuit comprises the light-emitting diodes of at least one of the groups of said set.
- each elementary circuit is divided into circuit segments, and, for each group, the light emitting diodes of said group are distributed over all the circuit segments.
- the circuit segments are aligned.
- each elementary circuit further comprises a current limiting circuit.
- the current limiting circuits are connected in parallel.
- each current limiting circuit comprises a resistor.
- the same elements have been designated by the same references in the various figures and, in addition, the various figures are not drawn to scale.
- the terms “substantially”, “about” and “of the order of” mean “to within 10%”.
- the term “connected” is used to designate a direct electrical connection, without intermediate electronic component, for example by means of a conductive track, and the term “coupled” or the term “connected”, to designate either a direct electrical connection (meaning “connected") or a connection via one or more intermediate components (resistor, capacitor, etc.).
- the global light-emitting diodes are made in a modular manner and are distributed according to several light-emitting diode modules, called optical modules or optical circuits thereafter, connected to each other.
- the elementary light-emitting diodes of each global light-emitting diode are distributed on each optical module.
- the optical modules all have the same structure. This advantageously makes it possible to easily add an optical module to the optoelectronic circuit or to easily remove an optical module from the optoelectronic circuit.
- the elementary light-emitting diodes are, for example, planar light-emitting diodes, each comprising a stack of layers resting on a plane face, of which at least one active layer adapted to emit light.
- the elementary light-emitting diodes are, for example, electroluminescent diodes formed from three-dimensional semiconductor elements, in particular microwires, nanowires or pyramids, comprising, for example, a semiconductor material based on a compound comprising predominantly at least one group III element and a group V element (For example gallium nitride GaN), hereinafter called compound III-V, or comprising predominantly at least one group II element and a group VI element (for example zinc oxide ZnO), called by the compound sequence II-VI.
- Each three-dimensional semiconductor element is covered with at least one active layer adapted to emit light.
- the figure 4 represents an embodiment of an optoelectronic circuit 40.
- the elements common with the optoelectronic circuit 10 are designated by the same references.
- the optoelectronic circuit 40 comprises the rectifier circuit 12, the current source 22, the control module 26, the sensor 28 and the switches SW 1 to SW N which are distributed in a module 0 , called the control module by the after.
- the elementary light-emitting diodes which form each global light-emitting diode D i , i ranging from 1 to N, are distributed over K optical modules, K being an integer greater than or equal to 2, for example between 2 and 100.
- figure 4 four optical modules Module 1 , Module 2 , Module 3 and Module 4 are shown.
- the elementary light-emitting diodes of each global light-emitting diode D i are distributed in K groups D i, j of elementary light-emitting diodes, j being an integer ranging from 1 to K, each group D i, j belonging to the optical module Module j .
- the groups D i, j , j varying from 1 to K are connected in parallel for each global light emitting diode D i .
- the elementary light-emitting diodes of each group D i, j are connected in series.
- Each optical module Module j comprises input nodes IN i, j and output nodes OUT i, j where i is an integer varying from 1 to N + 3 in the present embodiment, for example from 4 to 103.
- the optical modules Module j all have the same number of input nodes IN i, j and, for each optical module Module j , the number of input nodes IN i, j is equal to the number of output nodes OUT i, j .
- the nodes IN i, j and OUT i, j are connected to the anode of the group D i, j , for i varying from 1 to N.
- Module 0 control module further includes output nodes OUT i, 0 , i ranging from 1 to N + 3 in the present embodiment.
- the output node OUT 1.0 is connected to the node A 1 and the output node OUT N + 3.0 is connected to the node A 2 .
- the optical modules Module 1 to Module K are identical.
- the modules are connected successively to each other.
- the input nodes IN i, 1 of the first optical module Module 1 of the succession of optical modules are connected to the output nodes OUT i, 0 of the module control module 0 and the output nodes OUT i, j of each optical module Module j , j varying from 1 to K, are connected to the input nodes IN i, j + 1 of the following optical module Module j + 1 .
- the addition of an additional optical module to the succession of optical modules can, advantageously, be achieved in a simple manner.
- the addition of an additional optical module to the optoelectronic circuit 40 causes the addition of elementary light-emitting diodes to each global light-emitting diode D i .
- V ALIM supply voltage
- the light emission of each global light-emitting diode is thus distributed on each optical module.
- each Module module j further comprises a current limiting circuit R j .
- the circuit R j may correspond to a resistor.
- the nodes IN N + 2, j and OUT N + 2, j are connected to a terminal of the current limiting circuit R j and the nodes IN N + 3, j and OUT N + 3, j are connected to the other terminal of the current limiting circuit R j .
- the current limiting circuits R 1 to R K are then connected in parallel.
- the current source 22 may be of resistive nature. In this case, the resistors R 1 to R K can play the role of the current source and be connected in parallel between the nodes A 2 and A 3 .
- the current source 22 is an active current source, notably comprising metal oxide gate field effect transistors or MOS transistors.
- the voltage across the resistors R 1 to R K connected in parallel can be used by the current source 22 to adapt the intensity of the current I CS .
- the resistance of the additional optical module is connected in parallel across the resistors of the other optical modules. This can cause a change in the intensity of the current I CS so as to take account of the presence of the additional optical module.
- each module Module 0 to Module 1 corresponds to a separate integrated circuit chip, the integrated circuit chips being mounted on a printed circuit to be connected to each other.
- several optical modules are formed on the same integrated circuit chip.
- the modules Module 0 to Module 1 are formed on the same integrated circuit chip. The modules are preferably aligned to form a module strip.
- the figure 5 illustrates an embodiment of a method of manufacturing an optoelectronic circuit similar to the optoelectronic circuit 40.
- a first optoelectronic circuit 50 is formed on a support 52 and comprises successive series of optical modules separated by a control module.
- the optical modules and the control modules may have the structures described above in connection with the figure 4 .
- the series of optical modules may comprise the same number of optical modules or comprise different numbers of optical modules.
- the optoelectronic circuit 50 successively comprises, from the left to the right, a Module 0 control module, three successive optical modules Module 1 , Module 2 , Module 3 , a module control module ' 0 and two successive optical modules Module' 1 and Module ' 2 .
- the groups of elementary light-emitting diodes D i, j are represented by rectangles, the resistance R j by a hatched rectangle and the connections between modules by horizontal lines in dashed lines.
- the repetition frequency of the Module 0 control modules depends on the maximum permissible power of the switches of the Module 0 control module. According to one embodiment, when a Module 0 control module is located between two optical modules, the input nodes IN 1 and IN 2 of this control module are respectively connected to the output nodes OUT 1, K and OUT N + 3, K of the above optical module.
- the Module 0 control modules have the same structure which can be that represented in FIG. figure 4 .
- only one of the Module 0 control modules comprises the rectifier circuit 12, the other Module ' 0 control modules not comprising the rectifier circuit 12 and having their input node IN 1 directly connected to the node A 1 and their input node IN 2 directly connected to the node A 2 .
- none of the Module 0 control modules includes the rectifier circuit 12, the rectifier circuit being provided on a separate circuit if its use is necessary according to the intended application.
- Optoelectronic circuits can be produced from the optoelectronic circuit 50 by cutting out the optoelectronic circuit 50.
- the optoelectronic circuit 55 shown in FIG. figure 5 can be obtained by cutting the optoelectronic circuit 50 at the vertical line 56 and the optoelectronic circuit 57 shown below in figure 5 can be obtained by cutting the optoelectronic circuit at the vertical line 58.
- the modules are arranged one after the other in the form of a band so that the cutting of the optoelectronic circuit 50 is facilitated.
- the Figures 6 and 7 represent embodiments of groups D 1, j to D N, j of light-emitting diodes of an optical module Module j .
- Each group of elementary light-emitting diodes D 1, j comprises a number M of LED elementary light-emitting diodes.
- the M * N elementary light-emitting diodes are divided into an integer number P of segments Seg q, j , where q is an integer ranging from 1 to P, each segment Seg q, j comprising an elementary light-emitting diode of each group of elementary light-emitting diodes D 1, j to D N, j .
- each elementary light-emitting diode is schematically represented by an LED square containing the electrical symbol of a light-emitting diode.
- conductive traces of a first metallization level are represented by single-hatched strips 60 and conductive tracks of a metallization level higher than the first level by double-hatched strips 62.
- Each vertical band 62 is extended by a circle 64 which corresponds to the connection (for example a via) connecting the conductive track 62 to one of the conductive tracks 60.
- each module Module j comprises four groups D i, j , and each group comprises three diodes LED elemental electroluminescent elements in three segments Seg 1, j , Seg 2, j and Seg 3, j .
- the elementary LEDs of group D 1 were surrounded by a dashed line and the LED elementary LEDs of group D 2, j , were surrounded by a dashed line.
- the arrangement of the LED elementary LEDs is identical for each segment Seg q, j .
- Each group D 1, j to D N, j comprises at least one elementary light emitting diode Seg q, j .
- the arrangement of the conductive tracks 60, 62 of the intermediate segments Seg q, j , q varying from 2 to P-1 is identical and the arrangement of the conductive tracks 60, 62 of the first segment Seg 1, j and the last segment Seg P, j is different from the arrangement of the conductive tracks 60, 62 of the intermediate segments Seg 2, j to Seg P-1, j .
- the LED elementary LEDs of each group D 1, j to D N, j are connected in series and the groups D 1, j to D N, j are connected in series.
- the LED elementary LEDs are aligned.
- the first elementary light-emitting diode belongs to the first group D 1, j
- the second elementary light-emitting diode belongs to the second group D 2, j and so on.
- the LED elementary LEDs are arranged at the corners of a square, the elementary light-emitting diode located at the same corner for each segment belonging to the same group.
Landscapes
- Led Devices (AREA)
Claims (11)
- Optoelektronische Schaltung (40) mit in Reihe geschalteten Anordnungen (Di) von lichtemittierenden Dioden (LED) und einem Modul (Moduleo) zum Steuern der Anordnungen, dadurch gekennzeichnet, dass die Anordnungen von lichtemittierenden Dioden auf einem Träger (52) angeordnet sind und in einer Folge von ausgerichteten elementaren Schaltungen (Modulej) verteilt sind, die auf dem Träger angeordnet sind, wobei jede elementare Schaltung mindestens eine lichtemittierende Diode jeder Anordnung umfasst.
- Optoelektronische Schaltung nach Anspruch 1, wobei jede Anordnung (Di) Gruppen (Di,1, Di,2) von parallel geschalteten lichtemittierenden Dioden aufweist.
- Optoelektronische Schaltung nach Anspruch 2, wobei für jede Anordnung (Di) jede Elementarschaltung (Modulej) die lichtemittierenden Dioden (LED) von mindestens einer der Gruppen der Anordnung aufweist.
- Optoelektronische Schaltung nach Anspruch 3, wobei jede Elementarschaltung (Modulej) in Schaltungssegmente (Seg1,j, Seg2,j, Seg3,j) unterteilt ist, und wobei für jede Gruppe (D1,j, DN,j) die lichtemittierenden Dioden (LED) der Gruppe über alle Schaltungssegmente verteilt sind.
- Optoelektronische Schaltung nach Anspruch 4, wobei die Schaltungssegmente (Seg1,j, Seg2,j, Seg3,j) ausgerichtet sind.
- Optoelektronische Schaltung nach einem der Ansprüche 1 bis 5, wobei jede Elementarschaltung (Modulej) ferner eine Strom-Begrenzungsschaltung (Rj) aufweist.
- Optoelektronische Schaltung nach Anspruch 6, wobei die Strom-Begrenzungsschaltungen (Rj) parallel geschaltet sind.
- Optoelektronische Schaltung nach Anspruch 6 oder 7, wobei jede Strom-Begrenzungsschaltung (Rj) einen Widerstand aufweist.
- Optoelektronische Schaltung nach einem der Ansprüche 1 bis 8, die auf dem Träger (52), wenigstens Folgendes in ausgerichteter Weise und aufeinanderfolgender Weise aufweist:das Steuermodul (Moduleo); unddie Anordnungen von lichtemittierenden Dioden, die über die Folge von Elementarschaltungen (Module1, Module2, Module3) verteilt sind.
- Optoelektronische Schaltung nach Anspruch 9, ferner aufweisend:ein zusätzliches Steuermodul (Module'0); undzusätzliche Anordnungen von lichtemittierenden Dioden, die über eine zusätzliche Folge von Elementarschaltungen (Module'1, Module'2) verteilt sind, die auf aufeinanderfolgenden ausgerichteten Abschnitten des Trägers angeordnet sind, wobei jede Elementarschaltung der zusätzlichen Folge wenigstens eine lichtemittierende Diode jeder zusätzlichen Anordnung umfasst.
- Verfahren zur Herstellung der optoelektronischen Schaltung nach einem der Ansprüche 1 bis 10, das die folgenden Schritte aufweist:Herstellen einer anfänglichen optoelektronischen Schaltung (50), die die in Reihe geschalteten Anordnungen von lichtemittierenden Dioden und das Modul zum Steuern der Anordnungen aufweist, sowie zusätzliche Anordnungen von lichtemittierenden Dioden, die über eine zusätzliche Folge von ausgerichteten elementaren Schaltungen verteilt sind, die auf dem Träger angeordnet sind, wobei jede elementare Schaltung der zusätzlichen Folge wenigstens eine lichtemittierende Diode jeder zusätzlichen Anordnung aufweist; undSchneiden der anfänglichen optoelektronischen Schaltung, um die zusätzlichen Anordnungen zu entfernen.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1563433A FR3046294A1 (fr) | 2015-12-29 | 2015-12-29 | Circuit optoelectronique a diodes electroluminescentes |
PCT/FR2016/053675 WO2017115049A1 (fr) | 2015-12-29 | 2016-12-28 | Circuit optoelectronique a diodes electroluminescentes |
Publications (2)
Publication Number | Publication Date |
---|---|
EP3398408A1 EP3398408A1 (de) | 2018-11-07 |
EP3398408B1 true EP3398408B1 (de) | 2019-10-09 |
Family
ID=55759753
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP16829294.4A Not-in-force EP3398408B1 (de) | 2015-12-29 | 2016-12-28 | Optoelektronische schaltung mit leuchtdioden |
Country Status (4)
Country | Link |
---|---|
US (1) | US20190342956A1 (de) |
EP (1) | EP3398408B1 (de) |
FR (1) | FR3046294A1 (de) |
WO (1) | WO2017115049A1 (de) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040233145A1 (en) * | 2003-05-19 | 2004-11-25 | Add Microtech Corp. | LED driving device |
US20080265795A1 (en) * | 2005-12-14 | 2008-10-30 | Koninklijke Philips Electronics, N.V. | Circuit-Arrangement for Modulating an Led and Method for Operating Same |
US20110080101A1 (en) * | 2009-10-02 | 2011-04-07 | Optromax Electronics Co., Ltd | Electronic device |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4899651B2 (ja) * | 2006-06-07 | 2012-03-21 | ソニー株式会社 | 発光ダイオード点灯回路、照明装置及び液晶表示装置 |
CN101669404B (zh) * | 2007-04-24 | 2012-03-28 | 皇家飞利浦电子股份有限公司 | 具有移位寄存器和电平移动器的led串驱动器 |
US9538596B2 (en) * | 2011-02-04 | 2017-01-03 | Philips Lighting Holding B.V. | Lighting unit with LED strip |
US9538590B2 (en) * | 2012-03-30 | 2017-01-03 | Cree, Inc. | Solid state lighting apparatuses, systems, and related methods |
US8704448B2 (en) * | 2012-09-06 | 2014-04-22 | Cooledge Lighting Inc. | Wiring boards for array-based electronic devices |
CN103388805B (zh) * | 2013-07-01 | 2015-03-18 | 临安市新三联照明电器有限公司 | 一种基于支架料板的led灯丝支架成型方法 |
WO2016205271A1 (en) * | 2015-06-15 | 2016-12-22 | Cooledge Lighting, Inc. | Arbitrarily sizable broad-area lighting system |
-
2015
- 2015-12-29 FR FR1563433A patent/FR3046294A1/fr not_active Withdrawn
-
2016
- 2016-12-28 US US16/066,622 patent/US20190342956A1/en not_active Abandoned
- 2016-12-28 EP EP16829294.4A patent/EP3398408B1/de not_active Not-in-force
- 2016-12-28 WO PCT/FR2016/053675 patent/WO2017115049A1/fr active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040233145A1 (en) * | 2003-05-19 | 2004-11-25 | Add Microtech Corp. | LED driving device |
US20080265795A1 (en) * | 2005-12-14 | 2008-10-30 | Koninklijke Philips Electronics, N.V. | Circuit-Arrangement for Modulating an Led and Method for Operating Same |
US20110080101A1 (en) * | 2009-10-02 | 2011-04-07 | Optromax Electronics Co., Ltd | Electronic device |
Also Published As
Publication number | Publication date |
---|---|
EP3398408A1 (de) | 2018-11-07 |
FR3046294A1 (fr) | 2017-06-30 |
US20190342956A1 (en) | 2019-11-07 |
WO2017115049A1 (fr) | 2017-07-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
FR2613135A1 (fr) | Element recepteur de lumiere pour circuits de commutation | |
FR3023066A1 (fr) | Dispositif optoelectronique comprenant des diodes electroluminescentes et un circuit de commande | |
EP3484039B1 (de) | Schaltmodul für spannungswechsel- oder gleichrichter | |
EP2219287B1 (de) | Spannungswechselrichter für 3N-4-Niveau | |
FR2491253A1 (fr) | Support pour relais | |
WO2017046048A1 (fr) | Source lumineuse led a micro- ou nano-fils comprenant des moyens de mesure de la temperature | |
EP3344024B1 (de) | Drehstrom-umschaltmodul | |
FR3059439B1 (fr) | Generateur de signal d'horloge | |
EP3398408B1 (de) | Optoelektronische schaltung mit leuchtdioden | |
EP3351057B1 (de) | Leistungsverwaltung für eine mikro- oder nanodraht-led-lichtquelle | |
EP2751916A1 (de) | Leistungsstarker wandler mit parallel geschalteten niedrigenergietransistoren | |
WO2016001201A1 (fr) | Circuit optoelectronique a diodes electroluminescentes | |
FR2538168A1 (fr) | Dispositif semi-conducteur protege contre le claquage du second genre, en particulier transistor de puissance | |
WO2017046107A1 (fr) | Source lumineuse led comprenant un circuit electronique | |
EP3332608B1 (de) | Optoelektronische schaltung mit leuchtdioden | |
EP3840200B1 (de) | Schaltersteuerungssperre | |
WO2017046083A1 (fr) | Gestion de la tension directe d'une source lumineuse led a micro- ou nano-fils | |
WO2015121502A1 (fr) | Circuit optoelectronique a diodes electroluminescentes | |
FR3128351A1 (fr) | Source lumineuse matricielle pour un vehicule automobile | |
David | Study and design of integrated laser diode driver for 3D-depth sensing applications | |
EP3563647A1 (de) | Elektronische struktur mit einem matrix-array aus elektronischen vorrichtungen mit verbesserten thermischen leistungen | |
FR3104862A1 (fr) | Dispositif de commande d’interrupteur | |
FR3111247A1 (fr) | Dispositif de commande d'interrupteur | |
WO2017162982A1 (fr) | Circuit optoelectronique comprenant des diodes electroluminescentes | |
FR2530391A1 (fr) | Montage de circuits pour le redoublement d'un signal, comportant un discriminateur de flancs pour etre convertis en signaux de meme forme |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: UNKNOWN |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE |
|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE |
|
17P | Request for examination filed |
Effective date: 20180613 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
AX | Request for extension of the european patent |
Extension state: BA ME |
|
DAV | Request for validation of the european patent (deleted) | ||
DAX | Request for extension of the european patent (deleted) | ||
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: GRANT OF PATENT IS INTENDED |
|
INTG | Intention to grant announced |
Effective date: 20190528 |
|
GRAJ | Information related to disapproval of communication of intention to grant by the applicant or resumption of examination proceedings by the epo deleted |
Free format text: ORIGINAL CODE: EPIDOSDIGR1 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE |
|
GRAR | Information related to intention to grant a patent recorded |
Free format text: ORIGINAL CODE: EPIDOSNIGR71 |
|
GRAS | Grant fee paid |
Free format text: ORIGINAL CODE: EPIDOSNIGR3 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: GRANT OF PATENT IS INTENDED |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE PATENT HAS BEEN GRANTED |
|
INTC | Intention to grant announced (deleted) | ||
INTG | Intention to grant announced |
Effective date: 20190828 |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D Free format text: NOT ENGLISH |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: EP |
|
REG | Reference to a national code |
Ref country code: IE Ref legal event code: FG4D Free format text: LANGUAGE OF EP DOCUMENT: FRENCH |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R096 Ref document number: 602016022329 Country of ref document: DE |
|
REG | Reference to a national code |
Ref country code: AT Ref legal event code: REF Ref document number: 1190354 Country of ref document: AT Kind code of ref document: T Effective date: 20191115 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R079 Ref document number: 602016022329 Country of ref document: DE Free format text: PREVIOUS MAIN CLASS: H05B0033080000 Ipc: H05B0045000000 |
|
REG | Reference to a national code |
Ref country code: NL Ref legal event code: MP Effective date: 20191009 |
|
REG | Reference to a national code |
Ref country code: LT Ref legal event code: MG4D |
|
REG | Reference to a national code |
Ref country code: AT Ref legal event code: MK05 Ref document number: 1190354 Country of ref document: AT Kind code of ref document: T Effective date: 20191009 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: NO Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20200109 Ref country code: PL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20191009 Ref country code: LV Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20191009 Ref country code: SE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20191009 Ref country code: AT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20191009 Ref country code: FI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20191009 Ref country code: GR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20200110 Ref country code: BG Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20200109 Ref country code: NL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20191009 Ref country code: PT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20200210 Ref country code: ES Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20191009 Ref country code: LT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20191009 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IS Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20200224 Ref country code: HR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20191009 Ref country code: RS Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20191009 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: AL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20191009 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R097 Ref document number: 602016022329 Country of ref document: DE |
|
PG2D | Information on lapse in contracting state deleted |
Ref country code: IS |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: CZ Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20191009 Ref country code: RO Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20191009 Ref country code: EE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20191009 Ref country code: DK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20191009 Ref country code: IS Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20200209 |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: PL |
|
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
REG | Reference to a national code |
Ref country code: BE Ref legal event code: MM Effective date: 20191231 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: MC Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20191009 Ref country code: SM Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20191009 Ref country code: IT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20191009 Ref country code: SK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20191009 |
|
26N | No opposition filed |
Effective date: 20200710 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: LU Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20191228 Ref country code: IE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20191228 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: CH Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20191231 Ref country code: BE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20191231 Ref country code: LI Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20191231 Ref country code: SI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20191009 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 20201229 Year of fee payment: 5 Ref country code: GB Payment date: 20201217 Year of fee payment: 5 Ref country code: DE Payment date: 20201209 Year of fee payment: 5 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: CY Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20191009 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: HU Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO Effective date: 20161228 Ref country code: MT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20191009 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: TR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20191009 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: MK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20191009 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R119 Ref document number: 602016022329 Country of ref document: DE |
|
GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20211228 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20211228 Ref country code: DE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20220701 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20211231 |