EP3332608B1 - Optoelektronische schaltung mit leuchtdioden - Google Patents

Optoelektronische schaltung mit leuchtdioden Download PDF

Info

Publication number
EP3332608B1
EP3332608B1 EP16750976.9A EP16750976A EP3332608B1 EP 3332608 B1 EP3332608 B1 EP 3332608B1 EP 16750976 A EP16750976 A EP 16750976A EP 3332608 B1 EP3332608 B1 EP 3332608B1
Authority
EP
European Patent Office
Prior art keywords
current
voltage
switch
phase
optoelectronic circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
EP16750976.9A
Other languages
English (en)
French (fr)
Other versions
EP3332608A1 (de
Inventor
Frédéric MERCIER
David GRAS
Nicolas Joubert
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aledia
Original Assignee
Aledia
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aledia filed Critical Aledia
Publication of EP3332608A1 publication Critical patent/EP3332608A1/de
Application granted granted Critical
Publication of EP3332608B1 publication Critical patent/EP3332608B1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/40—Details of LED load circuits
    • H05B45/44—Details of LED load circuits with an active control inside an LED matrix
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/395—Linear regulators
    • H05B45/397—Current mirror circuits

Definitions

  • the present description relates to an optoelectronic circuit, in particular an optoelectronic circuit comprising light-emitting diodes.
  • an optoelectronic circuit comprising light-emitting diodes with an alternating voltage, in particular a sinusoidal voltage, for example the mains voltage.
  • the figure 1 represents an example of an optoelectronic circuit 10 comprising input terminals IN 1 and IN 2 between which an AC voltage V IN is applied.
  • the optoelectronic circuit 10 further comprises a rectifying circuit 12 comprising a diode bridge 14, receiving the voltage V IN and supplying a rectified voltage V ALIM which supplies light-emitting diodes 16, for example, connected in series with a resistor 15. On Calls I ALIM the current passing through the light-emitting diodes 16.
  • the figure 2 is a timing diagram of the supply voltage V ALIM and the supply current I ALIM for an example in which the AC voltage V IN corresponds to a sinusoidal voltage.
  • the voltage V ALIM is greater than the sum of the threshold voltages of the light-emitting diodes 16, the light-emitting diodes 16 turn on.
  • the supply current I ALIM then follows the supply voltage V ALIM . There is therefore an alternation of OFF phases of absence of light emission and ON phases of light emission.
  • a disadvantage is that as long as the voltage V ALIM is less than the sum of the threshold voltages of the light-emitting diodes 16, no light is emitted by the optoelectronic circuit 10. An observer can perceive this absence of light emission when the duration of each OFF phase of absence of light emission between two ON phases of light emission is too important. One possibility to increase the duration of each ON phase is to reduce the number of light-emitting diodes 16. A disadvantage is that the electrical power lost in the resistance is important.
  • the publication US 2012/0056559 discloses an optoelectronic circuit in which the number of light-emitting diodes receiving the supply voltage V ALIM increases progressively during a phase of growth of the supply voltage and decreases progressively during a phase of decrease of the supply voltage . This is achieved by a switching circuit adapted to short-circuit a larger or smaller number of light-emitting diodes according to the evolution of the voltage V ALIM . This makes it possible to reduce the duration of each phase of absence of light emission.
  • a disadvantage of the optoelectronic circuit described in the publication US 2012/0056559 is that the power supply current of the light emitting diodes does not vary continuously, that is to say that there are sudden interruptions of flow of the current during the variation of the voltage. This causes variations over time in the light intensity provided by electroluminescent diodes that can be perceived by an observer. This also causes a deterioration in the harmonic distortion rate of the current supplying the light-emitting diodes of the optoelectronic circuit.
  • the publication WO 2013/191806 A1 discloses an optoelectronic circuit for receiving a variable voltage and comprising a plurality of sets of light-emitting diodes, said assemblies being connected in series and comprising a current source connected to each assembly by a switch.
  • An object of an embodiment is to overcome all or part of the disadvantages of the optoelectronic circuits described above.
  • Another object of an embodiment is to reduce the duration of the phases of absence of light emission by the optoelectronic circuit.
  • Another object of an embodiment is that the current supplying the light-emitting diodes varies substantially continuously.
  • control module is adapted, during each increasing phase, for each switch, to control the opening of said switch when the current flowing in the adjacent and closed switch goes above the current threshold, and, during each decreasing phase, for each open switch adjacent to a closed switch, controlling the closing of said switch when said voltage drops below the voltage threshold.
  • the current source is adapted to supply a current whose intensity depends on at least one control signal.
  • the current source is adapted to supply a current whose intensity varies among several distinct intensity values as a function of the number of sets traversed by said current during at least one increasing or decreasing phase.
  • the optoelectronic circuit is adapted to receive a modulation signal external to the optoelectronic circuit and the current source is adapted to modify said intensity values as a function of said modulation signal.
  • the current source comprises elementary current sources connected in parallel and adapted to be activated and deactivated independently of one another.
  • the elementary current sources are adapted to supply currents having the same intensity or having different intensities.
  • control module is adapted to activate at least one of the elementary current sources during at least one increasing phase and is adapted to deactivate at least one of the elementary current sources during at least one decreasing phase.
  • one of the elementary current sources is adapted to supply a current having a given intensity and the other elementary current sources are adapted to each provide a current having an intensity equal to the product of a power of two and said given intensity.
  • control module is adapted to control the switches for connecting the light-emitting diode assemblies according to a plurality of connection configurations successively in a first order during each increasing phase of the variable voltage and a second order in the course of each decreasing phase of the variable voltage and is adapted to activate the elementary current sources in a third order during each increasing phase of the variable voltage and to disable the elementary current sources in a fourth order during each increasing phase of the variable voltage.
  • the optoelectronic circuit comprises a memory in which are stored several values of the control signal of the current source each corresponding to the supply by the current source of a current whose intensity varies among said several values. intensity.
  • the optoelectronic circuit comprises means for modifying the evolution profile of the intensity of said current as a function of the number of assemblies crossed by said current during at least one increasing or decreasing phase.
  • the method further comprises the following step: during each increasing phase, for each switch, open said switch when the current flowing in the adjacent and closed switch goes above the current threshold, and, during each decreasing phase, for each open switch adjacent to a closed switch , closing said switch when said voltage drops below the voltage threshold.
  • the current source comprises at least two elementary current sources connected in parallel and at least one of the elementary current sources is activated during at least one increasing phase and at least one of the Elementary current sources are deactivated during at least one decreasing phase.
  • the current source comprises at least three elementary current sources connected in parallel, in which, for at least successive increasing and decreasing phases, the number of activated elementary current sources increases from the beginning to the end of the current.
  • the increasing phase and the number of activated elementary current sources decreases from the beginning to the end of the decreasing phase or in which the number of activated elementary current sources increases and then decreases from the beginning to the end of the increasing phase and the number of sources Activated elementary current increases and then decreases from the beginning to the end of the decreasing phase.
  • the same elements have been designated by the same references in the various figures and, in addition, the various figures are not drawn to scale.
  • the terms “approximately”, “substantially”, and “of the order of” mean within 10%, preferably within 5%.
  • the term “power factor” of an electronic circuit is the ratio between the active power consumed by the electronic circuit and the product of the rms values of the current and of the voltage supplying the electronic circuit.
  • the figure 3 is a circuit diagram of an embodiment of an optoelectronic circuit 20 comprising a light-emitting diode switching device.
  • the elements of the optoelectronic circuit 20 common with the optoelectronic circuit 10 are designated by the same references.
  • the optoelectronic circuit 20 comprises the rectifier circuit 12 receiving the supply voltage V IN between the terminals IN 1 and IN 2 and supplying the voltage V ALIM rectified between nodes A 1 and A 2 .
  • the circuit 20 can directly receive a rectified voltage, the rectifier circuit may then not be present.
  • the potential at the node A 2 may correspond to the low reference potential with respect to which the voltages of the optoelectronic circuit 20 are referenced.
  • the optoelectronic circuit 20 comprises N series sets of elementary light-emitting diodes, called global electroluminescent diodes D i in the remainder of the description, where i is an integer ranging from 1 to N and where N is an integer between 2 and 200
  • Each global light-emitting diode D 1 to D N comprises at least one elementary light-emitting diode and is preferably composed of placing in series and / or in parallel at least two light-emitting diodes. elementary.
  • the N global light-emitting diodes D i are connected in series, the cathode of the global light-emitting diode D i being connected to the anode of the global light-emitting diode D i + 1 , for i ranging from 1 to N- 1.
  • the anode of the global light-emitting diode D 1 is connected to the node A 1 .
  • the global light emitting diodes D i , i ranging from 1 to N may comprise the same number of elementary light emitting diodes or different numbers of elementary light emitting diodes.
  • the figure 4 represents an embodiment of the global light-emitting diode D 1 in which the global light-emitting diode D 1 comprises R branches 26 connected in parallel, each branch comprising S elementary light-emitting diodes 27 connected in series in the same direction, R and S being integers greater than or equal to 1.
  • the figure 5 represents another embodiment of the global light-emitting diode D 1 in which the global light-emitting diode D 1 comprises P blocks 28 connected in series, each block comprising Q elementary light-emitting diodes 27 connected in parallel, P and Q being higher integers or equal to 1 and Q may vary from block to block.
  • the other global light-emitting diodes D 2 to D N may have a structure similar to the global light-emitting diode D 1 shown in FIG. figure 4 or 5 .
  • the elementary light-emitting diodes 27 are, for example, planar light-emitting diodes, each comprising a stack of layers resting on a plane face, of which at least one active layer adapted to emit light.
  • the elementary light-emitting diodes 27 are, for example, light-emitting diodes formed from three-dimensional semiconductor elements, in particular microwires, nanowires or pyramids, comprising, for example, a semiconductor material based on a compound comprising for the most part at least a Group III element and a Group V element (by gallium nitride GaN), hereinafter called compound III-V, or comprising predominantly at least one group II element and a group VI element (for example zinc oxide ZnO), hereinafter called compound II-VI.
  • Each three-dimensional semiconductor element is covered with at least one active layer adapted to emit light.
  • the optoelectronic circuit 20 comprises a current source 30, one terminal of which is connected to the node A 2 and the other terminal of which is connected to a node A 3 .
  • V CS is called the voltage across the current source CS 30 and I the current supplied by the current source 30.
  • the optoelectronic circuit 20 may comprise a circuit, not shown, which provides a reference voltage for supplying the current source, possibly obtained from the voltage V ALIM .
  • the circuit 20 comprises a device 32 for switching the global light-emitting diodes D i , i ranging from 1 to N.
  • the device 32 comprises N-1 controllable switches SW 1 to SW N-1 .
  • Each switch SW i , i ranging from 1 to N-1 is mounted between the node A 3 and the cathode of the global light emitting diode D i .
  • Each switch SW i , i varying from 1 to N-1 is controlled by a signal S i supplied by a control module 34.
  • the current flowing in the switch is called i i SW i and is called I N the current flowing in the global light emitting diode D N.
  • a switch may further be present between the cathode of the global light emitting diode D N and the node A 3 .
  • the current source 30 is also controlled by the control module 34.
  • the control module 34 may, in whole or in part, be realized by a dedicated circuit or may comprise a microprocessor or a microcontroller adapted to execute a sequence of instructions stored in a memory.
  • the signal S i is a binary signal and the switch SW i is open when the signal S i is in a first state, for example the low state, denoted "0", and the switch SW i is closed when the signal S i is in a second state, for example the high state, denoted "1" .
  • Each switch SW i is, for example, a switch based on at least one transistor, in particular a metal oxide oxide or MOS transistor field-effect transistor, enriched (normally closed) or depleted (normally open).
  • each switch SW i corresponds to a MOS transistor, for example N-channel, whose drain is connected to the cathode of the global light emitting diode D i , the source of which is connected to the node A 3 and whose gate receives the signal S i .
  • the optoelectronic circuit 20 comprises, for i varying from 1 to N-1, a current sensor 36 i , provided between the node A 3 and the switch SW i , supplying a signal CUR i to the control module 34.
  • the optoelectronic circuit 20 further comprises a current sensor 36 N provided between the node A 3 and the cathode of the global light-emitting diode D N and supplying a signal CUR N to the control module 34.
  • the optoelectronic circuit 20 comprises a sensor voltage supply 38 provided between the power source 30 and the node A 3 and supplying a signal VOLT to the control module 34.
  • the signal CUR i is representative of the intensity of the current I i .
  • the signal CUR i indicates whether the intensity of the current I i is greater than a current threshold, the current threshold may be the same for each current I i or may be different depending on the current I i considered.
  • the signal VOLT is representative of the voltage V CS .
  • the signal VOLT indicates whether the voltage V CS is greater than a voltage threshold.
  • the voltage sensor 36 may then comprise an operational amplifier mounted as a comparator providing the signal VOLT, the input of which is not invertor is connected to the node A 3 and whose inverting input receives the voltage threshold.
  • the figure 6 shows a circuit diagram of a more detailed embodiment of the current source 30.
  • the power source 30 comprises an ideal current source 40 having a terminal connected to a source of a potential VREF top reference.
  • the other terminal of the current source 40 is connected to the drain of a diode-mounted N-channel transistor MOS 42.
  • the source of the MOS transistor 42 is connected to the node A 2 .
  • the gate of the MOS transistor 42 is connected to the drain of the MOS transistor 42.
  • the high reference potential VREF can be supplied from the voltage V ALIM . It can be constant or vary depending on the voltage V ALIM .
  • the intensity of the current supplied by the current source 30 can be constant or be variable, for example vary according to the voltage V ALIM .
  • the current source 30 comprises an N-channel MOS transistor 44 whose gate is connected to the gate of transistor 42 and whose source is connected to node A 2 .
  • the drain of the transistor 44 is connected to the node A 3 , the voltage sensor 38 not being represented in FIG. figure 6 .
  • the MOS transistors 42 and 44 form a current mirror which reproduces the current I CS supplied by the current source 40, possibly with a multiplicative factor.
  • the figure 7 represents an embodiment of the current sensor 36 i in which the current sensor 36 i comprises a resistor 46 i connected in series between the node A 3 and the switch SW i , shown in FIG. figure 7 by a MOS transistor, and an operational amplifier 48 i mounted as a comparator providing the signal CUR i , whose non-inverting input (+) is connected to a terminal of the resistor 46 i and whose inverting input (-) is connected at the other terminal of the resistance 46 i .
  • the amplifier 48 i comprises a terminal for adjusting the offset voltage V offset , or reference voltage, of the amplifier.
  • the amplifier 48 i supplies the signal CUR i to a first state when the voltage between the terminals of the resistor 46 i is greater than the offset voltage V offset and to a second state when the voltage across the terminals of the resistor 46 i is less than the offset voltage V offset .
  • the figure 8 represents a more detailed embodiment of the comparator 48 i and a circuit providing the reference voltage V offset .
  • the comparator 48 i comprises a first differential pair P 1 comprising, for example, two MOS transistors fed by a current I BIAS and which detects the current flowing through the resistor 46 i , not shown in FIG. figure 8 and located between the gates V plus and V minus of the transistors of the pair P 1 .
  • the nodes O 1 and O 2 are connected to the drains of the transistors of the pair P 1 .
  • the comparator 48 i comprises a second differential pair P 2 comprising, for example, two MOS transistors fed by a current I BIAS and which supplies the reference voltage V offset .
  • the nodes O 1 and O 2 are, in addition, connected to the drains of the transistors of the pair P 2 .
  • the reference voltage V offset is proportional to a bias current KI CS , an image of the current I CS supplied by the current source 30, to the resistor R REF crossed by the previous current and to the ratio of the transconductances of the differential pairs.
  • An amplifier output stage connected to the nodes O 1 and O 2 provides a signal at a state "1" or "0" according to the sign of the voltage between the nodes O 1 and O 2 .
  • the current sensor may comprise a current mirror. Only a small fraction of the current flowing through the switch SW i is then diverted to a current comparator.
  • the figure 9 represents another embodiment of the current sensor 36 i in which the current sensor 36 i comprises a resistor 50 i and a diode 52 i connected in series between the node A 3 and the switch SW i , represented in FIG. figure 9 by a MOS transistor, the cathode of the diode 52 i being connected to the resistor 50 i .
  • the current sensor 36 i further comprises a bipolar transistor 54 i whose base is connected to the anode of the diode 52 i whose collector supplies the signal CUR i and whose emitter is connected to the node A 3 by resistance 56 i .
  • the collector of the bipolar transistor 54 i is connected to a terminal of a source of a reference current CREF whose other terminal is connected to the source of the reference potential VREF.
  • the maximum voltages applied to the electronic components, in particular the MOS transistors, the current sensors 36 i and the voltage sensor 38 remain small compared with the maximum value that the voltage V ALIM can take. It is then not necessary to provide, for the current sensors 36 i and the voltage sensor 38, electronic components that can support the maximum value that can take the voltage V ALIM .
  • the operation of the optoelectronic circuit 20 is as follows. At the beginning of an ascending phase of the voltage V ALIM , the switches SW i , i varying from 1 to N-1, are closed, that is to say, electrically conducting. In an ascending phase, for i varying from 1 to N-1, while the global light-emitting diodes D 1 to D i-1 are on and the global light-emitting diodes D i to D N are off, when the voltage at the terminals of the electroluminescent diodes D 1 to D N the global light-emitting diode D i becomes greater than the threshold voltage of the global light-emitting diode D i , the latter becomes conductive and a current begins to flow in the global light-emitting diode D i .
  • the flow of current is detected by the current sensor 36 i .
  • the module 34 then controls the opening of the switch SW i-1 .
  • the switches SW i , i varying from 1 to N-1 are open.
  • the global light-emitting diodes D 1 to D i-1 being conducting and the global light-emitting diodes D i to D N being blocked, when the voltage V CS decreases below a voltage threshold, this means that the voltage across the current source 30 may become too low for it to function properly and deliver its rated current. This means that it is necessary to reduce the number of diodes D i in conduction to increase the voltage at the terminals of the source of current.
  • each switch SW i is formed by an N-channel MOS transistor whose drain is connected to the cathode of the global light-emitting diode D i and whose source is connected to the current sensor 36 i
  • the voltage between the drain of the switch SW i and the node A 2 decreases until the operation of the transistor SW i goes from the saturation regime to the linear regime. This causes an increase in the voltage between the gate and the source of the transistor SW i and therefore a decrease in the voltage V CS .
  • the switch SW i-1 is closed.
  • the embodiment of the switch control method SW i described above does not depend on the number of elementary light-emitting diodes that make up each global light-emitting diode D i and therefore does not depend on the threshold voltage of each global light-emitting diode. .
  • the figure 10 represents timing diagrams of the supply voltage V ALIM , signals S i , i varying from 1 to N-1, currents I i , i varying from 1 to N, current I CS and voltage V CS illustrating the operation of the optoelectronic circuit 20 according to the embodiment shown in FIG. figure 3 in the case where N is equal to 4, in the case where each global light-emitting diode D i comprises the same number of elementary light-emitting diodes arranged in the same configuration, and therefore has the same threshold voltage Vled and in the case where the source current supply 30 provides a constant ICS current.
  • the global light emitting diode D 1 becomes conducting (phase P 1 ) and the voltage across the global light emitting diode D 1 1 then remains substantially constant and equal to Vled.
  • the voltage V CS is high enough to enable activation of the current source 30
  • the current I CS flows in the global light emitting diode D 1 which emits light.
  • the current I CS flows entirely in the branch comprising the switch SW 1 and the current I 1 is equal to I CS .
  • the voltage V CS is preferably substantially constant when the current source 30 is in operation. In figure 10 it has been assumed that the current source 30 is activated before the global light-emitting diode D 1 becomes turned on so that the current I CS flows in the global light-emitting diode D 1 from the instant t 1 .
  • the module 34 controls the opening of the switch SW 1 (signal S1 set to "0").
  • the current I 1 vanishes and the current I 2 increases to I CS .
  • the phase P 2 corresponds to a light emission phase by the global light-emitting diodes D 1 and D 2 .
  • the module 34 command the opening of the switch SW i when the current I i + 1 flowing in the branch containing the switch SW i + 1 exceeds the current threshold.
  • the phase P i + 1 corresponds to the emission of light by the global light-emitting diodes D 1 to D i + 1 .
  • the module 34 controls the opening of the switch SW 2 by setting "0" of the signal S 2 and at time t 4 , the module 34 controls the opening of the SW 3 switch by setting "0" signal S 3 .
  • the supply voltage V ALIM reaches its maximum value during phase P 4 and initiates a downward phase.
  • the module 34 commands the closing of the switch SW 3 by setting to "1 signal S 3 .
  • the current I CS then flows entirely in the branch containing the switch SW 3 .
  • the current I 4 is therefore canceled and the current I 3 goes to I CS .
  • the module 34 controls the closing of the switch SW i-1 .
  • the module 34 controls the closing of the switch SW 2 by setting "1" of the signal S 2 and, at time t 7 , the module 34 controls the closing of the switch SW 1 by setting "1" signal S 1 .
  • the optoelectronic circuit is sized, in particular by a suitable choice of the detection threshold of the comparison module 38 and the properties of the switches S i and sets of light-emitting diodes D i , so that the temporary decrease in the voltage CS V is sufficiently low not to be detected by the comparison module 38.
  • the control module 34 is adapted to ignore a detection of a decrease in the voltage V CS by the comparison module 38 during an increasing phase of the supply voltage V ALIM . This can be achieved by a temporary deactivation of the comparison module 38 during each increasing phase or for a determined duration after each opening of a switch SW i .
  • the current source 30 is a current source controlled by the control module 34 and adapted to supply a current I CS which remains uninterrupted as long as the supply voltage V ALIM is greater than the threshold voltage of the global light emitting diode D 1 .
  • the current source 30 is adapted to supply a variable current at different levels as a function of the number of global electroluminescent diodes that are on.
  • the figure 11 represents an embodiment of the current source 30 in which the current source 30 comprises M controllable elementary current sources CS 1 to CS M where M is an integer ranging from 1 to N. Preferably, M is equal to N.
  • the elementary current sources CS j , j varying from 1 to M are connected in parallel between the node A 3 and the node A 2 .
  • Each elementary current source CS j is activated or deactivated by the control module 34 by a control signal C j .
  • the signal C j is a binary signal and the elementary current source CS j is extinguished when the signal C j is in a first state, for example the low state, and the current source CS j is activated when the signal C j is in a second state, for example the high state.
  • the signal C 1 may not be present and the current source CS 1 may be activated automatically, i.e. it provides a current as soon as it is supplied with sufficient voltage.
  • the current source 30 is adapted to supply a current I CS having an intensity at one of several constant levels and the level of which depends on the number of global light emitting diodes that are on.
  • the currents provided by the elementary current sources CS j of the current source 30 may be the same or different.
  • each elementary current source CS j is adapted to supply a current of intensity I * 2 j-1 .
  • the current source 30 is then adapted to provide a current I CS whose intensity can, depending on the control signals C j , take any value k * I, k varying from 0 to 2 M -1.
  • the activation sequence of the current sources CS j during the evolution of the voltage V ALIM depends in particular on the operating properties of the optoelectronic circuit that is to be preferred.
  • the figure 12A illustrates an embodiment of the current source activation sequence which makes it possible to increase the power factor of the optoelectronic circuit with respect to the case where the current is constant.
  • the figure 12A represents curves of evolution of the signals S 1 , S 2 and S 3 , evolution curves of the signals C 1 , C 2 , C 3 and C 4 , and of the current I CS when the optoelectronic circuit 20 comprises four light-emitting diodes and four elementary current sources CS j in parallel, during a cycle of the voltage V ALIM in the case where the voltage V IN is a sinusoidal voltage.
  • the control of the signals S 1 , S 2 and S 3 is identical to that described above in connection with the figure 10 and I 1 , I 2 , I 3 and I 4 are increasing intensity values of the current I CS .
  • the signals S i , i varying from 1 to N-1 are initially at “1” so that the switches SW i are on.
  • the signal C 1 is at "1” so that the current source CS 1 is activated.
  • the global light-emitting diode D 1 becomes conducting and is traversed by the current I CS whose intensity is equal to I 1 .
  • the switches SW 1 , SW 2 and SW 3 are successively open at times t 1 , t 2 and t 3 as the voltage V ALIM is raised so that the global light-emitting diodes D 2 , D 3 and D 4 are successively supplied with current.
  • the current sources CS 2 , CS 3 and CS 4 are activated successively at times t 2 , t 3 and t 4 as the voltage V ALIM is raised so that the current intensity of supply I CS is successively equal to I 2 , I 3 and I 4 .
  • the switches SW 3 , SW 2 and SW 1 are closed successively at times t 5 , t 6 and t 7 in order to successively short-circuit the global light-emitting diodes D 4 , D 3 and D 2 .
  • the current sources CS 4 , CS 3 and CS 2 are successively deactivated at times t 5 , t 6 and t 7 so that the current intensity I CS feed is successively equal to I 3 , I 2 and I 1 .
  • the current I CS is canceled.
  • the current sources are activated so that the supply current I CS best follows the general shape of a sinusoid, that is to say the shape of the voltage V ALIM in phase. with this one.
  • the power factor of the optoelectronic circuit is then increased.
  • the figure 12B is analogous to the figure 12A and illustrates an embodiment of a current source activation sequence that reduces flicker perceived by an observer.
  • the curves of the figure 12B were obtained with the optoelectronic circuit used to obtain the curves of the figure 12A with the difference that the activation sequence of the current sources is modified. Indeed, the signals C 1 and C 2 are initially at "1" and the signals C 3 and C 4 are initially at "0" so that the current sources CS 1 and CS 2 are activated and that, at the instant t 1 , the intensity of the current I CS passing through the global light emitting diode D 1 is equal to I 2 .
  • the signal C 3 is set to "1" so that the intensity of the current I CS passing through the global light emitting diodes D 1 and D 2 is equal to I 3 .
  • the signal C 3 is set to "0" so that the intensity of the current I CS passing through the global light emitting diodes D 1 , D 2 and D 3 is equal to I 2 .
  • the signal C 2 is set to "0" so that the intensity of the current I CS passing through the global light-emitting diodes D 1 , D 2 , D 3 and D 4 is equal to I 1 .
  • a symmetrical activation sequence is performed at times t 5 , t 6 , t 7 and t 8 .
  • the intensity of the current is controlled so that the emission light power of the optoelectronic circuit is close to the average light output emitted on an alternation of the voltage V ALIM .
  • the variations in the luminous power perceived by the observer are then reduced.
  • the values of the control signals C j can be stored in a memory of the control module 34 for each switching configuration of the switches.
  • the control of the current source 30 by the control module 34 can be modified during the operation of the optoelectronic circuit, for example according to whether it is desirable to increase the power factor of the optoelectronic circuit. or reduce flicker perceived by an observer.
  • the current source 30 comprises elementary current sources CS j
  • the optoelectronic circuit may be implemented in the form of an integrated circuit comprising a dedicated pin to which a control signal of the control module 34 representative of the desired control of the current source 30 is applied.
  • the control module 34 comprises a memory programmable by a user and in which are stored data used by the control module 34 for the desired control of the current source 30 by the control module 34.
  • the figure 13 represents a circuit diagram of another embodiment of the current source 30.
  • the current source 30 comprises the transistors 42 and 44 forming the current mirror described above in connection with the present invention. figure 6 .
  • the current source 30 further comprises the current sources CS 1 to CS M which are connected in parallel between a source of the reference potential VREF and the drain of the transistor 42.
  • the figure 14 represents a circuit diagram of another embodiment of the current source 30 in which the current source 30 comprises the same elements as the embodiment shown in FIG. figure 13 and in which each source current CS j , j varying from 1 to M, comprises a resistor 60 j connected in series with a MOS transistor 62 j , for example P-channel, between the source of the reference potential VREF and the drain of the transistor 42.
  • the grid of each transistor 62 j receives the control signal C j .
  • each transistor 62 j is located on the side of the transistor 42 while each resistor 60 j is located on the side of the source of the reference potential VREF.
  • the figure 15 represents a circuit diagram of another embodiment of the current source 30 in which the current source 30 comprises the same elements as the embodiment shown in FIG. figure 11 and wherein each current source CS j , j varying from 1 to M, comprises a resistor 64 j connected in series with a MOS transistor 66 j , for example N-channel, between the node A 3 and the node A 2 .
  • the gate of each transistor 66 j receives the control signal C j .
  • Each transistor 66 j is preferably located on the side of the node A 3 while each resistor 64 j is preferably located on the side of the node A 2 .
  • the figure 16 represents a circuit diagram of another embodiment of the current source 30 in which the current source 30 comprises a MOS transistor 68, for example N-channel, whose drain is connected to the node A 3 and whose source is connected to a terminal of a resistor 70, the other terminal of the resistor 70 being connected to the node A 2 .
  • the current source 30 comprises an operational amplifier 72 whose non-inverting input (+) is connected to a terminal of a voltage source 74 controllable by the control module 34 and whose inverting input (-) is connected to the midpoint between the transistor 68 and the resistor 70.
  • the other terminal of the voltage source 74 is connected to the node A 2 .
  • the output of the operational amplifier 72 is connected to the gate of the transistor 68.
  • the figure 17 represents a circuit diagram of another embodiment of the current source 30 in which the current source 30 comprises a current source 76 having a terminal connected to the source of the reference potential VREF.
  • the other terminal of the current source 76 is connected to the drain of a transistor 78 MOS, for example N-channel, diode-mounted.
  • the source of the MOS transistor 78 is connected to the node A 2 .
  • the gate of the MOS transistor 78 is connected to the drain of the MOS transistor 78.
  • the current source 30 further comprises M MOS transistors 80 j , j varying from 1 to M, for example to an N channel.
  • the source of each transistor 80 j is connected to the node A 2 .
  • the drain of each transistor 80 j is connected to the node A 3 .
  • each transistor 80 j is connected to the gate of transistor 78 via a switch 82 j .
  • Each switch 82 j is controlled by the control signal C j provided by the control module 34. Alternatively, the switch 82 1 may not be present.
  • Each transistor 80 j forms with the transistor 78 a current mirror. The intensity of the current I CS depends on the number of switches 82 j which are closed. According to one embodiment, each transistor 80 j is identical to the transistor 78. When the switch 82 j is closed, the transistor 80 j is traversed by a current having the same intensity as the current supplied by the current source 76 and is equivalent at the elementary current source CS j .
  • the dimensions of the transistors 80 j may be different from those of the transistor 78 and may be different between the transistors 80 j so that the intensity of the current flowing through each transistor 80 j , when the switch 82 j associated is closed, is different from the intensity of the current supplied by the current source 76.
  • the intensity of the current flowing through each transistor 80 j when the associated switch 82 j is closed, is equal to produces a different power of two and a reference intensity.
  • the Figures 18 and 19 represent evolution curves, obtained by simulation during a cycle of the voltage V ALIM in the case where the voltage V IN is a sinusoidal voltage, of the supply voltage V ALIM , of the current I CS and of a voltage V LED equal to the sum of the voltages at the terminals of the global electroluminescent diodes which are conducting, when the optoelectronic circuit 20 comprises eight diodes electroluminescent devices and eight elementary current sources CS j in parallel. Each elementary current source CS j is adapted to provide a constant current of the same intensity.
  • the figure 18 was obtained with an activation sequence of the elementary current sources of the current source 30 similar to that described above in connection with the figure 12A .
  • the average active power consumed by the optoelectronic circuit is 10.55 W, the power factor is 0.99 and the flicker index FI is substantially equal to 33.
  • the power factor is substantially equal to 1.
  • the optoelectronic circuit satisfies, in addition, the constraints concerning the harmonic currents provided for class D and class C lighting equipment by the NF EN 61000-3-2 standard, November 2014 version, on electromagnetic compatibility .
  • the figure 19 was obtained for an activation sequence of the elementary current sources of the current source 30 similar to that described above in connection with the figure 12B .
  • the average active power consumed by the optoelectronic circuit is 10.58 W, the power factor is 0.89 and the flicker index F1 is substantially equal to 22.
  • the flicker index is reduced compared to the illustrated case. on the figure 18 .
  • the optoelectronic circuit furthermore satisfies the constraints concerning the harmonic currents provided for class D lighting equipment, that is to say receiving an active power of less than 25 W, by the standard NF EN 61000-3-2, version of November 2014, on electromagnetic compatibility.
  • the optoelectronic circuit is adapted to receive a modulation signal external to the optoelectronic circuit and the current source 30 can modify the intensity values of the current I CS as a function of the modulation signal.
  • the optoelectronic circuit may comprise a terminal dedicated to the reception of the modulation signal.
  • the modulation signal may be received by the control module 34 which accordingly controls the current source 30.
  • the modulation signal may correspond to a voltage.
  • the current source 30 is adapted to modulate each intensity value between 0% and 100% depending on the modulation signal.
  • the modulation signal can be provided by a drive, in particular a drive that can be actuated by a user.
  • the modulation of intensity values can be static, dynamic and digital, or dynamic and analog.
  • the modulation signal can be provided by a brightness sensor and the control module 34 can control the current source 30 to modulate the current intensity values, for example to take account of variations in the ambient luminosity and / or variations of the light emitted by the global light-emitting diodes as a function of the temperature.
  • the modulation due to the modulation signal takes precedence and the modulation rate is the same for each intensity value of the current I CS supplied by the current source 30.
  • each embodiment of the current source 30 previously described in connection with the Figures 13 to 17 can be used for the implementation of the embodiments of the control methods of the current source described above in relation to the Figures 12A and 12B .

Landscapes

  • Circuit Arrangement For Electric Light Sources In General (AREA)
  • Led Devices (AREA)

Claims (16)

  1. Optoelektronische Schaltung (20) zum Empfangen einer variablen Spannung (VALIM), die abwechselnde ansteigende und abfallende Phasen enthält, wobei die optoelektronische Schaltung Folgendes aufweist:
    eine Vielzahl von Anordnungen (Di) von lichtemittierenden Dioden, wobei die Anordnungen in Reihe geschaltet sind;
    eine Stromquelle (30), die mit jeder Anordnung (Di) aus mindestens bestimmten Anordnungen der Vielzahl von Anordnungen durch einen Schalter (SWi) verbunden ist, dadurch gekennzeichnet, dass die optoelektronische Schaltung Folgendes aufweist:
    für jeden Schalter eine erste Vergleichseinheit (36i), die geeignet ist, den durch den Schalter fließenden Strom (Ii) mit einem Stromschwellenwert zu vergleichen;
    eine zweite Einheit (38) zum Vergleichen einer Spannung, welche die Spannung (Vcs) über die Stromquelle darstellt, mit einem Spannungsschwellenwert; und
    eine Steuereinheit (34), die mit der ersten und zweiten Vergleichseinheit verbunden ist, und die geeignet ist, während jeder ansteigenden Phase und jeder abfallenden Phase die Schalter in den Aus-Zustand und in den Ein-Zustand zu steuern, und zwar gemäß den von der ersten und zweiten Vergleichseinheit gelieferten Signalen.
  2. Optoelektronische Schaltung nach Anspruch 1, wobei die Steuereinheit (34) geeignet ist, während jeder ansteigenden Phase für jeden Schalter den Schalter in den Aus-Zustand zu steuern, wenn der durch den benachbarten Schalter im Ein-Zustand fließende Strom über den Stromschwellenwert ansteigt, und während jeder abfallenden Phase für jeden ausgeschalteten Schalter, der benachbart zu einem Schalter im Ein-Zustand ist, den Schalter in den Ein-Zustand zu steuern, wenn die Spannung unter den Spannungsschwellenwert fällt.
  3. Optoelektronische Schaltung nach Anspruch 1 oder 2, wobei die Stromquelle (30) geeignet ist, einen Strom (Ics) zu liefern, dessen Intensität von mindestens einem Steuersignal (Cj) abhängt.
  4. Optoelektronische Schaltung nach Anspruch 3, wobei die Stromquelle (30) geeignet ist, einen Strom zu liefern dessen Intensität zwischen einer Vielzahl von verschiedenen Intensitätswerten variiert, und zwar gemäß der Anzahl von Anordnungen, die den Strom während mindestens einer ansteigenden Phase oder einer abfallenden Phase leiten.
  5. Optoelektronische Schaltung nach Anspruch 4, wobei die optoelektronische Schaltung geeignet ist, ein Modulationssignal von außerhalb der optoelektronischen Schaltung zu empfangen und die Stromquelle (30) in der Lage ist, die Intensitätswerte gemäß dem Modulationssignal zu modifizieren.
  6. Optoelektronische Schaltung nach einem der Ansprüche 1 bis 5, wobei die Stromquelle (30) elementare Stromquellen (CSj) aufweist, die parallel angeordnet sind und unabhängig voneinander aktiviert und deaktiviert werden können.
  7. Optoelektronische Schaltung nach Anspruch 6, wobei die elementaren Stromquellen (CSj) geeignet sind, Ströme mit gleicher Intensität oder mit unterschiedlichen Intensitäten zu liefern.
  8. Optoelektronische Schaltung nach Anspruch 6 oder 7, wobei die Steuereinheit (34) in der Lage ist, mindestens eine der elementaren Stromquellen während mindestens einer ansteigenden Phase zu aktivieren und mindestens eine der elementaren Stromquellen während mindestens einer abfallenden Phase zu deaktivieren.
  9. Optoelektronische Schaltung nach einem der Ansprüche 6 bis 8, wobei eine der elementaren Stromquellen (CSj) geeignet ist, einen Strom mit einer gegebenen Intensität zu liefern, und die anderen elementaren Stromquellen geeignet sind, jeweils einen Strom mit einer Intensität zu liefern, die dem Produkt aus einer Zweierpotenz und der gegebenen Intensität entspricht.
  10. Optoelektronische Schaltung nach einem der Ansprüche 6 bis 9, wobei die Steuereinheit (34) geeignet ist, die Schalter (SWi) zu steuern, um die Anordnungen (Di) von lichtemittierenden Dioden gemäß einer Vielzahl von Anschlusskonfigurationen nacheinander gemäß einer ersten Ordnung während jeder ansteigenden Phase der variablen Spannung (VALIM) und einer zweiten Ordnung während jeder abfallenden Phase der variablen Spannung zu verbinden, und die geeignet ist, die elementaren Stromquellen (CSj) gemäß einer dritten Ordnung während jeder ansteigenden Phase der variablen Spannung zu aktivieren und die elementaren Stromquellen gemäß einer vierten Ordnung während jeder abfallenden Phase der variablen Spannung zu deaktivieren.
  11. Optoelektronische Schaltung nach einem der Ansprüche 4 bis 10, aufweisend einen Speicher mit einer Vielzahl von darin gespeicherten Werten des Steuersignals der Stromquelle (30), die jeweils der Bereitstellung des Stroms durch die Stromquelle (30) entsprechen, dessen Intensität innerhalb der Vielzahl von Intensitätswerten variiert.
  12. Optoelektronische Schaltung nach einem der Ansprüche 4 bis 11, aufweisend Mittel zum Modifizieren des Variationsprofils der Intensität des Stroms gemäß der Anzahl der Anordnungen, die den Strom während mindestens einer ansteigenden Phase oder abfallenden Phase leiten.
  13. Verfahren zum Steuern einer Vielzahl von Anordnungen (Di) von lichtemittierenden Dioden, wobei die Anordnungen in Reihe geschaltet und mit einer variablen Spannung (VALIM) gespeist werden, die einen Wechsel von ansteigenden Phasen und abfallenden Phasen enthält, wobei jede Anordnung (Di) unter mindestens bestimmten Anordnungen aus der Vielzahl von Anordnungen durch einen Schalter (SWi) mit einer Stromquelle (30) verbunden ist, dadurch gekennzeichnet, dass das Verfahren die folgenden Schritte aufweist:
    für jeden Schalter, Durchführen eines ersten Vergleichs des durch den Schalter fließenden Stroms (Ii) mit einem Stromschwellenwert;
    Durchführen eines zweiten Vergleichs einer Spannung, die die Spannung (Vcs) über der Stromquelle darstellt, mit einem Spannungsschwellenwert; und
    Steuern der Schalter in den Aus-Zustand und in den Ein-Zustand während jeder ansteigenden Phase und jeder abfallenden Phase, und zwar gemäß den ersten und zweiten Vergleichen.
  14. Verfahren nach Anspruch 13, das ferner den folgenden Schritt aufweist:
    während jeder ansteigenden Phase für jeden Schalter, Ausschalten des Schalters, wenn der durch den benachbarten Schalter im eingeschalteten Zustand fließende Strom über den Stromschwellenwert ansteigt, und während jeder abfallenden Phase für jeden ausgeschalteten Schalter, der benachbart zu einem Schalter im eingeschalteten Zustand ist, Einschalten des Schalters, wenn die Spannung über den Spannungsschwellenwert ansteigt.
  15. Verfahren nach Anspruch 13 oder 14, wobei die Stromquelle (30) mindestens zwei parallel angeordnete elementare Stromquellen (CSj) aufweist und wobei mindestens eine der elementaren Stromquellen während mindestens einer ansteigenden Phase aktiviert wird und mindestens eine der elementaren Stromquellen während mindestens einer abfallenden Phase deaktiviert wird.
  16. Verfahren nach Anspruch 15, wobei die Stromquelle (30) mindestens drei parallel angeordnete elementare Stromquellen (CSj) aufweist, wobei für mindestens aufeinanderfolgende ansteigende Phasen und abfallende Phasen die Anzahl der aktivierten elementaren Stromquellen vom Beginn bis zum Ende der ansteigenden Phase ansteigt und die Anzahl der aktivierten elementaren Stromquellen vom Beginn bis zum Ende der abfallenden Phase abnimmt oder wobei die Anzahl der aktivierten elementaren Stromquellen vom Beginn bis zum Ende der ansteigenden Phase ansteigt und dann abnimmt und die Anzahl der aktivierten elementaren Stromquellen vom Beginn bis zum Ende der abfallenden Phase ansteigt und dann abnimmt.
EP16750976.9A 2015-08-03 2016-07-19 Optoelektronische schaltung mit leuchtdioden Active EP3332608B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1557480A FR3039943B1 (fr) 2015-08-03 2015-08-03 Circuit optoelectronique a diodes electroluminescentes
PCT/FR2016/051843 WO2017021610A1 (fr) 2015-08-03 2016-07-19 Circuit optoelectronique a diodes electroluminescentes

Publications (2)

Publication Number Publication Date
EP3332608A1 EP3332608A1 (de) 2018-06-13
EP3332608B1 true EP3332608B1 (de) 2019-02-13

Family

ID=54608726

Family Applications (1)

Application Number Title Priority Date Filing Date
EP16750976.9A Active EP3332608B1 (de) 2015-08-03 2016-07-19 Optoelektronische schaltung mit leuchtdioden

Country Status (6)

Country Link
US (1) US10264633B2 (de)
EP (1) EP3332608B1 (de)
KR (1) KR20180033241A (de)
CN (1) CN108029172B (de)
FR (1) FR3039943B1 (de)
WO (1) WO2017021610A1 (de)

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2393929C2 (ru) * 2005-03-15 2010-07-10 Прк Десото Интернэшнл, Инк. Устройство и способ для удаления краски и герметика
US7880400B2 (en) * 2007-09-21 2011-02-01 Exclara, Inc. Digital driver apparatus, method and system for solid state lighting
US9118847B2 (en) * 2009-03-24 2015-08-25 Nec Display Solutions, Ltd. Dustproof structure of image generation device, and projection display device
US8569956B2 (en) * 2009-06-04 2013-10-29 Point Somee Limited Liability Company Apparatus, method and system for providing AC line power to lighting devices
KR101272033B1 (ko) * 2011-10-27 2013-06-07 주식회사 실리콘웍스 Ｌｅｄ구동장치
WO2013191806A1 (en) * 2012-06-21 2013-12-27 Altoran Chip & Systems Inc. Light emitting diode driver
KR101267278B1 (ko) * 2012-11-22 2013-05-27 이동원 변조지수가 개선된 엘이디 조명장치
KR101503874B1 (ko) * 2013-09-25 2015-03-19 매그나칩 반도체 유한회사 발광 다이오드 구동 회로 및 이를 포함하는 조명 장치
EP2894944A1 (de) * 2014-01-14 2015-07-15 Dialog Semiconductor GmbH Verfahren zur Verbesserung der Genauigkeit eines Exponentialstrom-Digital-Analog-Wandlers (IDAC) mithilfe binär gewichteter MSB
US9544485B2 (en) * 2015-05-27 2017-01-10 Google Inc. Multi-mode LED illumination system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
None *

Also Published As

Publication number Publication date
FR3039943B1 (fr) 2017-09-01
US10264633B2 (en) 2019-04-16
CN108029172A (zh) 2018-05-11
US20180227992A1 (en) 2018-08-09
WO2017021610A1 (fr) 2017-02-09
CN108029172B (zh) 2019-10-01
EP3332608A1 (de) 2018-06-13
FR3039943A1 (fr) 2017-02-10
KR20180033241A (ko) 2018-04-02

Similar Documents

Publication Publication Date Title
FR3055505A1 (fr) Circuit d'eclairage et phare de vehicule
FR3013937A1 (fr) Circuit d'attaque avec une source lumineuse a base de semi-conducteurs, ainsi que procede de fonctionnement d'un circuit d'attaque
EP0695112B1 (de) Lumineszenzdiodenvorrichtung
EP3332608B1 (de) Optoelektronische schaltung mit leuchtdioden
FR3023119B1 (fr) Circuit optoelectronique a diodes electroluminescentes
EP3223590B1 (de) Optoelektronischer schaltkreis, der elektrolumineszenzdioden umfasst
EP3241408A1 (de) Optoelektronische schaltung mit leuchtdioden
EP3302003B1 (de) Optoelektronischer schaltkreis, der elektrolumineszenzdioden umfasst
EP3108719A1 (de) Optoelektronische schaltung mit leuchtdioden
EP3223589B1 (de) Optoelektronischer schaltkreis, der elektrolumineszenzdioden umfasst
EP3332607A1 (de) Optoelektronische schaltung mit leuchtdioden
WO2017162982A1 (fr) Circuit optoelectronique comprenant des diodes electroluminescentes
FR3060934A1 (fr) Circuit optoelectronique comprenant des diodes electroluminescentes
WO2017060657A1 (fr) Circuit optoelectronique a diodes electroluminescentes
WO2017060658A1 (fr) Circuit optoelectronique a diodes electroluminescentes
EP3398408B1 (de) Optoelektronische schaltung mit leuchtdioden
CA2869170C (fr) Generateur de courant et procede de generation d'impulsions de courant
FR3023671B1 (fr) Procede d’alimentation et systeme d’eclairage
EP3403471A1 (de) Verfahren zur steuerung eines arbeitspunktes eines satzes elektronischer komponenten
FR3046493A1 (fr) Circuit optoelectronique a diodes electroluminescentes
FR2924298A1 (fr) Reglage des leds blanches

Legal Events

Date Code Title Description
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE

PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20180208

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

DAV Request for validation of the european patent (deleted)
DAX Request for extension of the european patent (deleted)
GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: GRANT OF PATENT IS INTENDED

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

INTG Intention to grant announced

Effective date: 20181204

RIN1 Information on inventor provided before grant (corrected)

Inventor name: MERCIER, FREDERIC

Inventor name: JOUBERT, NICOLAS

Inventor name: GRAS, DAVID

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE PATENT HAS BEEN GRANTED

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

Free format text: NOT ENGLISH

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

Ref country code: AT

Ref legal event code: REF

Ref document number: 1096982

Country of ref document: AT

Kind code of ref document: T

Effective date: 20190215

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

Free format text: LANGUAGE OF EP DOCUMENT: FRENCH

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602016009963

Country of ref document: DE

REG Reference to a national code

Ref country code: LT

Ref legal event code: MG4D

REG Reference to a national code

Ref country code: NL

Ref legal event code: MP

Effective date: 20190213

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190613

Ref country code: NO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190513

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190213

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190213

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190213

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190213

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190514

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190513

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190613

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190213

Ref country code: HR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190213

Ref country code: RS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190213

REG Reference to a national code

Ref country code: AT

Ref legal event code: MK05

Ref document number: 1096982

Country of ref document: AT

Kind code of ref document: T

Effective date: 20190213

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190213

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190213

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190213

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190213

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190213

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190213

Ref country code: AL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190213

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602016009963

Country of ref document: DE

REG Reference to a national code

Ref country code: DE

Ref legal event code: R079

Ref document number: 602016009963

Country of ref document: DE

Free format text: PREVIOUS MAIN CLASS: H05B0033080000

Ipc: H05B0045000000

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SM

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190213

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190213

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190213

26N No opposition filed

Effective date: 20191114

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190213

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190213

REG Reference to a national code

Ref country code: BE

Ref legal event code: MM

Effective date: 20190731

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20190731

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20190731

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20190719

Ref country code: BE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20190731

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20190719

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190213

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190213

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO

Effective date: 20160719

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190213

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: IT

Payment date: 20210713

Year of fee payment: 6

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190213

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20220719

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20230721

Year of fee payment: 8

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20230726

Year of fee payment: 8

Ref country code: DE

Payment date: 20230719

Year of fee payment: 8