EP3182249B1 - Power-domain optimization - Google Patents
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- EP3182249B1 EP3182249B1 EP16204356.6A EP16204356A EP3182249B1 EP 3182249 B1 EP3182249 B1 EP 3182249B1 EP 16204356 A EP16204356 A EP 16204356A EP 3182249 B1 EP3182249 B1 EP 3182249B1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
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- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3058—Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
- G06F11/3062—Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations where the monitored property is the power consumption
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/06—Power analysis or power optimisation
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/12—Timing analysis or timing optimisation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- the present specification relates to systems, methods, apparatuses, devices, articles of manufacture and instructions for power management.
- Circuit designs can often be partitioned into multiple power-domains. Depending upon the partitioning, either flat power-domains having multiple supply voltages (MSV) or stacked power-domains employing charge recycling can be created.
- MSV supply voltages
- stacked power-domains employing charge recycling can be created.
- Partitioning and assigning voltages to each of these power-domains however can be a complex, costly and time consuming process, requiring extensive infrastructure support.
- Power consumption of such partitioned circuits is often not optimal and can drain batteries and/or unnecessarily increase electrical consumption.
- US7551985 describes a method and apparatus for power optimization for integrated circuits, where the circuit is comprised of several different power domains.
- US20120054511 describes an integrated circuit that has a power manager for controlling power consumption within different domains.
- US2007011643 describes a circuit design method that uses multiple cell libraries.
- optimal partitioning of the power-domains i.e. positioning of the inter-domain signal level-shifters, and optimal assignment of nominal power-domain voltages is performed.
- the controller is an adaptive-relative-voltage-frequency-scaling (ARVFS) controller.
- ARVFS adaptive-relative-voltage-frequency-scaling
- the operational phase optimization techniques are embedded in hardware, while in another example embodiment these techniques are implemented using computerized software.
- Dynamic Voltage and Frequency Scaling (DVFS) techniques may be used in other example embodiments.
- Figure 1 is one example dataflow and timing diagram 100 of a critical path delay 102 (i.e. Tcritical) in a circuit design with or without power-domain partitioning.
- Tcritical critical path delay
- the speed of a digital circuit design is characterized by its register-to-register delay (i.e. critical path delay 102).
- Tcritical 102 is determined by the speed at which data can be transferred between two registers/flip-flops 104 and 106.
- Tcritical is increased by combinational logic 108 between the registers/flip-flops 104, 106.
- FIG 2 is one example dataflow and timing diagram 200 of a critical path delay 202 (i.e. Tcritical) in a multiple supply voltage (MSV) partitioned power-domain design (also called flat design from here onwards in this document).
- Tcritical path crosses two power domains (e.g. power-domain A 204 and power-domain B 206).
- Each power-domain has its own voltage rails (i.e. VDDA 208 and VDDB 210).
- Tcritical TA + TB
- T A and T B are timing delays contribution of critical timing path in each power-domain A and B respectively.
- power consumption optimization is based on the total current consumed by the power-domain A and power-domain A (i.e. IA + IB).
- Figure 3 is one example dataflow and timing diagram 300 of a critical path delay 302 in a stack partitioned power-domain design.
- the current consumed from the power supply is the maximum current of either power-domain (i.e. MAX of either Itop or Ibottom or MAX of either IA or IB).
- power-domain top 304" is the same as “power-domain A” and “power-domain bottom 306" is the same as “power-domain B”.
- Voltage VDD-top 308 is assigned to power-domain top 304 and voltage VDD-bottom 310 is assigned to power-domain bottom 306.
- a set of level-shifters 312 interface signals transiting between the top and bottom power-domains.
- one example of power consumption optimization is based on minimizing the maximum value of Itop and Ibottom.
- Figure 4 is a first example set of instructions for enabling power-domain optimization.
- Tcritical and Itotal are minimized for either a flat or stacked power-domain design using nominal voltage scaling.
- the circuit is partitioned into a set of power-domains. This is part of the design phase (i.e. the design exploration phase), whereby an initial set of locations for the voltage level-shifters (LS) is chosen.
- the design phase i.e. the design exploration phase
- LS voltage level-shifters
- the level-shifters are located at the boundary of specific IP-blocks and/or subsystems, (e.g. at a boundary between a high speed subsystem and a low speed subsystem).
- the boundaries can be located between a memory subsystem, which operates at a lower voltage, and a CPU or other logic subsystem which operates at a higher voltage or vice-versa (Generally, memory is at higher voltage than logic/CPU, since memory voltages do not scale as much as logic voltages).
- a technique for minimizing timing and current overhead associated with such level-shifters is by minimizing the number of level-shifter-cells.
- an initial set of nominal power supply voltages for the set of power-domains is selected.
- a circuit profiler e.g. circuit logic, a microcontroller or a computer computes Tcritical, Itotal, IA (power-domain A current) and IB (power-domain B current) are computed.
- this computation is done using a set of infrastructure components (e.g. libraries containing timing and power information).
- infrastructure components e.g. libraries containing timing and power information.
- the financial costs for generation and supporting such infrastructure components are significant and certain support teams and additional tools are required.
- the infrastructure components supported may be limited to only a few power-domain voltages (e.g. VDDA and VDDB), and circuit design closure may require additional manual input from a design team.
- the computation described in 406 is performed using this different set of nominal power supply voltages. These newer (i.e. instruction 410) set of computations are then compared with the prior (i.e. instruction 406) set of computations.
- a final set of nominal power supply voltages are assigned to the set of power-domains.
- Figure 5 is a second example list of instructions for enabling power-domain optimization.
- Tcritical and Itotal are minimized for either a flat or stacked power-domain design using variable partitioning (i.e. changing locations of one or more signal level-shifters) and nominal voltage scaling.
- Instructions 502, 504, 506, 508 and 510 are similar to instructions 402, 404, 406, 408 and 410 discussed earlier.
- level-shifters are logically moved using EDA design tools to such other location and instructions 504, 506, 508 and 510 are repeated.
- the set of level-shifter positions corresponding to either a lowest total circuit power consumption, a lowest Tcritical, or some combination of both is selected.
- a final set of nominal power supply voltages are assigned to the set of power-domains corresponding to the selected set of level-shifter positions.
- Example instances of this design methodology also rely on the infrastructure components limitations mentioned earlier and are subject to similar limitations. Also, in some examples, this design methodology may only optimize the power consumption within individual power-domains instead of for the entire circuit. For example, in some instances these techniques will either scale the voltage of all power-domains equally or scale only one of the power-domains.
- Figure 6 is a third example list of instructions for enabling power-domain optimization.
- Tcritical and Itotal are minimized for either a flat or a stacked power-domain design using variable partitioning and both nominal and real-time voltage scaling.
- these algorithms can be applied both during both the design phase as well as during the real-time dynamic operational phase.
- Eqns. 6 and 7 are used to represent delay and current consumption in a digital system.
- Delay T K ⁇ VDD / VDD ⁇ Vth ⁇
- Vth is threshold voltage
- K is a proportionality constant
- ' ⁇ ' is velocity saturation index (1 ⁇ 2).
- Dynamic power (e.g. switching power ) is a power dissipated while charging and discharging the capacitive load at the outputs of each CMOS logic cell whenever a transition occurs.
- 'a' is the average number of output transitions in each clock period. It is usually less than 1, and so is often also defined as the probability of an output transition in a clock period; f is the clock frequency; C is the load capacitance. This can be extended for SOC where, 'a' is related with the average switching activity; C is total intrinsic capacitance of digital (switching part e.g. CPU). Eqn. 7 can be derived by dividing the power dissipation with voltage and merge 1 ⁇ 2 also into 'a'.
- Tcritical m 1 ⁇ VDDA / VDDA ⁇ Vth ⁇ + m 2 ⁇ VDDB / VDDB ⁇ Vth ⁇
- m1 TA ⁇ VDDA ⁇ Vth ⁇ / VDDA
- m 2 TB ⁇ VDDB ⁇ Vth ⁇ / VDDB
- k1, k2 are proportionality constants based on the circuit design and an assumption that each power-domain will operate at fixed frequency.
- k 1 IA / VDDA
- k 2 IB / VDDB
- Eqns. 8 and 11 are used to optimize overall system performance, during either the design phase or the real-time operational phase, and use fewer computational resources and fewer or none of the infrastructure components than the approach described in Figures 4 and 5 .
- the circuit is partitioned into an initial set of power-domains. This is part of the design phase.
- an initial set of nominal power supply voltages for the set of power-domains is selected by a circuit controller (e.g. circuit logic, a microcontroller or a computer).
- a circuit controller e.g. circuit logic, a microcontroller or a computer.
- a circuit profiler e.g. circuit logic, a microcontroller or a computer estimates or computes values for the operating parameters Tcritical, Itotal, IA (first power-domain (e.g. A) current) and IB (second power-domain (e.g. B) current).
- Tcritical TA + TB, where TA is the delay time for the first power-domain and TB is the delay time for the second power-domain.
- the operating parameter values are computed as discussed instruction 406 of Figure 4 .
- the estimate may require inserting few different VDDs to create linear equations. If the available infrastructure (like timing libraries not available then another alternative is to just compute (simulation of critical path or refer to design timing reports generated by the EDA tools.
- the values of at least one of the operating parameter are incrementally swept over a range of voltages (e.g. 0V up to the first power-domain's maximum operational voltage) using the circuit controller.
- operational parameter values for TA, TB, Tcritical, IA, IB, Itotal, and VDDB are derived using the circuit profiler. Note, during the design phase these parameter values are computed using Eqns. 8 through 13 using simulated versions of both power-domains. However during the operational phase these parameter values are derived in real-time using Eqns. 8 through 13 using actual measured signal values from both power-domain's actual hardware circuits.
- each set of operational parameter values are then compared with the prior set of operational parameter values. Iterations between instructions 608 and 612 are performed until the circuit is optimized by either minimizing total circuit power consumption (i.e. Itotal), minimizing Tcritical, or minimizing some combination of both.
- Tcritical, Itotal, IA and IB are validated so that the loop does not iterate infinitely. However in example embodiments, iteration is continued if the resulting power consumption is less than the previous one. When power consumption starts increasing, a few (e.g. three) more iterations can be performed to filter out the effect of noise, and ensure that the minima is reached in a reliable manner.
- the EDA design software checks whether there is another possible set of level-shifter (LS) locations.
- LS level-shifter
- level-shifters are logically moved using EDA design tools to such other location and instructions 604, 606, 608, 610 and 612 are repeated.
- a final set of nominal power supply voltages are assigned to the set of power-domains corresponding to the selected set of level-shifter positions by the circuit controller.
- Figures 7A, 7B and 7C show a first example set of EDA design simulation results for flat and stacked power-domain circuits.
- VDDA0 Power-Domain-A's voltage
- Figure 7A shows an example graph of the effect of a VDDA voltage sweep on both power-domain's timing delay (i.e. TA, TB).
- Figure 7B shows an example graph of the effect of a VDDA voltage sweep on power-domain B's voltage (VDDB).
- Figure 7C shows an example graph of the effect of a VDDA voltage sweep on the current consumption (Itotal) for both a flat and stacked set of power-domains.
- Itotal current consumption
- Figure 7C clear minimums in the total current consumption curves, for a given Ttotal, are visible.
- Figures 8A, 8B and 8C show a second example set of EDA design simulation results for flat and stacked power-domain circuits.
- VDDA0 Power-Domain-A's voltage
- Figure 8A shows an example graph of the effect of a VDDA voltage sweep on both power-domain's timing delay (i.e. TA, TB).
- Figure 8B shows an example graph of the effect of a VDDA voltage sweep on power-domain B's voltage (VDDB).
- Figure 8C shows an example graph of the effect of a VDDA voltage sweep on the current consumption (Itotal) for both a flat and stacked set of power-domains. Again, in Figure 8C , clear minimums in the total current consumption curves, for a given Ttotal, are visible.
- VDDA should initially be about 0.7V and VDDB be about 1V, for either flat or stacked power-domain circuit designs.
- VDDA voltage sweeping routine may be used to characterize the circuit and similarly select specific VDDA and VDDB values in real-time response to changes in each power-domain's task/logic/software loading.
- Such voltage scaling adaptation functionality during design-time and run-time, optimally maintains low power consumption in the circuit.
- the overall circuit design is cleanly partitioned such that the level-shifters remain within their operating limits (e.g. power consumption and silicon area overhead) and such each power-domain has similar power consumption requirements for range of task, logic or software applications.
- the level-shifters remain within their operating limits (e.g. power consumption and silicon area overhead) and such each power-domain has similar power consumption requirements for range of task, logic or software applications.
- level-shifting is either not required or very minimally required.
- level-shifters are required.
- a well chosen set of power-domain partitions simplifies overhead calculations performed during the real-time operational phase of power-domain optimization.
- the partitioning creates a set of power-domains having different power consumption levels.
- a generic microcontroller design consumes more power in the CPU power-domain during dynamic operations, while in standby mode, the memory power-domain consumes more power, since most of the CPU logic can be powered-off.
- a memory consumes about 30-40% power while microcontroller logic consumes 60-70% of the power, when both power-domains are operating at the same voltage (e.g. 1V for 40nm technology).
- critical path delay can be between the CPU and the SRAM, where, logic is responsible for 30-40% of critical delay and memory is 60-70%. For example, for a 100MHz MCU design (10ns timing/clock period) and with memory speed ( ⁇ 130MHz in C40).
- VDDA for the CPU/MCU/logic is reduced, while the SRAM/memory is kept at 1V. This causes the CPU/MCU/logic timing delay to increase but does reduce power consumption. So as not to make the overall circuit design slower, VDDB for the SRAM/memory power-domain is increased, which reduces timing delay in the SRAM/memory power-domain.
- Figure 9 is example system 900 for hosting instructions for enabling a power-domain optimization apparatus.
- the system 900 shows an input/output data 902 interface with a computing device 904 (e.g. a controller).
- the computing device 904 includes a processor device 906, a storage device 908, and a machine-readable storage medium 910. Instructions 912 within the machine-readable storage medium 910 control how the processor 906 interprets and transforms the input data 902, using data within the storage device 908.
- the machine-readable storage medium in an alternate example embodiment is a computer-readable storage medium.
- FIG. 910 Various example sets of instructions stored in the machine-readable storage medium 910 include those shown in Figures 4 , 5 and 6 .
- the processor (such as a central processing unit, CPU, microprocessor, application-specific integrated circuit (ASIC), etc.) controls the overall operation of the storage device (such as random access memory (RAM) for temporary data storage, read only memory (ROM) for permanent data storage, firmware, flash memory, external and internal hard-disk drives, and the like).
- the processor device communicates with the storage device and non-transient machine-readable storage medium using a bus and performs operations and tasks that implement one or more instructions stored in the machine-readable storage medium.
- the machine-readable storage medium in an alternate example embodiment is a computer-readable storage medium.
- the set of instructions described above are implemented as functional and software instructions embodied as a set of executable instructions in a non-transient computer-readable or computer-usable media which are effected on a computer or machine programmed with and controlled by said executable instructions.
- Said instructions are loaded for execution on a processor (such as one or more CPUs).
- Said processor includes microprocessors, microcontrollers, processor modules or subsystems (including one or more microprocessors or microcontrollers), or other control or computing devices.
- a processor can refer to a single component or to plural components.
- Said computer-readable or computer-usable storage medium or media is (are) considered to be part of an article (or article of manufacture).
- An article or article of manufacture can refer to any manufactured single component or multiple components.
- the non-transient machine or computer-usable media or mediums as defined herein excludes signals, but such media or mediums may be capable of receiving and processing information from signals and/or other transient mediums.
- Example embodiments of the material discussed in this specification can be implemented in whole or in part through network, computer, or data based devices and/or services. These may include cloud, internet, intranet, mobile, desktop, processor, look-up table, microcontroller, consumer equipment, infrastructure, or other enabling devices and services. As may be used herein and in the claims, the following non-exclusive definitions are provided.
- one or more instructions or steps discussed herein are automated.
- the terms automated or automatically mean controlled operation of an apparatus, system, and/or process using computers and/or mechanical/electrical devices without the necessity of human intervention, observation, effort and/or decision.
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US11455450B1 (en) * | 2021-06-03 | 2022-09-27 | Cadence Design Systems, Inc. | System and method for performing sign-off timing analysis of electronic circuit designs |
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US9960769B2 (en) | 2018-05-01 |
EP3182249A1 (en) | 2017-06-21 |
CN107025322B (zh) | 2022-04-15 |
CN107025322A (zh) | 2017-08-08 |
US20170179957A1 (en) | 2017-06-22 |
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