Classifications

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  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
  • H01L23/5223—Capacitor integral with wiring layers
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  • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
  • H01F17/00—Fixed inductances of the signal type 
  • H01F17/0006—Printed inductances
  • H01F17/0013—Printed inductances with stacked layers
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  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
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  • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
  • H01L23/64—Impedance arrangements
  • H01L23/645—Inductive arrangements
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  • H01F17/00—Fixed inductances of the signal type 
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  • H01F2017/0086—Printed inductances on semiconductor substrate
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  • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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  • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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  • H01L2224/05001—Internal layers
  • H01L2224/05005—Structure
  • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
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  • H01L2224/05099—Material
  • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
  • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
  • H01L2224/05147—Copper [Cu] as principal constituent
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  • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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  • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
  • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
  • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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  • H05K1/111—Pads for surface mounting, e.g. lay-out
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
  • H05K1/165—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed inductors
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
  • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
  • H05K2201/10621—Components characterised by their electrical contacts
  • H05K2201/10674—Flip chip

Definitions

• WLP wafer level packaging
• FIG. 1 conceptually illustrates a semiconductor device that includes an inductor.
• FIG. 1 illustrates a die 100, a packaging substrate 102, a set of solder balls 104, a printed circuit board (PCB) 106, and an inductor 108.
• the die 100 is coupled to the packaging substrate 102.
• the packaging substrate 102 is coupled to the PCB 106 through the set of solder balls 104.
• the inductor 108 is defined and located in the die 100.
• FIG. 1 also illustrates that some solder balls have been omitted / removed in a region near the inductor 108. This is because solder balls can affect / disrupt the performance of an inductor. More specifically, solder balls that are near an inductor can disrupt the magnetic flux of an inductor, resulting in a low inductance and low Q factor for the inductor, which is why solder balls are removed in a region near an inductor. However, removing solder balls between a packaging substrate and a PCB can affect the structural stability of the packaging substrate and the PCB.
• solder balls e.g., better inductance and Q factor inductor
• disadvantage of removing solder balls e.g., less stable packaging substrate / PCB structure
• WLP wafer level packaging
• a first example provides an integrated device that includes a capacitor and an inductor.
• the inductor is electrically coupled to the capacitor.
• the inductor and the capacitor are configured to operate as a filter for an electrical signal in the integrated device.
• the inductor includes a first metal layer of a printed circuit board (PCB), a set of solder balls coupled to the PCB, and a second metal layer in a die.
• PCB printed circuit board
• the capacitor is located in the die.
• the capacitor is one of at least a metal-insulator- metal (MIM) capacitor, and/or metal-on-metal (MOM) capacitor.
• MIM metal-insulator- metal
• MOM metal-on-metal
• the capacitor is a surface mounted passive device on the PCB.
• the first metal layer is a trace on the PCB.
• the second metal layer is an under bump metallization (UBM) layer of the die.
• UBM under bump metallization
• the inductor further includes a third metal layer in the die.
• the second metal layer is an under bump metallization (UBM) layer of the die
• the third metal is a redistribution layer of the die.
• the integrated device is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.
• a second example provides an apparatus that includes a passive means and an inductor.
• the passive means is configured to store energy.
• the inductor is electrically coupled to the passive means.
• the inductor and the passive means are configured to operate as a filter for an electrical signal in the integrated device.
• the inductor includes a first metal layer of a printed circuit board (PCB), a set of solder balls coupled to the PCB, a second metal layer in a die.
• PCB printed circuit board
• the passive means is located in the die.
• the passive means is one of at least a metal- insulator-metal (MIM) capacitor, and/or metal-on-metal (MOM) capacitor.
• MIM metal-insulator-metal
• MOM metal-on-metal
• the passive means is a surface mounted passive device on the PCB.
• the first metal layer is a trace on the PCB.
• the second metal layer is an under bump metallization (UBM) layer of the die.
• UBM under bump metallization
• the inductor includes a third metal layer in the die.
• the second metal layer is an under bump metallization (UBM) layer of the die
• the third metal is a redistribution layer of the die.
• the apparatus is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.
• a third example provides a method for fabricating an integrated device.
• the method provides a capacitor.
• the method provides an inductor such that the inductor is electrically coupled to the capacitor.
• the inductor and the capacitor are configured to operate as a filter for an electrical signal in the integrated device.
• the method of providing the inductor includes forming a first metal layer of a printed circuit board (PCB).
• the method of providing the inductor includes providing a set of solder balls coupled to the PCB.
• the method of providing the inductor includes forming a second metal layer in a die.
• the capacitor is located in the die. [0027] According to one aspect, the capacitor is one of at least a metal-insulator- metal (MIM) capacitor, and/or metal-on-metal (MOM) capacitor.
• MIM metal-insulator- metal
• MOM metal-on-metal
• the capacitor is a surface mounted passive device on the PCB.
• the first metal layer is a trace on the PCB.
• the second metal layer is an under bump metallization (UBM) layer of the die.
• UBM under bump metallization
• providing the inductor further comprises forming a third metal layer in the die.
• the second metal layer is an under bump metallization (UBM) layer of the die
• the third metal is a redistribution layer of the die.
• the integrated device is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.
• a fourth example provides an integrated device that includes a capacitor and an inductor.
• the inductor is electrically coupled to the capacitor.
• the inductor and the capacitor are configured to operate as a filter for an electrical signal in the integrated device.
• the inductor includes a first metal layer of a substrate, a set of solder balls coupled to the substrate, and a second metal layer in a die.
• the capacitor is located in the die.
• the capacitor is one of at least a metal-insulator- metal (MIM) capacitor, and/or metal-on-metal (MOM) capacitor.
• MIM metal-insulator- metal
• MOM metal-on-metal
• the capacitor is a surface mounted passive device on the substrate.
• the first metal layer is a trace on the substrate.
• the substrate is one of at least a package substrate and/or an interposer.
• the integrated device is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.
• a fifth example provides an apparatus that includes a passive means and an inductor.
• the passive means is configured to store energy.
• the inductor is electrically coupled to the passive means.
• the inductor and the passive means are configured to operate as a filter for an electrical signal in the integrated device.
• the inductor includes a first metal layer of a substrate, a set of solder balls coupled to the substrate, a second metal layer in a die.
• the passive means is located in the die.
• the passive means is one of at least a metal- insulator-metal (MIM) capacitor, and/or metal-on-metal (MOM) capacitor.
• MIM metal-insulator-metal
• MOM metal-on-metal
• the passive means is a surface mounted passive device on the substrate.
• the substrate is one of at least a package substrate and/or an interposer.
• the apparatus is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.
• a sixth example provides a method for fabricating an integrated device.
• the method provides a capacitor.
• the method provides an inductor such that the inductor is electrically coupled to the capacitor.
• the inductor and the capacitor are configured to operate as a filter for an electrical signal in the integrated device.
• the method of providing the inductor includes forming a first metal layer of a substrate.
• the method of providing the inductor includes providing a set of solder balls coupled to the substrate.
• the method of providing the inductor includes forming a second metal layer in a die.
• the capacitor is located in the die.
• the capacitor is one of at least a metal-insulator- metal (MIM) capacitor, and/or metal-on-metal (MOM) capacitor.
• MIM metal-insulator- metal
• MOM metal-on-metal
• the capacitor is a surface mounted passive device on the substrate.
• the integrated device is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.
• FIG. 1 illustrates a known inductor integrated in a die.
• FIG. 2 illustrates an inductor defined between a die and a printed circuit board (PCB), where the die includes a capacitor.
• PCB printed circuit board
• FIG. 3 illustrates an inductor defined between a die and a printed circuit board (PCB), where a capacitor is coupled to the PCB.
• PCB printed circuit board
• FIG. 4 illustrates a conceptual inductor having 2 turns defined between a die and a printed circuit board (PCB).
• PCB printed circuit board
• FIG. 5 illustrates a conceptual inductor having 3 turns defined between a die and a printed circuit board (PCB).
• PCB printed circuit board
• FIG. 6 illustrates an angled view of an inductor defined between a die and a printed circuit board (PCB).
• PCB printed circuit board
• FIG. 7 illustrates a side view of an inductor defined between a die and a printed circuit board (PCB).
• PCB printed circuit board
• FIG. 8 illustrates a bottom view of an inductor defined between a die and a printed circuit board (PCB).
• PCB printed circuit board
• FIG. 9 illustrates a top view of an inductor defined between a die and a printed circuit board (PCB).
• PCB printed circuit board
• FIG. 10 illustrates an angled view of an inductor defined between a die and a printed circuit board (PCB).
• PCB printed circuit board
• FIG. 11 illustrates a plan view of an inductor defined between a die and a printed circuit board (PCB).
• PCB printed circuit board
• FIG. 12 illustrates a profile view of an inductor defined between a die and a printed circuit board (PCB).
• PCB printed circuit board
• FIG. 13 illustrates a flow diagram for manufacturing / providing an inductor.
• FIG. 14 illustrates an inductor defined between a first die and a second die.
• FIG. 15 illustrates an inductor in a package on package structure.
• FIG. 16 illustrates a flow diagram for manufacturing / providing an inductor.
• FIG. 17 illustrates a flow diagram for manufacturing / providing an inductor.
• FIG. 18 illustrates a profile view of an integrated device that includes a capacitor and part of an inductor.
• FIG. 19 illustrates a profile view of an integrated device that includes another capacitor and part of an inductor.
• FIG. 20 (comprising FIGS. 20A-20D) illustrates an example of a sequence for fabricating an integrated device that includes a capacitor.
• FIG. 21 illustrates a flow diagram of a method for fabricating an integrated device that includes a capacitor.
• FIG. 22 illustrates an example of a semi-additive patterning (SAP) process.
• FIG. 23 illustrates an example of flow diagram of a semi-additive patterning (SAP) process.
• SAP semi-additive patterning
• FIG. 24 illustrates an example of a damascene process.
• FIG. 25 illustrates an example of a flow diagram of a damascene process.
• FIG. 26 illustrates various electronic devices that may integrate an integrated device, a die, an integrated circuit and/or PCB described herein.
• Some implementations provide an integrated device that includes a capacitor and an inductor.
• the inductor is electrically coupled to the capacitor.
• the inductor and the capacitor are configured to operate as a filter for an electrical signal in the integrated device.
• the inductor includes a first metal layer of a printed circuit board (PCB), a set of solder balls coupled to the PCB, and a second metal layer in a die.
• a capacitor is a passive means configured to store energy (e.g., store energy electrostatically in an electric field).
• the capacitor is located in the die.
• the capacitor is one of at least a metal- insulator-metal (MIM) capacitor, and/or metal-on-metal (MOM) capacitor.
• MIM metal- insulator-metal
• MOM metal-on-metal
• the capacitor is a surface mounted passive device on the PCB.
• the first metal layer is a trace on the PCB.
• the second metal layer is an under bump metallization (UBM) layer of the die.
• the inductor includes a third metal layer in the die.
• the second metal layer is an under bump metallization (UBM) layer of the die, and the third metal is a redistribution layer of the die.
• Some implementations provide an integrated device that includes a capacitor and an inductor.
• the inductor is electrically coupled to the capacitor.
• the inductor and the capacitor are configured to operate as a filter for an electrical signal in the integrated device.
• the inductor includes a first metal layer of a substrate, a set of solder balls coupled to the substrate, and a second metal layer in a die.
• An interconnect is an element or component that allows or facilitates an electrical connection between two points, elements and/or components.
• an interconnect may include a trace, a via, a pad, a pillar, a redistribution layer, an under bump metallization (UBM) layer, and/or solder (e.g., solder balls).
• UBM under bump metallization
• solder e.g., solder balls.
• an interconnect is an electrically conductive material that provides an electrical path for a signal (e.g., data signal, ground signal, power signal).
• An interconnect may include one element / component or several elements /components that provide an electrical path for a signal.
• FIG. 2 conceptually illustrates a novel inductor for an integrated device.
• a die 200 that is coupled to a printed circuit board (PCB) 202 through a set of solder balls 204.
• the die 200 is a wafer- level packaging die (e.g., manufactured using a wafer level packaging process).
• FIG. 2 illustrates a capacitor 203 located in the die 200.
• the capacitor 203 is located in the lower level metal layers of the die 200. More specific examples of a capacitor in the lower level metal layers of a die are further described in FIGS. 18-19.
• a capacitor is a passive means (e.g., passive capacitive means) configured to store energy (e.g., store energy electrostatically in an electric field).
• FIG. 2 also conceptually illustrates an inductor 206 that is defined by components on the die 200, components on the PCB 202, and at least one solder ball 204.
• the inductor 206 is configured to operate with the capacitor 203 as a filter for an electrical signal.
• the filter is one of at least a trap filter and/or a notch filter.
• the filter is a high quality factor (Q) filter.
• the die 200 includes a first set of metal layers 210, a via 212, a passivation layer 214, a first polyimide layer 216, a second metal layer 218, a second polyimide layer 220, and a under bump metallization (UBM) layer 222.
• the first set of metal layers 210 are stacked metal layers in some implementations.
• a dielectric layers may be positioned between the metal layers in the first set of metal layers 210.
• the via 212 couples at least one of metal layer from the first set of metal layers 210 to the second metal layer 218.
• the second metal layer 218 is a post passivation layer.
• the post passivation layer may be referred as the post passivation interconnect (PPI) layer.
• the second metal layer 218 may be a copper layer in some implementations.
• the UBM layer 222 is coupled to the second metal layer 218 (e.g., copper layer).
• the UBM layer 222 is coupled to a solder ball 204.
• a polyimide layer e.g., first polyimide layer 216) may be an insulative layer.
• the PCB 202 includes a first PCB layer 202a (e.g., PCB LI), a second PCB layer 202b (e.g., PCB L2), and a third PCB layer 202c (e.g., PCB L3).
• One of more of the PCB layers 200a-200c may include one or more traces.
• the first PCB layer 202a includes a trace 224, which is coupled to the solder ball 204.
• the inductor 206 may include a winding.
• the winding of the inductor 206 may be defined by at least one metal layer from the first set of metal layers 210, the via 212, the second metal layer 218, the solder ball 204 and the trace 224.
• the winding of the inductor 206 may have several turns (e.g., 2 turns).
• the inductor 206 leverages one or more traces of the PCB 202 and the solder balls 204 to provide an inductor with better inductance (L), lower resistance and better quality (Q) factor value.
• the inductance generated by the trace and the height of the solder ball, and the magnetic flux between the PCB and metal layers (e.g., metal layer 210, second metal layer 218) of the die 200 help increase the inductance of the inductor 206.
• inductors that integrate solder balls as part of the inductor are capable of more turns in a given area / space (e.g., area of the die, area of package, area of PCB) than an inductor that does not include solder balls. Inductors with more turns have better inductance (L) than inductors with fewer turns.
• an inductor that includes solder balls thus is able to be configured to have more turns, will have better inductance (L) than an inductor that does not include solder balls.
• L inductance
• the solder balls 204 not only help increase the inductance of the inductor 206, but the solder balls 204 also help provide structure stability for the die 200 and the PCB 202 in some implementations.
• FIG. 3 conceptually illustrates another novel inductor for an integrated device.
• FIG. 3 illustrates a die 200 that is coupled to a printed circuit board (PCB) 202 through a set of solder balls 204.
• the die 200 is a wafer-level packaging die (e.g., manufactured using a wafer level packaging process).
• FIG. 3 is similar to FIG.2, except that a capacitor is located in a different location.
• FIG. 3 illustrates a capacitor 303 that is located on the printed circuit board 202.
• the capacitor 303 is a surface mounted passive device coupled to pads and/or traces on the printed circuit board (PCB) 202.
• the inductor of FIG. 2 may be defined by components of a substrate (e.g., package substrate, interposer) instead of a PCB. That is, in some implementations, an inductor may be defined by components of a die, a substrate, and a solder ball.
• a substrate e.g., package substrate, interposer
• an inductor may be defined by components of a die, a substrate, and a solder ball.
• FIG. 3 also conceptually illustrates an inductor 206 that is defined by components on the die 200, components on the PCB 202, and at least one solder ball 204.
• the inductor 206 is configured to operate with the capacitor 303 as a filter for an electrical signal.
• the filter is one of at least a trap filter and/or a notch filter.
• the filter is a high quality factor (Q) filter.
• the inductor of FIG. 3 may be defined by components of a substrate (e.g., package substrate, interposer) instead of a PCB. That is, in some implementations, an inductor may be defined by components of a die, a substrate, and a solder ball.
• a substrate e.g., package substrate, interposer
• an inductor may be defined by components of a die, a substrate, and a solder ball.
• FIGS. 4-5 illustrate an inductor that is defined by components from a die, solder balls, and a printed circuit board (PCB) in some implementations.
• FIG. 4 illustrates an inductor 400 that includes a winding that has 2 turns.
• the winding of the inductor 400 is defined by a first metal layer 402, a second metal layer 404, a set of vias 406, a set of solder balls 408, and a set of traces 410.
• other materials may be used instead of or in conjunction with the solder ball 204.
• a metal interconnect e.g., copper
• interconnecting metal layer may be used.
• the first metal layer 402 may be a metal layer from stacked metal layers (e.g., stacked metal layers 210) of a die (e.g., die 200).
• the second metal layer 404 may be a copper layer (e.g., second metal layer 218) of a die.
• the second metal layer 404 is coupled to the first metal layer 402 through the set of vias 406.
• the second metal layer 404 is also coupled to the set of solder balls 408.
• the second metal layer 404 is positioned between the set of solder balls 408 and a passivation layer (not shown) of a die.
• the die is a wafer-level packaging die (e.g., manufactured using a wafer level packaging process).
• the set of traces 410 may be one or more trace on a first layer of a printed circuit board (PCB) in some implementations.
• PCB printed circuit board
• FIG. 5 illustrates another inductor 500 that includes a winding.
• the inductor 500 is similar to the inductor 300 of FIG. 3, except that the inductor 500 has a winding that has 3 turns.
• the winding of the inductor 500 is defined by a first metal layer 502, a second metal layer 504, a set of vias (not visible), a set of solder balls 506, and a set of traces 508.
• the first metal layer 502 may be a metal layer from stacked metal layers (e.g., stacked metal layers 210) of a die (e.g., die 200).
• the second metal layer 504 may be a copper layer (e.g., second metal layer 218) of a die.
• the second metal layer 504 is coupled to the first metal layer 502 through the set of vias (not visible).
• the second metal layer 504 is also coupled to the set of solder balls 506.
• the second metal layer 504 is positioned between the set of solder balls 506 and a passivation layer (not shown) of a die.
• the die is a wafer-level packaging die (e.g., manufactured using a wafer level packaging process).
• the set of traces 508 may be one or more trace on a first layer of a printed circuit board (PCB) in some implementations.
• the above exemplary inductors that include / integrate solder balls as part of the inductor provide several technical advantages over known inductors (e.g., inductors that do not integrate solder balls). For example, the above exemplary inductors provide better performance / properties than known inductors.
• Some of the relevant properties of an inductor include effective inductance, Q factor and/or effectiveness of the coupling of the inductor.
• the effectiveness of an inductor may be defined by its Q factor.
• a Q factor is a quality factor/value that defines the efficiency of an inductor.
• the higher the Q factor the closer the inductor approaches the behavior of an ideal inductor, which is a lossless inductor. Thus, generally speaking, a higher Q factor is more desirable than a lower Q factor.
• the above exemplary inductors have better inductance (L) (e.g., higher inductance), better Q factor (e.g., higher Q factor) and better resistance (R) (e.g., lower resistance).
• these better properties may be achieved by maximizing magnetic flux by increasing the number of turns / windings of the inductor in a given area (e.g., area of the die, area of package, area of PCB) and thus increasing the coupling between layers.
• integrating solder balls as part of an inductor allows for more turns in the inductor in a given area / space (e.g., area of the die, area of package, area of PCB).
• integrating solder balls in an inductor increases the inductance (L), which increases the Q factor of the inductor.
• solder balls leverage the height of the solder balls to increase inductance.
• One benefit of using an inductor that integrates solder balls is that such inductors are capable of supporting high current for high power applications.
• the relatively large size of solder balls (compared to metal layers of the die that are part of the inductor) lowers the resistance of the inductor, which effectively increases the Q factor of the inductor.
• traces on a PCB that are part of an inductor are typically larger than metal layers in a die that are part of the inductor.
• these traces (that area part of the inductor) of PCB may be about 2 times wider than the metal interconnects / lines (that area part of the inductor) on the die. These wider traces have lower resistance than the narrower metal interconnects. Consequently, these wider traces lower the overall effective resistance of the inductor. As result, an inductor that integrate traces on the PCB as part of the inductor has a better Q factor (because of the lower resistance) than an inductor that is solely in a die.
• the inductor of FIGS. 4-5 may be defined by components of a substrate (e.g., package substrate, interposer) instead of a PCB. That is, in some implementations, an inductor may be defined by components of a die, a substrate, and a solder ball.
• FIGS. 6-9 illustrate another example of a novel inductor in some implementations.
• FIG. 6 illustrates an inductor 600 from an angled point of view.
• the inductor 600 includes a first metal layer 602, a second metal layer 604, a set of vias 605, a third metal layer 606, a set of solder balls 608 (e.g., first solder ball 608a, second solder ball 608b, third solder ball 608c, fourth solder ball 608d, fifth solder ball 608e), a fourth metal layer 610, a via 612 and a fifth metal layer 614.
• solder balls 608 e.g., first solder ball 608a, second solder ball 608b, third solder ball 608c, fourth solder ball 608d, fifth solder ball 608e
• the first metal layer 602, the second metal layer 604 and the third metal layer 606 are metal layers of a die.
• the first, second and third metal layers 602-606 may be one of the metal layers of the die 200 of FIG. 2.
• the first and second metal layers 602-604 may correspond to the metal layers 210 of FIG. 2 and the third metal layer 606 may correspond to the second metal layer 218 (e.g., post passivation interconnect (PPI) layer) of FIG. 2 in some implementations.
• the die is a wafer-level packaging die (e.g., manufactured using a wafer level packaging process).
• the set of vias 605 may be vias in a die in some implementations.
• one of the vias from the set of vias 605 may correspond to the via 212 of FIG. 2.
• the set of vias 605 is positioned and configured to reduce the resistance of the inductance, thereby increasing the Q factor of the inductor.
• the set of solder balls 608 provides an interconnect path / interconnect means between a die and a printed circuit board (PCB).
• PCB printed circuit board
• other materials may be used to provide an interconnect path / interconnect means between a die and a PCB.
• the fourth metal layer 610, the via 612 and the fifth metal layer 614 are located in a printed circuit board (PCB).
• the fourth metal layer 610 and the fifth metal layer 614 may be metal layers of a PCB.
• the fourth metal layer may be the trace 224 (e.g., metal layer) of the PCB 202 of FIG. 2 in some implementations.
• FIG. 7 illustrates a side view of the inductor 600 of FIG. 6.
• FIG. 7 illustrates a side view of an inductor defined by metal layers of a die, solder balls and metal layers of a printed circuit board.
• the inductor 600 includes the first metal layer 602, the second metal layer 604, the set of vias 605, the third metal layer 606, the set of solder balls 608 (e.g., first solder ball 608a, second solder ball 608b, third solder ball 608c), the fourth metal layer 610, a via 612 and a fifth metal layer 614.
• the first metal layer 602, the second metal layer 604 and the third metal layer 606 are metal layers of a die.
• the first, second and third metal layers 602-606 may be one of the metal layers of the die 200 of FIG. 2.
• the first and second metal layers 602-604 may correspond to the metal layers 210 of FIG. 2 and the third metal layer 606 may correspond to the second metal layer 218 (e.g., post passivation interconnect (PPI) layer) of FIG. 2 in some implementations.
• the die is a wafer-level packaging die (e.g., manufactured using a wafer level packaging process).
• the set of vias 605 may be vias in a die in some implementations.
• one of the vias from the set of vias 605 may correspond to the via 212 of FIG. 2.
• the set of solder balls 608 provides an interconnect path / interconnect means between a die and a printed circuit board (PCB).
• PCB printed circuit board
• other materials may be used to provide an interconnect path / interconnect means between a die and a PCB.
• the fourth metal layer 610, the via 612 and the fifth metal layer 614 are located in a printed circuit board (PCB).
• the fourth metal layer 610 and the fifth metal layer 614 may be metal layers of a PCB.
• the fourth metal layer may be the trace 224 (e.g., metal layer) of the PCB 202 of FIG. 2 in some implementations.
• FIG. 8 illustrates a view (e.g., bottom view) of the inductor 600 of FIG. 6 from the perspective of the die. Specifically, FIG. 8 illustrates a bottom view of an inductor defined by metal layers of a die, solder balls and metal layers of a printed circuit board. It should be noted that the view of FIG. 8 may be a top view depending on how the inductor, die, and/or PCB are positioned. As shown in FIG.
• the inductor 600 includes the first metal layer 602, the second metal layer 604, the set of vias 605, the third metal layer 606, the set of solder balls 608 (e.g., first solder ball 608a, second solder ball 608b, third solder ball 608c), the fourth metal layer 610, a via 612 and a fifth metal layer 614.
• the first metal layer 602, the second metal layer 604 and the third metal layer 606 are metal layers of a die.
• the first, second and third metal layers 602-606 may be one of the metal layers of the die 200 of FIG. 2.
• the first and second metal layers 602-604 may correspond to the metal layers 210 of FIG. 2 and the third metal layer 606 may correspond to the second metal layer 218 (e.g., post passivation interconnect (PPI) layer) of FIG. 2 in some implementations.
• the die is a wafer-level packaging die (e.g., manufactured using a wafer level packaging process).
• the set of vias 605 may be vias in a die in some implementations.
• one of the vias from the set of vias 605 may correspond to the via 212 of FIG. 2.
• the set of solder balls 608 provides an interconnect path / interconnect means between a die and a printed circuit board (PCB).
• PCB printed circuit board
• other materials may be used to provide an interconnect path / interconnect means between a die and a PCB.
• the fourth metal layer 610, the via 612 and the fifth metal layer 614 are located in a printed circuit board (PCB).
• the fourth metal layer 610 and the fifth metal layer 614 may be metal layers of a PCB.
• the fourth metal layer may be the trace 224 (e.g., metal layer) of the PCB 202 of FIG. 2 in some implementations.
• FIG. 9 illustrates a view (e.g., top view) of the inductor 600 of FIG. 6 from the perspective of the printed circuit board (PCB).
• FIG. 9 illustrates a top view of an inductor defined by metal layers of a die, solder balls and metal layers of a printed circuit board. It should be noted that the view of FIG. 9 may be a bottom view depending on how the inductor, die, and/or PCB are positioned. As shown in FIG.
• the inductor 600 includes the first metal layer 602, the second metal layer 604, the set of vias 605, the third metal layer 606, the set of solder balls 608 (e.g., first solder ball 608a, second solder ball 608b, third solder ball 608c), the fourth metal layer 610, a via 612 and a fifth metal layer 614.
• the first metal layer 602, the second metal layer 604 and the third metal layer 606 are metal layers of a die.
• the first, second and third metal layers 602-606 may be one of the metal layers of the die 200 of FIG. 2.
• the first and second metal layers 602-604 may correspond to the metal layers 210 of FIG. 2 and the third metal layer 606 may correspond to the second metal layer 218 (e.g., post passivation interconnect (PPI) layer) of FIG. 2 in some implementations.
• the die is a wafer-level packaging die (e.g., manufactured using a wafer level packaging process).
• the set of vias 605 may be vias in a die in some implementations.
• one of the vias from the set of vias 605 may correspond to the via 212 of FIG. 2.
• the set of solder balls 608 provides an interconnect path / interconnect means between a die and a printed circuit board (PCB).
• PCB printed circuit board
• other materials may be used to provide an interconnect path / interconnect means between a die and a PCB.
• the fourth metal layer 610, the via 612 and the fifth metal layer 614 are located in a printed circuit board (PCB).
• the fourth metal layer 610 and the fifth metal layer 614 may be metal layers of a PCB.
• the fourth metal layer may be the trace 224 (e.g., metal layer) of the PCB 202 of FIG. 2 in some implementations.
• FIGS. 2-9 illustrate examples of an inductor defined by components on a die, printed circuit board (PCB) and a solder ball. As shown in FIGS. 2-9, these inductors bypass the use of a packaging substrate. In other words, these inductors are free of a packaging substrate. The advantage of bypassing the use of a packaging substrate is lower cost (because of using less material) and smaller size.
• an inductor may also be defined by components on a first die, a second die, and a solder ball. These other types of inductors will be further described below.
• the inductor may be defined by components of a substrate (e.g., package substrate, interposer) instead of a PCB. That is, in some implementations, an inductor may be defined by components of a die, a substrate, and a solder ball.
• FIGS 10-12 illustrate another novel inductor in some implementations.
• FIG. 10 illustrates an angled view of an inductor 1000 formed by traces in a printed circuit board (PCB), at least one solder ball, and metal layers in an integrated device.
• FIG. 10 illustrates the inductor 1000 that includes a first interconnect 1002, a solder ball 1004, an under bump metallization (UBM) layer 1006, and a first redistribution layer 1010.
• the first interconnect 1002 is a trace in/on a printed circuit board (PCB).
• the first interconnect 1002 is an interconnect on a substrate (e.g., package substrate, interposer).
• FIG. 10 illustrates an angled view of an inductor 1000 formed by traces in a printed circuit board (PCB), at least one solder ball, and metal layers in an integrated device.
• FIG. 10 illustrates the inductor 1000 that includes a first interconnect 1002, a solder ball 1004, an under bump metallization (UBM) layer 1006, and
• FIG. 10 illustrates an dielectric layer 1006 between the UBM layer 1006 and the first redistribution layer 1010.
• FIG. 1 1 illustrates a plan view of the inductor 1000 of FIG. 10.
• FIG. 12 illustrates a profile view of the inductor 1000 of FIG. 10.
• the inductor of FIGS. 10-12 may be defined by components of a substrate (e.g., package substrate, interposer) instead of a PCB. That is, in some implementations, an inductor may be defined by components of a die, a substrate, and a solder ball. [00115] Having described various novel inductors (e.g., inductor defined by two dies, inductor defined by two package substrates), methods for fabricating / providing such inductors will now be described below.
• FIG. 13 illustrates a flow diagram of a method for fabricating / providing an inductor and/or capacitor.
• the method of FIG. 13 may be implemented to manufacture / provide the inductors described in FIGS. 2-12.
• the method provides (at 1305) a die that includes a first metal layer, a second metal layer and a capacitor.
• the second metal may be a post passivation layer.
• the die may include a passivation layer.
• the passivation layer may be a dielectric material and may be located between the first metal layer and the second metal layer (e.g., post passivation layer) of the die.
• the die may also include an under bump metallization layer (UBM) layer, which is coupled to the second metal layer of the die.
• UBM under bump metallization layer
• the die is manufactured using wafer level packaging.
• the capacitor may be located in the lower level metal layers of the die. An example of a die with a capacitor is further described in FIGS. 18-19.
• the method couples (at 1310) a set of solder balls to the die.
• coupling the set of solder balls to the die includes coupling a solder ball to a UBM layer of the die.
• FIG. 2 illustrates an example of a solder ball coupled to a UBM layer of a die. Specifically, FIG. 2 illustrates solder ball 204 coupled to UBM 222 of die 200.
• the method further couples (at 1315) the die that includes the set of solder balls to a printed circuit board (PCB).
• the PCB includes a third metal layer.
• the PCB may include additional metal layers (e.g., fourth metal layer, fifth metal layer).
• the additional metal layers of the PCB e.g., fourth metal layer, fifth metal layer
• the combination of the inductor and capacitor provides an electrical signal filter with a high Q value.
• the filter is one of at least a trap filter and/or a notch filter.
• FIGS. 2-12 illustrate some examples of novel inductors and capacitors. However, some implementations may also use different designs and configurations.
• FIGS. 14-15 illustrate other examples of novel inductors and capacitors.
• FIG. 14 conceptually illustrates a novel inductor for an integrated device that includes a capacitor.
• FIG. 14 illustrates a first die 1400 that is coupled to a second die 1402 through a set of solder balls 1404.
• the first die and/or second die are wafer-level packaging dies (e.g., manufactured using a wafer level packaging process).
• FIG. 14 illustrates a capacitor 1403 located in the first die 1400. Specifically, the capacitor 1403 is located in the lower level metal layers of the die 1400. More specific examples of a capacitor in the lower level metal layers of a die are further described in FIGS. 18-19.
• a capacitor is a passive means (e.g., passive capacitive means) configured to store energy (e.g., store energy electrostatically in an electric field).
• FIG. 14 also conceptually illustrates an inductor 1406 that is defined by components on the first die 1400, components on the second die 1402, and at least one solder ball 1404.
• the inductor 1406 is configured to operate with the capacitor 1403 as a filter for an electrical signal.
• the filter is one of at least a trap filter and/or a notch filter.
• the filter is a high quality factor (Q) filter.
• the first die 1400 includes a first set of metal layers 1410, a via 1412, a passivation layer 1414, a first polyimide layer 1416, a second metal layer 1418, a second polyimide layer 1420, and a under bump metallization (UBM) layer 1422.
• the first set of metal layers 1410 are stacked metal layers in some implementations.
• a dielectric layers may be positioned between the metal layers in the first set of metal layers 210.
• the via 1412 couples at least one of metal layer from the first set of metal layers 1410 to the second metal layer 1418.
• the second metal layer 1418 is a post passivation layer.
• the post passivation layer may be referred as the post passivation interconnect (PPI) layer.
• the second metal layer 1418 may be a copper layer in some implementations.
• the UBM layer 1422 is coupled to the second metal layer 1418 (e.g., copper layer).
• the UBM layer 1422 is coupled to a solder 1404.
• the second die 1402 includes a first set of metal layers 1430, a via 1432, a passivation layer 1434, a first polyimide layer 1436, a second metal layer 1438, a second polyimide layer 1440, and an under bump metallization (UBM) layer 1442.
• the first set of metal layers 1430 are stacked metal layers in some implementations.
• the via 1432 couples at least one of metal layer from the first set of metal layers 1430 to the second metal layer 1438.
• the second metal layer 1438 may be a copper layer in some implementations.
• the UBM layer 1442 is coupled to the second metal layer 1438 (e.g., copper layer).
• the UBM layer 1442 is coupled to a solder 1404.
• the inductor 1406 may include a winding.
• the winding of the inductor 1406 may be defined by at least one metal layer from the first set of metal layers 1410, the via 1412, the second metal layer 1418, the solder 1404, the second metal layer 1438, the via 1432, and at least one metal layer from the first set of metal layers 1430.
• the winding of the inductor 1406 may have several turns (e.g., 2 turns).
• a die may be in a die package (which includes a packaging substrate).
• a die package may be referred to as a wafer level package.
• an inductor may be defined by components of a first die package, a second die package, and a set of solder balls.
• FIG. 15 illustrates an inductor defined in a package on package (PoP) structure that includes a capacitor.
• the PoP structure 1500 includes a first package substrate 1502, a capacitor 1503, a first die 1504, a first set of solder balls 1506, a second package substrate 1508, a second die 1510, a third die 1512, a second set of solder balls 1514.
• the first die 1504 may be a logic die.
• the second and third dies 1510-1512 may be stacked memory dies in some implementations .
• the first package of the PoP structure 1500 may includes the first package substrate 1502, the capacitor 1503, the first die 1504, and the first set of solder balls 1506.
• the first die 1504 may be an Application Specific Integrated Circuit (ASIC) die in some implementations.
• the second package of the PoP structure 1500 may includes the second package substrate 1508, the second die 1510, the third die 1512, and the second set of solder balls 1514.
• the capacitor 1503 is a surface mounted passive device that is coupled to the first package substrate 1502.
• a capacitor is a passive means (e.g., passive capacitive means) configured to store energy (e.g., store energy electrostatically in an electric field).
• an inductor 1516 in the PoP structure 1500 may be defined by the second set of solder balls 1514 (e.g., solder ball 1514a, solder ball 1514b) and at least one metal layer in the first and second package substrate 1502 and 1508.
• the metal layer 1518 of the first package substrate 1502, the solder ball 1514a, the solder ball 1514b, and the metal layer 1520 of the second package substrate 1508 are configured to operate as the inductor 1516 in the PoP structure 1500 in some implementations.
• the first package substrate 1502 may include additional metal layers.
• the second package substrate 1508 may include additional metal layers.
• one or more additional metal layers of the first package substrate 1502 and/or second package substrate 1508 may be part of the inductor 1516. That is, in some implementations, one or more additional metal layers of the first package substrate 1502 and/or second package substrate 1508 may be configured to operate as the inductor 1516.
• first and second metal layers of the first package substrate 1502, second and third metal layers of the second package substrate 1508, and the solder balls 1514a-b may be configured to operate as an inductor in some implementations.
• solder balls 1514a-b are integrated in the inductor 1516. However, in some implementations, other interconnecting means may be used in lieu of or in conjunction with the solder balls.
• the inductor 1516 is configured to operate with the capacitor 1503 as a filter for an electrical signal.
• the filter is one of at least a trap filter and/or a notch filter.
• the filter is a high quality factor (Q) filter.
• FIG. 16 illustrates a flow diagram of a method for fabricating / providing an inductor defined by two dies and a set of solder balls.
• the method of FIG. 16 may be implemented to manufacture / provide the inductor described in FIG. 14.
• the method provides (at 1605) a first die that includes a first metal layer and a capacitor.
• the capacitor is located in lower level metal layers of the first die. Examples of capacitors in lower level metal layers of a die are further described in FIGS. 18-19.
• the first die is manufactured using wafer level packaging.
• the first die may include additional metal layers (e.g., third metal layer).
• one of the metal layers of the first die may be a post passivation layer.
• the first die may include a passivation layer.
• the passivation layer may be a dielectric material and may be located between the first metal layer and another metal layer of the first die.
• the first die may also include an under bump metallization layer (UBM) layer, which is coupled to the first metal layer of the die.
• UBM under bump metallization layer
• the method couples (at 1610) a set of solder balls to the first die.
• coupling the set of solder balls to the first die includes coupling a solder ball to a UBM layer of the first die.
• FIG. 14 illustrates an example of a solder ball coupled to a UBM layer of a die. Specifically, FIG. 14 illustrates solder ball 1404 coupled to UBM 1422 of die 1400.
• the method further couples (at 1615) the first die that includes the set of solder balls to a second die.
• the second die is manufactured using wafer level packaging.
• the second die includes a second metal layer.
• the second die may include additional metal layers (e.g., fourth metal layer, fifth metal layer).
• the additional metal layers of the second die e.g., fourth metal layer, fifth metal layer
• the additional metal layers of the second die may be configured to operate as an inductor.
• the inductor is configured to operate with the capacitor as a filter for an electrical signal.
• the filter is one of at least a trap filter and/or a notch filter.
• the filter is a high quality factor (Q) filter.
• FIG. 17 illustrates a flow diagram of a method for fabricating / providing an inductor defined by two package substrates and a set of solder balls, where at least one substrate includes a capacitor.
• the method of FIG. 17 may be implemented to manufacture / provide the inductor described in FIG. 15.
• the method provides (at 1705) a first package substrate that includes a first metal layer and a capacitor.
• the capacitor is a surface mounted passive device.
• the first package substrate may include additional metal layers (e.g., third metal layer).
• the package substrate may include one or more dies in some implementations.
• the method couples (at 1710) a set of solder balls to the first package substrate.
• the method further couples (at 1715) the first package substrate that includes the set of solder balls to a second package substrate.
• the second package substrate includes a second metal layer.
• the second package substrate may include additional metal layers (e.g., fourth metal layer, fifth metal layer).
• the second package substrate may also include one or more dies in some implementations.
• the additional metal layers of the second package substrate (e.g., fourth metal layer, fifth metal layer) along with the first and third metal layers of the first package substrate, the set of solder balls and the second metal layer of the second package substrate may be configured to operate as an inductor.
• the inductor is configured to operate with the capacitor as a filter for an electrical signal.
• the filter is one of at least a trap filter and/or a notch filter.
• the filter is a high quality factor (Q) filter.
• FIG. 18 illustrates an example of a profile view of an integrated device 1800 that includes a capacitor and part of an inductor.
• the integrated device 1800 includes a substrate 1801, several lower level metal and dielectric layers 1802, a pad 1804, a passivation layer 1806, a first insulation layer 1808, a first metal redistribution layer 1810, a second insulation layer 1812, and an under bump metallization (UBM) layer 1814.
• the integrated device 1800 also includes a solder ball 1816. Specifically, the solder ball 1816 of the integrated device 1800 is coupled to a trace of a printed circuit board (PCB) (not shown).
• PCB printed circuit board
• the solder ball 1816, the UBM layer 1814, and /or the first metal redistribution layer 1810 is part of an inductor in the integrated device 1800.
• the lower level metal and dielectric layers 1802 includes a capacitor.
• a capacitor is a passive capacitive means configured to store energy (e.g., store energy electrostatically in an electric field).
• the capacitor is a metal-insulator-metal (MIM) capacitor.
• the capacitor includes a first interconnect 1820, a second interconnect 1821, a third interconnect 1823, a fourth interconnect 1824, and a fifth interconnect 1825.
• the first interconnect 1820 is a first via.
• the second interconnect 1821 is a first trace.
• the third interconnect 1823 is a second trace.
• the fourth interconnect 1824 is a second via.
• the fifth interconnect 1825 is a third trace.
• the first interconnect 1820, the second interconnect 1821, the third interconnect 1823, the fourth interconnect 1824, and/or the fifth interconnect 1825 are lower level metal layers in the integrated device 1800 (e.g., die).
• FIG. 19 illustrates an example of a profile view of an integrated device 1900 that includes a capacitor and part of an inductor.
• the integrated device 1900 includes a substrate 1901, several lower level metal and dielectric layers 1902, a pad 1904, a passivation layer 1906, a first insulation layer 1908, a first metal redistribution layer 1910, a second insulation layer 1912, and an under bump metallization (UBM) layer 1914.
• the integrated device 1900 also includes a solder ball 1916.
• the solder ball 1916 of the integrated device 1900 is coupled to a trace of a printed circuit board (PCB) (not shown).
• PCB printed circuit board
• the solder ball 1916, the UBM layer 1914, and /or the first metal redistribution layer 1910 is part of an inductor in the integrated device 1900.
• the lower level metal and dielectric layers 1902 includes a capacitor.
• a capacitor is a passive capacitive means configured to store energy (e.g., store energy electrostatically in an electric field).
• the capacitor is a metal-on-metal (MOM) capacitor.
• the capacitor includes a first interconnect 1920, a second interconnect 1921, a third set of interconnect 1922, a fourth interconnect 1923, a fifth set of interconnects 1924, and a sixth interconnect 1925.
• the first interconnect 1920 is a first via.
• the second interconnect 1921 is a first trace.
• the third set of interconnect 1922 is a second set of vias.
• the fourth interconnect 1923 is a second trace.
• the fifth set of interconnects 1924 is a third set of vias.
• the sixth interconnect 1925 is a third trace.
• the first interconnect 1920, the second interconnect 1921, the third set of interconnect 1922, the fourth interconnect 1923, the fifth set of interconnects 1924, and/or the sixth interconnect 1925 are lower level metal layers in the integrated device 1900 (e.g., die).
• FIG. 20 (which includes FIGS. 20A-20D) illustrates an exemplary sequence for providing and/or fabricating an integrated device that includes a capacitor and at least part of an inductor.
• the sequence of FIGS. 20A-20D may be used to provide and/or fabricate the integrated devices of FIGS. 2-12, 18-19 and/or other integrated devices described in the present disclosure.
• Stage 1 of FIG. 20A illustrates a stage after a substrate (e.g., substrate 2001) is provided (e.g., formed, fabricated).
• the substrate is a wafer.
• Different implementations may use different materials for the substrate (e.g., silicon substrate, glass substrate).
• Stage 2 illustrates a state after several lower level metal and dielectric layers (e.g., lower level metal and dielectric layers 2002) are provided (e.g., formed, fabricated) on the substrate 2001.
• Different implementations may provide different number of lower level metal and dielectric layers (e.g., Ml metal layer, M2 metal layer, M3 metal layer, M4 metal layer, M5 metal layer, M6 metal layer, M7 metal layer).
• circuits, routes and/or interconnects are also provided in the substrate 2001 and/or the lower level metal and dielectric layers 2002.
• a capacitor 2003 is provided in the lower level metal and dielectric layers 2002.
• the capacitor 2003 is metal-insulator-metal (MIM) capacitor as shown in FIG. 18.
• the capacitor 2003 can be other types of capacitors, such as the metal-on-metal (MOM) capacitor of FIG. 19.
• Stage 3 illustrates a state after at least one pad (e.g., pad 2004) is provided (e.g., formed, fabricated) on the lower level metal and dielectric layers 2002.
• the pad is coupled to one of the lower level metal layer (e.g., the top lower level metal layer, M7 metal layer).
• the pad 2004 is an aluminum pad.
• different implementations may use different materials for the pad 2004.
• Different implementations may use different processes for providing the pad on the lower level metal and dielectric layers 2002. For example, in some implementations, a lithography and/or etching process may be use to provide the pad 2004 on the lower level metal and dielectric layers 2002.
• Stage 4 illustrates a state after a passivation layer (e.g., passivation layer 2006) is provided (e.g., formed, fabricated) on the lower level metal and dielectric layers 2002.
• a passivation layer e.g., passivation layer 2006
• Different implementations may use different materials for the passivation layer.
• the passivation layer 2006 is provided on the lower level metal and dielectric layers 2002 such that at least a portion of the pad 2004 is exposed.
• Stage 5 of FIG. 20B illustrates a state after a first insulation layer (e.g., first insulation layer 2008) is provided (e.g., formed, fabricated) on the passivation layer 2006 and the pad 2004.
• a first insulation layer e.g., first insulation layer 2008
• the first insulation layer 2008 may be a Polybenzoxazole (PbO) layer or a polymer layer.
• Stage 6 illustrates a state after a cavity (e.g., cavity 2009) is provided (e.g., formed, fabricated) in the first insulation layer 2008. As further shown in stage 6, the cavity 2009 is created over the pad 2004. Different implementations may create the cavity 2009 differently. For example, the cavity 2009 may be provided / created by etching the first insulation layer 2008.
• a cavity e.g., cavity 2009
• the cavity 2009 may be provided / created by etching the first insulation layer 2008.
• Stage 7 illustrates a state after a first metal redistribution layer is provided (e.g., formed, fabricated). Specifically, a first metal redistribution layer 2010 is provided over the pad 2004 and the first insulation layer 2008. As shown in stage 20, the first metal redistribution layer 2010 is coupled to the pad 2004. In some implementations, the first metal redistribution layer 2010 is a copper layer.
• Stage 8 of FIG. 20C illustrates a state after a second insulation layer (e.g., second insulation layer 2012) is provided (e.g., formed, fabricated) on the first insulation layer 2008 and the first metal redistribution layer 2010.
• a second insulation layer e.g., second insulation layer 2012
• the second insulation layer 2012 may be a Polybenzoxazole (PbO) layer or a polymer layer.
• Stage 9 illustrates a state after a cavity (e.g., cavity 2013) is provided (e.g., formed, fabricated) in the second insulation layer 2012.
• a cavity e.g., cavity 2013
• Different implementations may create the cavity 2013 differently.
• the cavity 2013 may be provided / created by etching the second insulation layer 2012.
• Stage 10 illustrates a state after an under bump metallization (UBM) layer is provided (e.g., formed, fabricated). Specifically, an under bump metallization (UBM) layer 2014 is provided in the cavity 2013 of the second insulation layer 2012. As shown at stage 21, the UBM layer 2014 is coupled to the first metal redistribution layer 2010. In some implementations, the UBM layer 2014 is a copper layer.
• UBM under bump metallization
• Stage 1 1 illustrates a state after a solder ball is provided on the UBM layer. Specifically, a solder ball 2016 is coupled to the UBM layer 2014. In some implementations, the solder ball 2016, the UBM layer 2014, and/or the first metal redistribution layer 2010 is part of an inductor in the integrated device.
• FIG. 21 illustrates an exemplary flow diagram of a method for providing and/or fabricating an integrated device that includes a capacitor.
• the flow diagram of FIG. 21 may be used to provide and/or fabricate the integrated devices of FIGS. 2, 6 or other integrated devices described in the present disclosure.
• the method provides (at 2105) a substrate.
• providing (at 2105) the substrate includes providing a wafer (e.g., silicon wafer).
• a wafer e.g., silicon wafer
• different implementations may use different materials for the substrate (e.g., glass substrate).
• the method then optionally provides (at 21 10) a capacitor (e.g., MIM capacitor, MOM capacitor) in lower level metal layers.
• a capacitor e.g., MIM capacitor, MOM capacitor
• the method further provides (at 21 15) at least one pad on one of the lower level metal and dielectric layers (e.g., M7 metal layer).
• providing (at 21 15) the pad includes coupling the pad to one of the lower level metal layer (e.g., the top lower level metal layer, M7 metal layer).
• the pad is an aluminum pad.
• different implementations may use different materials for the pad.
• different implementations may use different processes for providing the pad on the lower level metal and dielectric layers. For example, in some implementations, a lithography and/or etching process may be use to provide (at 2115) the pad on the lower level metal and dielectric layers.
• the method provides (at 2120) a passivation layer (e.g., passivation layer 2306), a first insulation layer (e.g., first insulation layer 2308), a redistribution layer (e.g., redistribution layer 2310), and a second insulation layer (e.g., second insulation layer 2312).
• a passivation layer e.g., passivation layer 2306
• a first insulation layer e.g., first insulation layer 2308
• a redistribution layer e.g., redistribution layer 2310
• second insulation layer e.g., second insulation layer 2312
• Different implementations may use different materials for the passivation layer.
• the passivation layer is provided on the lower level metal and dielectric layers such that at least a portion of the pad is exposed.
• the metal redistribution layer is provided over the pad and the first insulation layer.
• the metal redistribution layer is coupled to the pad.
• the metal redistribution layer is a copper
• the first and second insulation layers may be a Polybenzoxazole (PbO) layer and/or a polymer layer.
• PbO Polybenzoxazole
• the method then provides (at 2125) an under bump metallization (UBM) layer.
• UBM under bump metallization
• providing (at 2125) the UBM layer includes coupling the UBM layer to the metal redistribution layer.
• the UBM layer is a copper layer.
• the method further provides (at 2135) a solder ball on the UBM layer.
• Different implementations may use different processes to form and/or fabricate the metal layers (e.g., redistribution layer, under bump metallization layer, protrusion).
• these processes include a semi-additive patterning (SAP) process and a damascene process.
• FIG. 22 illustrates a sequence for forming an interconnect using a semi- additive patterning (SAP) process to provide and/or form an interconnect (e.g., redistribution layer, under bump metallization layer, protrusion) in one or more dielectric layer(s).
• SAP semi- additive patterning
• stage 1 illustrates a state of an integrated device (e.g., substrate) after a dielectric layer 2202 is provided (e.g., formed).
• stage 1 illustrates that the dielectric layer 2202 includes a first metal layer 2204.
• the first metal layer 2204 is a seed layer in some implementations.
• the first metal layer 2204 may be provided (e.g., formed) on the dielectric layer 2202 after the dielectric layer 2202 is provided (e.g., received or formed). Stage 1 illustrates that the first metal layer 2204 is provided (e.g., formed) on a first surface of the dielectric layer 2202. In some implementations, the first metal layer 2204 is provided by using a deposition process (e.g., PVD, CVD, plating process).
• a deposition process e.g., PVD, CVD, plating process.
• Stage 2 illustrates a state of the integrated device after a photo resist layer 2206 (e.g., photo develop resist layer) is selectively provided (e.g., formed) on the first metal layer 2204.
• selectively providing the resist layer 2206 includes providing a resist layer 2206 on the first metal layer 2204 and selectively removing portions of the resist layer 2206 by developing (e.g., using a development process).
• Stage 2 illustrates that the resist layer 2206 is provided such that a cavity 2208 is formed.
• Stage 3 illustrates a state of the integrated device after a second metal layer 2210 is formed in the cavity 2208.
• the second metal layer 2210 is formed over an exposed portion of the first metal layer 2204.
• the second metal layer 2210 is provided by using a deposition process (e.g., plating process).
• Stage 4 illustrates a state of the integrated device after the resist layer 2206 is removed. Different implementations may use different processes for removing the resist layer 2206.
• Stage 5 illustrates a state of the integrated device after portions of the first metal layer 2204 are selectively removed. In some implementations, one or more portions of the first metal layer 2204 that is not covered by the second metal layer 2210 is removed. As shown in stage 5, the remaining first metal layer 2204 and the second metal layer 2210 may form and/or define an interconnect 2212 (e.g., trace, vias, pads) in an integrated device and/or a substrate.
• an interconnect 2212 e.g., trace, vias, pads
• the first metal layer 2206 is removed such that a dimension (e.g., length, width) of the first metal layer 2204 underneath the second metal layer 2210 is smaller than a dimension (e.g., length, width) of the second metal layer 2210, which can result in an undercut, as shown at stage 5 of FIG. 22.
• the above mentioned processes may be iterated several times to provide and/or form several interconnects in one or more dielectric layers of an integrated device and/or substrate.
• FIG. 23 illustrates a flow diagram for a method for using a (SAP) process to provide and/or form an interconnect (e.g., redistribution layer, under bump metallization layer, protrusion) in one or more dielectric layer(s).
• the method provides (at 2305) a dielectric layer (e.g., dielectric layer 2202).
• a dielectric layer e.g., dielectric layer 2202.
• providing the dielectric layer includes forming the dielectric layer.
• providing the dielectric layer includes forming a first metal layer (e.g., first metal layer 2204).
• the first metal layer is a seed layer in some implementations.
• the first metal layer may be provided (e.g., formed) on the dielectric layer after the dielectric layer is provided (e.g., received or formed).
• the first metal layer is provided by using a deposition process (e.g., physical vapor deposition (PVD) or plating process).
• PVD physical vapor deposition
• the method selectively provides (at 2310) a photo resist layer (e.g., a photo develop resist layer 2206) on the first metal layer.
• a photo resist layer e.g., a photo develop resist layer 2206
• selectively providing the resist layer includes providing a first resist layer on the first metal layer and selectively removing portions of the resist layer (which provides one or more cavities).
• the method then provides (at 2315) a second metal layer (e.g., second metal layer 2210) in the cavity of the photo resist layer.
• a second metal layer e.g., second metal layer 2210 in the cavity of the photo resist layer.
• the second metal layer is formed over an exposed portion of the first metal layer.
• the second metal layer is provided by using a deposition process (e.g., plating process).
• the method further removes (at 2320) the resist layer. Different implementations may use different processes for removing the resist layer. The method also selectively removes (at 2325) portions of the first metal layer. In some implementations, one or more portions of the first metal layer that is not covered by the second metal layer are removed. In some implementations, any remaining first metal layer and second metal layer may form and/or define one or more interconnects (e.g., trace, vias, pads) in an integrated device and/or a substrate. In some implementations, the above mentioned method may be iterated several times to provide and/or form several interconnects in one or more dielectric layers of an integrated device and/or substrate.
• interconnects e.g., trace, vias, pads
• FIG. 24 illustrates a sequence for forming an interconnect using a damascene process to provide and/or form an interconnect (e.g., redistribution layer, under bump metallization layer, protrusion) in a dielectric layer.
• stage 1 illustrates a state of an integrated device after a dielectric layer 2402 is provided (e.g., formed).
• the dielectric layer 2402 is an inorganic layer (e.g., inorganic film).
• Stage 2 illustrates a state of an integrated device after a cavity 2404 is formed in the dielectric layer 2402.
• Different implementations may use different processes for providing the cavity 2404 in the dielectric layer 2402.
• Stage 3 illustrates a state of an integrated device after a first metal layer 2406 is provided on the dielectric layer 2402.
• the first metal layer 2406 provided on a first surface of the dielectric later 2402.
• the first metal layer 2406 is provided on the dielectric layer 2402 such that the first metal layer 2406 takes the contour of the dielectric layer 2402 including the contour of the cavity 2404.
• the first metal layer 2406 is a seed layer in some implementations.
• the first metal layer 2406 is provided by using a deposition process (e.g., physical vapor deposition (PVD), Chemical Vapor Deposition (CVP) or plating process).
• PVD physical vapor deposition
• CVP Chemical Vapor Deposition
• Stage 4 illustrates a state of the integrated device after a second metal layer 2408 is formed in the cavity 2404 and a surface of the dielectric layer 2402.
• the second metal layer 2408 is formed over an exposed portion of the first metal layer 2406.
• the second metal layer 2408 is provided by using a deposition process (e.g., plating process).
• Stage 5 illustrates a state of the integrated device after the portions of the second metal layer 2408 and portions of the first metal layer 2406 are removed.
• Different implementations may use different processes for removing the second metal layer 2408 and the first metal layer 2406.
• CMP chemical mechanical planazation
• the remaining first metal layer 2406 and the second metal layer 2408 may form and/or define an interconnect 2412 (e.g., trace, vias, pads) in an integrated device and/or a substrate.
• the interconnect 2412 is formed in such a way that the first metal layer 2406 is formed on the base portion and the side portion(s) of the second metal layer 2410.
• the cavity 2404 may include a combination of trenches and/or holes in two levels of dielectrics so that via and interconnects (e.g., metal traces) may be formed in a single deposition step,
• via and interconnects e.g., metal traces
• the above mentioned processes may be iterated several times to provide and/or form several interconnects in one or more dielectric layers of an integrated device and/or substrate.
• FIG. 25 illustrates a flow diagram of a method for forming an interconnect using a damascene process to provide and/or form an interconnect (e.g., redistribution layer, under bump metallization layer, protrusion) in a dielectric layer.
• the method provides (at 2505) a dielectric layer (e.g., dielectric layer 2402).
• a dielectric layer e.g., dielectric layer 2402.
• providing a dielectric layer includes forming a dielectric layer.
• providing a dielectric layer includes receiving a dielectric layer from a supplier.
• the dielectric layer is an inorganic layer (e.g., inorganic film).
• the method forms (at 2510) at least one cavity (e.g., cavity 2404) in the dielectric layer.
• at least one cavity e.g., cavity 2404
• Different implementations may use different processes for providing the cavity in the dielectric layer.
• the method provides (at 2515) a first metal layer (e.g., first metal layer 2406) on the dielectric layer.
• the first metal layer is provided (e.g., formed) on a first surface of the dielectric later.
• the first metal layer is provided on the dielectric layer such that the first metal layer takes the contour of the dielectric layer including the contour of the cavity.
• the first metal layer is a seed layer in some implementations.
• the first metal layer 2406 is provided by using a deposition process (e.g., PVD, CVD or plating process).
• the method provides (at 2520) a second metal layer (e.g., second metal layer 2408) in the cavity and a surface of the dielectric layer.
• the second metal layer is formed over an exposed portion of the first metal layer.
• the second metal layer is provided by using a deposition process (e.g., plating process).
• the second metal layer is similar or identical to the first metal layer.
• the second metal layer is different than the first metal layer.
• the method then removes (at 2525) portions of the second metal layer and portions of the first metal layer.
• Different implementations may use different processes for removing the second metal layer and the first metal layer.
• CMP chemical mechanical planazation
• the remaining first metal layer and the second metal layer may form and/or define an interconnect (e.g., interconnect 2412).
• an interconnect may include one of at least a trace, a via, and/or a pad) in an integrated device and/or a substrate.
• the interconnect is formed in such a way that the first metal layer is formed on the base portion and the side portion(s) of the second metal layer.
• the above mentioned method may be iterated several times to provide and/or form several interconnects in one or more dielectric layers of an integrated device and/or substrate.
• FIG. 26 illustrates various electronic devices that may be integrated with any of the aforementioned integrated device, semiconductor device, integrated circuit, die, interposer or package.
• a mobile telephone 2602, a laptop computer 2604, and a fixed location terminal 2606 may include an integrated device 2600 as described herein.
• the integrated device 2600 may be, for example, any of the integrated circuits, substrates, dies, package or package-on-package (PoP) devices described herein.
• PoP package-on-package
• the devices 2602, 2604, 2606 illustrated in FIG. 26 are merely exemplary.
• Other electronic devices may also feature the integrated device 2600 including, but not limited to, mobile devices, hand-held personal communication systems (PCS) units, portable data units such as personal digital assistants, GPS enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communications devices, smartphones, tablet computers or any other device that stores or retrieves data or computer instructions, or any combination thereof.
• PCS personal communication systems
• portable data units such as personal digital assistants
• GPS enabled devices GPS enabled devices
• navigation devices set top boxes
• music players, video players, entertainment units set top boxes
• fixed location data units such as meter reading equipment
• communications devices smartphones, tablet computers or any other device that stores or retrieves data or computer instructions, or any combination thereof.
• FIGS. 2, 3, 4, 5, 6, 7, 8, 9, 10, 1 1, 12, 13, 14, 15, 16, 17, 18, 19, 20A-20D, 21, 22, 23, 24, 25, and/or 26 may be rearranged and/or combined into a single component, step, feature or function or embodied in several components, steps, or functions. Additional elements, components, steps, and/or functions may also be added without departing from the disclosure. It should also be noted that FIGS. 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20A-20D, 21, 22, 23, 24, 25, and/or 26 and its corresponding description in the present disclosure is not limited to dies and/or ICs. In some implementations, FIGS.
• an integrated device may include a die package, an integrated circuit (IC), a wafer, a semiconductor device, substrate and/or an interposer.
• IC integrated circuit
• the embodiments may be described as a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed.

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