EP3055946A1 - Dispositif, amplificateur et procédé de traitement des signaux - Google Patents

Dispositif, amplificateur et procédé de traitement des signaux

Info

Publication number
EP3055946A1
EP3055946A1 EP14852491.1A EP14852491A EP3055946A1 EP 3055946 A1 EP3055946 A1 EP 3055946A1 EP 14852491 A EP14852491 A EP 14852491A EP 3055946 A1 EP3055946 A1 EP 3055946A1
Authority
EP
European Patent Office
Prior art keywords
gain
delay
mixer
drain
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP14852491.1A
Other languages
German (de)
English (en)
Other versions
EP3055946A4 (fr
EP3055946B1 (fr
Inventor
Alyssa Apsel
Alyosha Molnar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cornell University
Original Assignee
Cornell University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cornell University filed Critical Cornell University
Publication of EP3055946A1 publication Critical patent/EP3055946A1/fr
Publication of EP3055946A4 publication Critical patent/EP3055946A4/fr
Application granted granted Critical
Publication of EP3055946B1 publication Critical patent/EP3055946B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • H04B1/50—Circuits using different frequencies for the two directions of communication
    • H04B1/52—Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H04B1/0475—Circuits with means for limiting noise, interference or distortion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/14—Two-way operation using the same type of signal, i.e. duplex
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/75—Indexing scheme relating to amplifiers the amplifier stage being a common source configuration MOSFET

Definitions

  • the disclosure relates to radio frequency signal processing devices, and more particularly to diplexers for radio frequency signals.
  • Radio Frequency (“RF”) duplexers and diplexers are great assets in these systems, as they allow bidirectional communication either on the same band or over adjacent bands over the same path, enabling a transmitter and a receiver to share an antenna while transceiver communicating with minimal round-trip latency.
  • Duplexers and diplexers preferably isolate the transmitter and receiver such that the receiver and transmitter do not load each other, the noise from the transmitter does not corrupt the receive signal, and the receiver is not desensitized (or damaged) by the high-power transmitted signal.
  • An advantageous RF front would be fully integrated on chip with a single antenna port, would support simultaneous reception and transmission of RF signals, and would provide significant flexibility (i.e., multiple octaves) in center frequency and bandwidth of both receiver and transmitter.
  • An active duplexer circuit capable of significant signal and noise isolation was demonstrated, however, the transmit power was limited to only 10's of microwatts.
  • a truly useful system should meet these same requirements of isolation, integration and flexibility, while transmitting four orders of magnitude more power. No such system exists today.
  • An active electronic circuit that enables bidirectional communication over a single antenna or path is disclosed.
  • the disclosed circuit has a topology similar to that of a distributed amplifier, but provides tunable gain cells.
  • the forward path through the amplifier offers high gain.
  • the reverse path, from input to the receiver port can be configured as an finite impulse response (“FIR") filter by programming the gain cells to represent the weights of the filter, while LC sections of input and output lines implement the delay or sampling time of the filter.
  • the circuit also provides for tuning of the output resistance using passive mixers.
  • Embodiments of the disclosure enable wideband RF duplexing using a circuit that may be realized in an integrated fashion.
  • the circuit effectively isolates a high-power RF transmitted signal from a co-integrated receiver, allowing the two circuits to share the same antenna and the same frequency band without interfering with each other.
  • the receiver is able to handle the transmitter power and is not affected by TX noise because it is placed on a port where the signal from the TX is effectively filtered by the circuit's FIR filter behavior. This advantageously enables a radio to communicate continuously and bi-directionally, with frequencies across octaves, using a single antenna— typically an expensive and physically large portion of a radio transceiver system.
  • Embodiments of the present disclosure can advantageously:
  • the disclosure may be embodied as a distributed signal processing device.
  • the signal processing device comprises a plurality of gain cells, each gain cell has an input and an output. Each gain cell amplifies an electrical signal received at the input by a reconfigurable gain
  • the device has a plurality of bi-directional drain delay cells, each drain delay cell having a first terminal and a second terminal.
  • the drain delay cells are configured to delay an electrical signal between the first terminal and second terminal by a reconfigurable delay.
  • each drain delay cell contains an inductor.
  • the drain delay cells are arranged such that each drain delay cell is between the outputs of two gain cells, thereby forming a drain line.
  • the device has a plurality of gate delay cells, each gate delay cell having an input terminal, configured to receive a transmit signal, and an output terminal connected to the input of a corresponding gain cell.
  • the gate delay cells are configured to delay an electrical signal between the input terminal and output terminal by a reconfigurable delay.
  • the device comprises a controller configured to determine a transfer function of the device, and reconfigure the gain of the gain cells and/or the delay of the drain and/or gate delay cells according to the determined transfer function.
  • Figure 1 is a signal processing device according to an embodiment of the present disclosure
  • Figure 2 is a signal processing device according to another embodiment of the present
  • Figure 3 A is a graph depicting the transmit efficiency of a modelled device configured for nulling at the receiver port
  • Figure 3B is a graph depicting the power amplifier output (gain cell output) for a six stage amplifier assuming ideal (perfect in precision) weights from 500 MHz to 3 GHz;
  • Figure 4 is a signal processing device showing a detail view of an exemplary gain cell
  • Figure 5 is an RF amplifier according to another embodiment of the present disclosure
  • Figure 6 is a set of graphs depicting the operation of an embodiment of a gain cell wherein source degeneration is provided, in part, by a passive mixer capacitively coupled to a low voltage source;
  • Figure 7 is a diagram depicting an exemplary gate delay cell(s) and gain cells
  • Figure 8 is a model of an exemplary device according to the present disclosure.
  • Figure 9 is a flowchart depicting a method according to an embodiment of the present
  • the present disclosure provides a signal processing device 10 that enables bidirectional communication over a single antenna 90 or path.
  • the circuit is based upon a distributed amplifier topology with tunable gain cells 20.
  • the forward path through this amplifier (from input (port 1) to output (port 3)) can be configured with high gain and is similar to a typical distributed amplifier in performance.
  • an input line 12 is constructed as a transmission line or artificial transmission line.
  • the sections between gain cells 20 act as delays 30 by providing some electromagnetic path length at frequencies comparable to the input signal. These signals see another delay 40 on the output transmission line and can be configured to add up in phase when the sum of the delays 30, 40 on each path through each gain cell 20 is equal.
  • a matched antenna can be connected to port 3 for transmission of the amplified signal.
  • This can be configured as an finite impulse response (“FIR”) filter by programming the gain of each gain cell 20 to represent the weights of the filter.
  • the LC sections of the input and output lines represent the delay or sampling time of the filter.
  • Tx transmit
  • Rx receive
  • a and ⁇ can be defined for each stage, thereby tuning the transfer characteristic from port 1 to port 2 to notch out the transmit signal across a range of frequencies.
  • both output power summation and notching can be maintained simultaneously, isolating port 2 from the output on port 3.
  • configuring weights for both notch and summation may slightly degrade efficiency compared to focusing only on output power.
  • a tunable, interference-resistant receiver can then be used to realize full tunability of both Tx and Rx for cognitive radio and software defined radio (“SDR”) applications.
  • the circuit can be further enhanced by utilizing a technique for tuning the output resistance based on passive mixers (further described below under the heading "Source
  • Such a realization of the gain cell 20 is advantageous to reduce the noise from the Tx from propagating to the Rx. Furthermore, it enables the shunt impedance of the circuit between ports 3 and 2 to be high at the Rx frequency of interest, reducing loss.
  • the disclosure may be embodied as a distributed signal processing device 10.
  • Such a signal processing device 10 may be used as a diplexed transceiver.
  • the signal processing device 10 comprises a plurality of gain cells 20.
  • Each gain cell 20 has an input 22 and an output 24, and the gain cell 20 amplifies an electrical signal received at the input 22 by a gain A.
  • the gain is selectable (i.e., reconfigurable) according to the frequency of interest. In this way, if the frequency of interest is changed (i.e., the transmit and/or receive frequency), the gain of the gain cells 20 can be reconfigured.
  • the gain cells 20 may have the same gain, or one or more gain cells 20 may have different gain(s) than those of the other gain cells 20.
  • the device 10 has a plurality of bi-directional drain delay cells 40.
  • Each drain delay cell 40 has a first terminal 42 and a second terminal 44.
  • the drain delay cells 40 are configured to delay an electrical signal between the first terminal 42 and second terminal 44. It should be noted that the drain delay cells 40 are bi-directional such that an electrical signal received at the first terminal 42 may be delayed to the second terminal 44, and an electrical signal received at the second terminal 44 may be delayed to the first terminal 42.
  • the delay may be fixed. In other embodiments, the delay is selectable (i.e., reconfigurable) according to a frequency of interest. In this way, if the frequency of interest is changed, the delay of the drain delay cells 40 can be reconfigured.
  • the drain delay cells 40 may have the same delay as each other.
  • one or more drain delay cells 40 may have different delay(s) than those of the other drain delay cells 40.
  • the drain delay cells 40 have an inductance and a capacitance.
  • each drain delay cell 40 may contain an inductor 46.
  • each drain delay cell 40 may be configured as an inductor-capacitor pi- network having one or more stages.
  • each drain delay cell 40 is between the outputs 24 of two gain cells 20.
  • the first terminal 42 of each drain delay cell 40 is connected to the output 24 of a gain cell 20, and the second terminal 44 of each drain delay cell 40 is connected to the output 24 of an adjacent gain cell 20.
  • the drain delay cells 40 may form a string, which can be considered a drain line 14 having an antenna end 15 (i.e., port 3) and a receiver end 13 (i.e., port 2).
  • the device 10 has a plurality of gate delay cells 30.
  • Each gate delay cell 30 has an input terminal 32 and an output terminal 34.
  • the input terminal 32 of each gate delay cell 30 is configured to receive a transmit signal.
  • the gate delay cells 30 are arranged such that the output terminal 34 of each drain delay cell 30 is connected to the input 22 of a corresponding gain cell 20.
  • the gate delay cells 30 are configured to delay an electrical signal between the input terminal 32 and output terminal 34 by a delay.
  • the delay is selectable (i.e., reconfigurable) according to a frequency of interest. In this way, if the frequency of interest is changed, the delay of the gate delay cells 30 can be reconfigured.
  • the gate delay cells 30 may have the same delay as each other.
  • one or more gate delay cells 30 may have different delay(s) than those of the other gate delay cells 30.
  • Each gate delay cell 30 may have the same delay as a corresponding drain delay cell 40.
  • the delays of the gate delay cells 30 may be different than the delays of the drain delay cells 40.
  • the device 10 may include a first gate delay cell 31 at the transmit end 11 (port 1).
  • a first drain delay cell 41 can be used to provide the corresponding delay on the drain line 14.
  • the gate delay cells 30 are arranged such that each gate delay cell 30 is between the inputs 22 of two gain cells 20.
  • the input terminal 32 of each gate delay cell 30 is connected to the input 22 of a gain cell 20, and the output terminal 34 of each gate delay cell 30 is connected to the input 22 of an adjacent gain cell 20.
  • the gate delay cells 30 may form a string, which can be considered a gate line 12 having a transmitter end 11 (i.e., port 1).
  • a gate delay cell 80 comprises an up-conversion mixer 82.
  • Each up-conversion mixer 82 is configured to receive a local oscillator ("Tx LO") signal.
  • Each up-conversion mixer 82 receives a baseband Tx signal (“TxBB”) on the input terminal 84 and is configured to up-convert the baseband signal using the Tx LO signal.
  • TxBB baseband Tx signal
  • the resulting up-converted signal is provided at the corresponding output terminal 86.
  • the Tx signal is phase-shifted to effect the delay of the gate delay cells 80.
  • the up-converted Tx signal output from a second gate delay cell 20 is phase-delayed relative to the up-converted Tx signal output from a first gate delay cell 20, and so on.
  • delay should be broadly interpreted to include time delay and/or phase delay.
  • An exemplary gate delay cell is configured to provide a phase delay on the incoming transmit signal (see, e.g., Fig. 7).
  • a gate delay cell may comprise a quadrature phase rotator followed by a quadrature mixer for up-conversion of the transmit signal.
  • the transmit mixer may be an 8-phase mixer configured to suppress 3 rd and 5 th harmonic
  • the baseband transmit signal comprises two independent signals, in-phase and quadrature (/ and Q), representing the real and imaginary parts of the desired transmit signal. These are converted to a single high- frequency signal through quadrature up conversion, where / is converted to the cosine part of the high frequency signal, and Q is upconverted to the sine part of the upconverter signal.
  • Effective phase rotation can be realized by appropriately adding a weighted version of the Q signal to the / signal, and a weighted version of the / signal (same magnitude, opposite sign to the previous weight) to the Q signal in baseband before up- conversion.
  • the device 10 comprises a controller 18 configured to determine a transfer function of the device 10.
  • the controller 18 is configured to automatically set the gain(s) of each gain cell 20 and/or the delay(s) of the gate and drain delay cells 30, 40 based on the transfer function of the device 10 based on a transmit signal applied at port 1.
  • the controller 18 may be configured to select the gain(s) and or the delay(s) such that the amplified signals from each gain cell 20 are substantially nulled at the receiver end 13 of the drain line 14.
  • the controller 18 is configured to optimize amplification at the antenna end 15, the null at the receiver end 13, and/or the power consumed by the device 10, 70. This is further described below under the heading "Exemplary Controller Optimization.”
  • the Tx signal should be low enough such that a receiver at the receiver end 13 is not degraded by the Tx signal.
  • the Tx signal is nulled by 20 dB, 30 dB, 40 dB or more.
  • noise may also be a consideration in the Rx signal at the receiver end 13.
  • Rx-band noise reduction may be 20 dB, 30 dB, 40 dB, or more. Therefore, signals are nulled to a level whereby, in view of the amplified Tx signals from the gain cells 20 and Rx band noise of the device, a useable Rx signal is provided at the receiving end 13.
  • controller 18 is depicted as being in electrical communication with the receiver end 13, it should be understood that controller 18 may further (or alternatively) be connected at one or more other locations of the device 10, 70 dictated only be the desired control result. For example, where amplification at the antenna end 15 is to be maximized, the controller 18 may be in electrical communication with the antenna end 15. In another example, where power utilization is to be reduced, the controller 18 may be configured to measure the power consumed by one or more components, such as, for example, the gain cells 20.
  • each gain cell 100 comprises a cascode 101.
  • each gain cell 100 comprises a common source amplifier 110 containing a cascode device 120.
  • Each of the cascaded common source amplifiers 110 has an input gate, a source, and a drain line output.
  • the amplifiers may be transistors, such as n-channel MOSFETs.
  • the gate 112 of the common source amplifier 110 is in electrical communication with the input terminal 102 of the gate cell 100.
  • the source 114 of the common source amplifier 110 is in electrical communication with a low supply voltage (e.g., ground).
  • the drain 116 of the common source amplifier 110 is in electrical communication with the source 124 of the cascode device 120.
  • the drain 126 of the cascode amplifier 120 makes up the output terminal 104 of the gate cell 100.
  • the gate 122 of the cascode 120 is connected to a bias voltage— the cascode voltage ( casc ).
  • the cascodes 120 are arranged in series such that the drain of a first 120 is connected to a source of an adjacent device 120.
  • the cascode voltage of each stage is selected to distribute a drain voltage swing across the common source amplifier 110 and cascode device 120 of the cascode amplifier.
  • the cascode voltage of each stacked stage can be selected to distribute the voltage across each amplifier to prevent a transistor from exceeding a breakdown voltage.
  • the source 112 of the common source amplifier 110 is connected to the low supply voltage by an inductor 130 to provide inductive source
  • the source 112 of the common source amplifier 110 is further coupled to a passive mixer 140 having a plurality of baseband mixer ports 142
  • each baseband mixer port 142 is coupled to the low supply voltage by a corresponding capacitor 144.
  • the passive mixer 140 is configured to downconvert a signal received from the common source
  • Each of the baseband signals has a predetermined phase of a plurality of predetermined phases. Because of the capacitive coupling on the baseband ports, only signals close the switching frequency of the mixer 140 (or harmonics thereof) generate significant baseband voltages. The baseband voltages are inherently re-up-converted to the RF port of the mixer 140, presenting an inherently high impedance close to the switching frequency. Because signals at frequencies distant from the switching frequency do not generate significant baseband voltage, these signals experience a low impedance on the RF port of the mixer.
  • Each passive mixer 140 can be configured to have a switching frequency that is the same as a receiver frequency and/or different from a transmitter frequency.
  • PPM pulse-position modulation
  • Such an embodiment effectively utilizes pulse-position modulation ("PPM") of the Rx signal for degeneration for the gain cell 100.
  • PPM pulse-position modulation
  • a tunable degeneration peak is provided in each gain cell 100, wherein the peak is tuned to the center of the receive band.
  • this arrangement may prevent very tight spacing of receive and transmit frequency, it would reduce degradation of the receiver path by noise and loading from the transmitter amplifier stages.
  • increased degeneration impedance on a common source amplifier reduces its gain.
  • the high impedance of the passive mixer at the receive frequency will tend to suppress receive-band noise on the gate of the common source amplifier from reaching its output (drain).
  • output noise generated by the amplifier itself is reduced with increased degeneration impedance, receive-band noise of the amplifier itself will be suppressed.
  • the passive mixer 140 will cause the amplifier to have a higher output impedance in the receive band.
  • the passive mixer 140 can also inject noise due to reciprocal mixing of its local oscillator phase noise by the transmitter signal, as shown in Fig., 6. However, this noise will be mostly correlated across amplifiers, and so may be suppressed at the receiver port in a similar fashion to transmitted signal itself.
  • a device is modeled as having N+1 nodes, each with a power amplifier current (I), a shunt resistor (3 ⁇ 4,), and a shunt capacitor (C) (see Fig. 8).
  • the nodes are coupled by inductors (L) with finite Q (modelled as series R).
  • KCL K-cosine
  • nulling of Rx-band phase noise can be determined by defining X
  • co-optimization can also be framed as a convex optimization problem, where the controller may determine parameters to minimize three squared errors and current squared:
  • the present disclosure may be embodied as a method 200 for automatic configuration of a signal processing device (see, e.g., Fig. 9).
  • the method 200 comprises the step of providing 203 a device having a transmitter port, a receiver port, an antenna port, and a controller.
  • a signal, received at the transmitter port, is separated 206 into phase-shifted signals.
  • the signal may be separated using a quadrature phase rotator as described above. Other ways of separating the signal will be apparent in light of the present disclosure.
  • Each of the separated signals is amplified 209.
  • the signals are amplified 209 by an initial gain.
  • the amplified signals are delayed 212 such that the amplified signals are summed at the antenna port.
  • the initial gain and/or the initial phase shift may be predetermined.
  • the controller determines 215 a transfer function of the device. For example, the controller may determine 215 a transfer function from the transmitter port to the receiver port. In other embodiments, the controller may determine a transfer function from the transmitter port to the antenna port. Other transfer functions may be determined according to the design parameters of a particular device. More than one transfer function may be determined 215.
  • the controller may determine 215 a transfer function by measuring a signal at one or more points of the device. For example, the controller may measure a signal at the receiver port and a signal at the antenna port. The controller automatically alters 218 the initial gain and/or the initial phase shift of the signal according to the determined transfer function.
  • the controller may alter 218 the gain and/or the phase shift such that the signals substantially null at the receiver port. In some embodiments, the controller may alter 218 the gain and/or the phase shift such that the signals provide a desired amplification at the antenna port.
  • the controller may measure 221 the power consumption of one or more components of the device.
  • the controller can alter 224 the gain and/or phase shift to reduce power consumption of the device (e.g., increase efficiency). In this way, the transfer functions and power consumption may be optimized for a particular device and signal.

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
  • Transceivers (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)

Abstract

La présente invention concerne un dispositif électronique actif qui active la communication bidirectionnelle sur une antenne ou une voie unique. Le dispositif peut être caractérisé par une voie vers l'avant (à partir d'une entrée vers un port d'antenne) offrant un gain élevé et une voie inverse (vers un port du récepteur) qui peut être conçue comme un filtre à réponse finie à une impulsion (« FIR »). L'invention concerne un amplificateur du dispositif, l'amplificateur permettant d'accorder la résistance de sortie au moyen de mélangeurs passifs.
EP14852491.1A 2013-10-11 2014-10-14 Dispositif, amplificateur et procédé de traitement des signaux Active EP3055946B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201361890022P 2013-10-11 2013-10-11
PCT/US2014/060531 WO2015054699A1 (fr) 2013-10-11 2014-10-14 Dispositif, amplificateur et procédé de traitement des signaux

Publications (3)

Publication Number Publication Date
EP3055946A1 true EP3055946A1 (fr) 2016-08-17
EP3055946A4 EP3055946A4 (fr) 2017-05-24
EP3055946B1 EP3055946B1 (fr) 2022-03-16

Family

ID=52813705

Family Applications (1)

Application Number Title Priority Date Filing Date
EP14852491.1A Active EP3055946B1 (fr) 2013-10-11 2014-10-14 Dispositif, amplificateur et procédé de traitement des signaux

Country Status (4)

Country Link
US (2) US10530414B2 (fr)
EP (1) EP3055946B1 (fr)
CN (1) CN105830385B (fr)
WO (1) WO2015054699A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10530414B2 (en) 2013-10-11 2020-01-07 Cornell University Signal processing device, amplifier, and method
WO2019103898A1 (fr) * 2017-11-27 2019-05-31 Skyworks Solutions, Inc. Amplificateurs de doherty combinés en quadrature
CN110048241A (zh) * 2019-04-22 2019-07-23 湖南时变通讯科技有限公司 二维相控阵列、大规模天线阵列和发射机
US11431367B2 (en) * 2019-06-28 2022-08-30 Indian Institute Of Technology, Bombay System for cancelling interference in a full-duplex wireline communication link

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4887657B2 (ja) * 2005-04-27 2012-02-29 日本電気株式会社 アクティブマトリクス型表示装置及びその駆動方法
US8145155B2 (en) * 2005-09-06 2012-03-27 Mediatek, Inc. Passive mixer and high Q RF filter using a passive mixer
US7498883B2 (en) * 2005-10-07 2009-03-03 University Of Rochester Distributed amplifier with built-in filtering functions
FR2895150A1 (fr) 2005-12-16 2007-06-22 Thales Sa Quasi circulateur actif
US7576627B2 (en) * 2006-04-24 2009-08-18 Bradley University Electronically tunable active duplexer
US7816997B2 (en) * 2006-09-28 2010-10-19 Infineon Technologies Ag Antenna multiplexer with a Pi-network circuit and use of a Pi-network
WO2009031042A2 (fr) * 2007-04-23 2009-03-12 Dali Systems, Co., Ltd. Amplificateur de puissance distribué de type doherty à n-voies
CN102845126B (zh) 2010-02-04 2015-04-15 康奈尔大学 无线通信设备及软件无线电设备
JP5539916B2 (ja) * 2011-03-04 2014-07-02 ルネサスエレクトロニクス株式会社 半導体装置
US10530414B2 (en) 2013-10-11 2020-01-07 Cornell University Signal processing device, amplifier, and method

Also Published As

Publication number Publication date
EP3055946A4 (fr) 2017-05-24
EP3055946B1 (fr) 2022-03-16
US11546012B2 (en) 2023-01-03
CN105830385B (zh) 2019-10-29
US20160261304A1 (en) 2016-09-08
US10530414B2 (en) 2020-01-07
WO2015054699A1 (fr) 2015-04-16
US20200395974A1 (en) 2020-12-17
CN105830385A (zh) 2016-08-03

Similar Documents

Publication Publication Date Title
US11546012B2 (en) Signal processing device, amplifier, and method
US10454432B2 (en) Radio frequency amplifiers with an injection-locked oscillator driver stage and a stacked output stage
US8265571B2 (en) Circuit arrangement with improved decoupling
US9438288B2 (en) System providing reduced intermodulation distortion
US9331720B2 (en) Combined directional coupler and impedance matching circuit
US9521023B2 (en) Systems for analog phase shifting
US9425840B2 (en) Wideband tunable notch cancellation
US9853623B2 (en) High-selectivity low-loss duplexer
EP3108587B1 (fr) Circuit et procédé pour fournir une impédance réglable
JP2021520763A (ja) マルチバンドミリ波５ｇ通信のための送信及び受信スイッチ並びに広帯域電力増幅器整合ネットワーク
Kang et al. Dual-band CMOS RF front-end employing an electrical-balance duplexer and N-path LNA for IBFD and FDD radios
Yang et al. A fully integrated software-defined FDD transceiver tunable from 0.3-to-1.6 GHz
CN109478898B (zh) 可调谐匹配网络
EP3925078B1 (fr) Circuit combinateur différentiel
US20220231642A1 (en) Amplifier with switchable transformer
KR20230131467A (ko) 스위칭가능 변압기를 갖는 증폭기

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20160510

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

DAX Request for extension of the european patent (deleted)
REG Reference to a national code

Ref country code: DE

Ref legal event code: R079

Ref document number: 602014082880

Country of ref document: DE

Free format text: PREVIOUS MAIN CLASS: H04L0005060000

Ipc: H04B0001520000

A4 Supplementary search report drawn up and despatched

Effective date: 20170425

RIC1 Information provided on ipc code assigned before grant

Ipc: H04B 1/52 20150101AFI20170419BHEP

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

17Q First examination report despatched

Effective date: 20181030

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: CORNELL UNIVERSITY

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: GRANT OF PATENT IS INTENDED

INTG Intention to grant announced

Effective date: 20211007

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE PATENT HAS BEEN GRANTED

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

Ref country code: DE

Ref legal event code: R096

Ref document number: 602014082880

Country of ref document: DE

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: AT

Ref legal event code: REF

Ref document number: 1476610

Country of ref document: AT

Kind code of ref document: T

Effective date: 20220415

REG Reference to a national code

Ref country code: LT

Ref legal event code: MG9D

REG Reference to a national code

Ref country code: NL

Ref legal event code: MP

Effective date: 20220316

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220316

Ref country code: RS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220316

Ref country code: NO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220616

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220316

Ref country code: HR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220316

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220616

REG Reference to a national code

Ref country code: AT

Ref legal event code: MK05

Ref document number: 1476610

Country of ref document: AT

Kind code of ref document: T

Effective date: 20220316

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220316

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220617

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220316

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220316

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SM

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220316

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220316

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220316

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220718

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220316

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220316

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220316

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220316

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220316

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220716

Ref country code: AL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220316

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602014082880

Country of ref document: DE

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220316

26N No opposition filed

Effective date: 20221219

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220316

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220316

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

REG Reference to a national code

Ref country code: BE

Ref legal event code: MM

Effective date: 20221031

P01 Opt-out of the competence of the unified patent court (upc) registered

Effective date: 20230519

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20221014

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20221031

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220316

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20221031

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20221031

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20221014

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20231027

Year of fee payment: 10

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20231025

Year of fee payment: 10

Ref country code: DE

Payment date: 20231027

Year of fee payment: 10

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO

Effective date: 20141014

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220316

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220316