EP2974032B1 - Cna capacitif à 4n+1 niveaux utilisant n condensateurs - Google Patents

Cna capacitif à 4n+1 niveaux utilisant n condensateurs Download PDF

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EP2974032B1
EP2974032B1 EP14720287.3A EP14720287A EP2974032B1 EP 2974032 B1 EP2974032 B1 EP 2974032B1 EP 14720287 A EP14720287 A EP 14720287A EP 2974032 B1 EP2974032 B1 EP 2974032B1
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Prior art keywords
switching
charge
dac
vref
transfers
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German (de)
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EP2974032A1 (fr
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Vincent Quiquempoix
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Microchip Technology Inc
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Microchip Technology Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/80—Simultaneous conversion using weighted impedances
    • H03M1/802—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0634—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale
    • H03M1/0656—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal
    • H03M1/066—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching
    • H03M1/0665—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching using data dependent selection of the elements, e.g. data weighted averaging
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H03M3/424—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
    • H03M3/464—Details of the digital/analogue conversion in the feedback path

Definitions

  • the present disclosure relates to digital to analog converters (DAC), in particular use of such DAC in sigma delta modulators.
  • DAC digital to analog converters
  • Analog-to-digital converters are in widespread use today in electronics for consumers, industrial applications, etc.
  • analog-to-digital converters include circuitry for receiving an analog input signal and outputting a digital value proportional to the analog input signal. This digital output value is typically in the form of either a parallel word or a serial digital bit string.
  • analog-to-digital conversion schemes such as voltage-to-frequency conversion, charge redistribution, delta modulation, as well as others.
  • each of these conversion schemes has its advantages and disadvantages.
  • One type of analog-to-digital converter that has seen increasing use is the switched capacitor sigma-delta converter.
  • the switched capacitor sigma-delta converter uses a digital-to-analog converter DAC in a feedback loop as shown in Fig. 1 and cannot be more linear than the digital-to-analog converter.
  • An input signal 114 is fed to a Loop Filter 116.
  • the output signal Vin of the Loop Filter 116 is forwarded to a Quantizer 120 which provides the output bitstream 112.
  • This bitstream 112 is fed back to the DAC 114 whose output is fed back to the Loop Filter 116. Therefore a very linear digital-to-analog converter is required in order to achieve a perfectly linear analog-to-digital conversion.
  • the digital-to-analog resolution can be exchanged with the oversampling ratio at the cost of a longer conversion time.
  • a two-level digital-to-analog converter is inherently linear and thus is not the limiting factor for the accuracy of a sigma-delta converter. Therefore it is the standard approach in a sigma-delta analog-to-digital converter.
  • Such A/D converters are for example disclosed in the article " A 192ks/s Sigma-Delta ADC with integrated DecimationFilters Providing - 97..4dB THD" by Mark A. Alexander, Hessam Mohajeri, and Justin O. Prayogo in IEEE International Solid State Circuit Conference 37(1994) February, New York, US , and " Theory and Practical Implementation of a fifth-Order Sigma-Delta A/D Converter" by R. W. Adams, P.F.
  • capacitive charge transfer DACs are often used to realize the feedback of the modulator if the modulator is made of switched capacitors.
  • Multi-bit architectures have nice advantages including less quantization noise, more stability, less sensitivity to idle tones as well as better distortion behavior. Since the DAC output resides at the input of the modulator, the inaccuracies of the DAC are directly transmitted to the signal and are difficult to compensate for. Therefore, it is critical to be able to realize linear DACs with as many levels as possible (making a multi level flash ADC is easier since in a sigma delta modulator, it does not require as much accuracy as the DAC as it stands at the end of the signal chain).
  • Multi-level DAC with more than 5 levels require multiple capacitors and dynamic element matching to be able to transfer the signals in two phases (most of the sigma delta modulators based on switched capacitors have two phases one for sampling signals one for transferring signals to the next stage).
  • These multi-level DACs are typically realized as charge transfer DAC. In these type of DACs, each output level is defined by a different amount of electrical charge transferred to the output of the DAC. Thus, a charge transfer DAC is transferring charges and therefore operates differently than a voltage or current DAC.
  • multi-level DAC with more than five levels require multiple capacitors and dynamic element matching to be able to transfer the signals in two phases (most of the sigma delta modulators based on switched capacitors have two phases: one for sampling signals and one for transferring signals to the next stage).
  • the switches for each one of the plurality of second switching units are independently controlled.
  • a sigma delta modulator includes a DAC of the charge transfer type including a capacitor switch unit operable to generate a 4n+1 output levels, and a plurality of second switching units for coupling first terminals of a plurality of reference capacitor pairs with either a positive or a negative reference signal; wherein the second terminals of the plurality of reference capacitor pairs are coupled in parallel, respectively; and a first switching unit for coupling first terminals of an input capacitor pair with either a positive or a negative input signal, wherein the second terminals of the input capacitor pairs and the plurality of reference capacitor pairs are coupled in parallel, respectively; wherein for even transfers a single switching configuration is provided to achieve linearity and wherein for odd transfers an average of different switching combinations is provided to achieve linearity; wherein an odd transfer is when an input of the DAC is even and an odd transfer is when an input to the DAC is odd.
  • the modulator includes a switching network coupling the second terminals of the input and reference capacitors with a differential amplifier.
  • a digital-to-analog converter (DAC) of the charge transfer type includes a reference voltage switching arrangement comprising n individual five-level reference voltage switching arrangements in parallel; a switched capacitor stage for generating 4n+1 output voltage levels; and a switching controller, the switching controller configured to control switching configurations; wherein for even transfers a single switching configuration is provided to achieve linearity and wherein for odd transfers an average of different switching combinations is provided to achieve linearity; wherein an even transfer is when an input of the DAC is even and an odd transfer is when an input to the DAC is odd.
  • the switching controller configured to aperiodically select an order of transfers for odd transfers.
  • a digital-to-analog converter (DAC) of the charge transfer type in accordance with embodiments includes a switched capacitor stage for generating a plurality of output voltages; a reference voltage switching arrangement comprising n individual five-level reference voltage switching arrangements in parallel; and a switching controller operable to control the switched capacitor stage and the reference voltage switching arrangement to generate switching patterns for each of the plurality of output voltages, wherein each pattern comprises a charge phase and a transfer phase; wherein for even transfers a single switching configuration is provided to achieve linearity and wherein for odd transfers an average of different switching combinations is provided to achieve linearity; wherein an even transfer is when an input of the DAC is even and an odd transfer is when an input to the DAC is odd.
  • the switched capacitor stage is configured to generate 4n+1 output levels.
  • the switching controller is configured to control a same number of transfers over each of the n individual five-level reference voltage switching arrangements for VREF and -VREF, where VREF and -VREF are reference voltage inputs to the n individual five level reference voltage switching arrangements. In some embodiments, for odd transfers a randomization of an order of sequences in the transfers is affected.
  • a method for producing a digital-to-analog converter (DAC) of the charge transfer type includes providing a switched capacitor stage for generating a plurality of output voltages; providing a reference voltage switching arrangement comprising n individual five-level reference voltage switching arrangements in parallel; and providing a switching controller operable to control the switched capacitor stage and the reference voltage switching arrangement to generate switching patterns for each of the plurality of output voltages, wherein each pattern comprises a charge phase and a transfer phase; wherein for even transfers a single switching configuration is provided to achieve linearity and wherein for odd transfers an average of different switching combinations is provided to achieve linearity; wherein an even transfer is when an input of the DAC is even and an odd transfer is when an input to the DAC is odd.
  • the switched capacitor stage is configured to generate 4n+1 output levels.
  • the switching controller configured to control a same number of transfers over each of the n individual five-level reference voltage switching arrangements for VREF and -VREF, where VREF and -VREF are reference voltage inputs to the n individual five level reference voltage switching arrangements. In some embodiments, for odd transfers a randomization of an order of sequences in the transfers is affected.
  • a method for operating a digital-to-analog converter (DAC) of the charge transfer type includes generating a plurality of output voltages with a switched capacitor stage; generating reference voltages using a reference voltage switching arrangement comprising n individual five-level reference voltage switching arrangements in parallel; and controlling the switched capacitor stage and the reference voltage switching arrangement to generate switching patterns for each of the plurality of output voltages, wherein each pattern comprises a charge phase and a transfer phase; wherein for even transfers a single switching configuration is implemented to achieve linearity and wherein for odd transfers an average of different switching combinations is implemented to achieve linearity; wherein an even transfer is when an input of the DAC is even and an odd transfer is when an input to the DAC is odd.
  • the switched capacitor stage is configured to generate 4n+1 output levels.
  • the method includes controlling a same number of transfers over each of the n individual five-level reference voltage switching arrangements for VREF and -VREF, where VREF and -VREF are reference voltage inputs to the n individual five level reference voltage switching arrangements.
  • the method includes randomizing of an order of sequences in the transfers for odd transfers.
  • ADC analog-to-digital converter
  • a multi-level (nlev) sigma-delta ADC with a quantizer may include an input voltage summation node 118, a loop filter 116, a multi-bit quantizer 120, a multi-bit digital-to-analog converter (DAC) 114, and a digital decimation filter 108.
  • the quantizer 120 may be a fixed or variable resolution quantizer.
  • the digital filter 108 receives an over sampled digital bit stream 112 and decimates the digital bit stream 112 so as to produce, for example but is not limited to, a P-bit data word (on bus 110) representative of the measured analog input signal at input 114. This decimation process also removes most of the high frequency noise that is coming from the quantization process and that is noise shaped by the sigma-delta ADC 100 throughout its analog loop filter 116.
  • the transfer function from E (quantization noise introduced by the quantizer) to the output bitstream is a high-pass filter.
  • E schematically represents the quantization error introduced by the fixed multi-bit quantizer 120.
  • the DAC 114 may be implemented as a multi-bit capacitive DAC of the charge transfer type with 4n+1 levels using only n capacitors and minimal dynamic element matching and a reduced number of switches. More generally, according to various embodiments, sigma delta converters can be provided with multi-level DACs with a minimal number of matched unit capacitors and relatively simple dynamic element matching techniques. This will lead to more accurate sigma delta devices using approximately same size and same power as existing devices.
  • FIG. 2 a diagram illustrating an exemplary DAC of the charge transfer type is shown. Depicted is a schematic circuit diagram of capacitor switching arrays and a differential amplifier for a multi-level feed-back digital-to-analog converter (DAC).
  • DAC digital-to-analog converter
  • the multi-level feedback DAC 200 includes a processing circuit 201 and a plurality of reference voltage charging circuits 202a-202n.
  • the DAC 200 thus comprises n parallel DACs, each of the n DACs including its own reference voltage charging circuit.
  • Each reference voltage charging circuit and corresponding DAC implements a five-level DAC.
  • the circuit 200 will be explained first as a five-level DAC implemented with a single reference voltage charging circuit 202a.
  • a five-level DAC is described in commonly-assigned U.S. Patent No. 7,102,558 , titled "Five-Level Feed-Back Digital-to-Analog Converter for a Switched Capacitor Sigma-Delta Analog-to-Digital Converter.
  • a five-level feed-back DAC of the charge transfer type can be operated using switching patterns that generate five equally spaced charge quantities during two phases, such as a charge or pre-charge phase and a transfer phase, of a differential charge transfer.
  • a pattern is defined by two phases according to an embodiment. However, other patterns with more phases may be used.
  • a pattern is to be understood to generate an output voltage of the DAC.
  • a sequence of patterns may be used which refers to a sequence of output voltages in the time domain generated by the DAC.
  • Each voltage is generated by a switching pattern which, for example, can be generated by a switching control unit 260.
  • Switching control unit 260 receives the DAC digital input word or the multi-level input information which is used to decode or determine which pattern is applied to the switches.
  • FIG. 2 only shows control lines for the switches in the reference voltage switching circuit. However, as indicated by the dotted line switching control unit 260 may generate all necessary switch control signals for the remaining switches of the circuit shown in FIG. 2 .
  • switching control unit 260 may also receive and generate further control signals such as clock signals, conversion start signals, conversion end signals, etc.
  • the switching control unit 260 may provide switch control signals for all n voltage reference modules 202.
  • a five-level feed-back DAC including a single reference voltage charging unit 202a implements a switching sequence that generates five equally spaced charge quantities during two phases (precharge+transfer) of a differential charge transfer.
  • the five equally distributed charge levels may be C ⁇ VREF, C ⁇ VREF/2, 0, -C ⁇ VREF/2 and -C ⁇ VREF.
  • the remainder of the specific exemplary embodiment comprises voltage input capacitors 230a and 230b, switches 204, 206, 208 and 210, and differential operational amplifier 250 having feed-back sampling capacitors 234a and 234b.
  • Switches 208a and 208b may relate to common mode operation
  • switch 208c may relate to differential signal operation.
  • VREFP and VREFM represent voltages at the differential reference input terminals.
  • the reference voltage VREF VREFP-VREFM.
  • VINP and VINM represent voltages at the differential input signal terminals.
  • the input signal voltage VIN VINP-VINM.
  • the transfer reference capacitors 232a and 232b may be, for example, equal to C/2.
  • the input sampling capacitors 230a and 230b may be equal to A ⁇ C/2.
  • the feed-back capacitors 234a and 234b may be equal to C to get a gain stage of 1 for the reference signals with one DAC stage, although in other embodiments this may differ depending on the desired reference path gain.
  • the gain of the circuit shown is A. (If there are multiple sets of C/2 caps in parallel (n times) to do a 4n+1 DAC, the gain is then equal to n, and the feedback caps would be C/n to still get a gain of 1. It is noted, however, that in other embodiments, gain may be different than 1).
  • the five-level feed-back DAC When summed with an input voltage, VIN, the five-level feed-back DAC produces five equally distributed output voltages of A ⁇ VIN+VREF, A ⁇ VIN+VREF/2, A ⁇ VIN+0, A ⁇ VIN-VREF/2 and A ⁇ VIN-VREF, where A is gain, VIN is the input voltage, and VREF is the reference voltage. This is illustrated more particularly with reference to FIG. 3 .
  • FIGS. 3a-3e depicted are timing diagrams for conventional switching patterns of the switches 204-216 used to obtain the five equally distributed charge levels C*VREF, C*VREF/2, 0, -C ⁇ VREF/2 and -C ⁇ VREF of the specific exemplary embodiment illustrated in FIG. 2 .
  • a “1" logic level depicts the respective switches in the closed position and a "0" logic level depicts the respective switches in the open position.
  • P1 represents a charging phase of the reference transfer capacitors 232a, 232b
  • P2 represents a transfer phase of the charge on the reference capacitors 232a, 232b.
  • FIGS. 3a-3e further illustrate non-overlapping delays between the switches 104-116 in order to prevent a short between inputs and to ensure that the switches connected to the summing node always open first.
  • the switches 204-216 are all open (off-logic 0) between time 302 and time 304.
  • Time 302 signifies the end of the charging phase for both the reference capacitors 232 and input signal capacitors 230.
  • Time 304 signifies the beginning of the transfer phase from both the reference capacitors 232 and input signal capacitors 230 to the feedback capacitors 234.
  • FIG. 3a depicted is the timing diagram for transferring a plus (positive) charge, C ⁇ VREF.
  • the reference capacitors 232a and 232b are connected to VREFP and VREFM, respectively, during the precharge phase (before time 202a) and switched to VREFM and VREFP, respectively, during the transfer phase (after time 204a).
  • a ⁇ C/2 ⁇ (VINP-VINM)-A ⁇ C/2 ⁇ (VINM-VINP) A ⁇ C ⁇ VIN at the summing node of the input of the differential operational amplifier 250, the transferred voltage is A ⁇ VIN+VREF at the output of the differential operational amplifier 250.
  • FIG. 3e depicted is the timing diagram for transferring a minus (negative) charge, C ⁇ (-VREF).
  • C ⁇ minus (negative) charge
  • the opposite pattern from that shown in FIG. 3a is performed to achieve a -C ⁇ VREF charge to the summing node.
  • a ⁇ C/2 ⁇ (VINP-VINM)-A/2 ⁇ C ⁇ (VINM-VINP) A ⁇ C ⁇ VIN at the summing node of the input of the differential operational amplifier 250
  • the transferred voltage is A ⁇ VIN-VREF at the output of the differential operational amplifier 250.
  • the charging and transferring patterns of FIGS. 3a and 3e represent a basic two level feed-back DAC of a sigma-delta modulator.
  • the reference capacitors 232a and 232b are connected to VREFP and VREFM, respectively, during the precharge phase (before time 402b) and have their input plates short-circuited during the transfer phase (after time 404b).
  • the input plates of the reference capacitors 232a and 232b are short-circuited during both during the precharge phase (before time 402c) and the transfer phase (after time 204 c).
  • a ⁇ C/2 ⁇ (VINP-VINM)-A ⁇ C/2 ⁇ (VINM-VINP) A ⁇ C ⁇ VIN at the summing node of the input of the differential operational amplifier 150
  • the transferred voltage is A ⁇ VIN+0 at the output of the differential operational amplifier 150.
  • the reference capacitors 232 a and 232b are connected to VREFM and VREFP, respectively, during the precharge phase (before time 202d) and have their input plates short-circuited during the transfer phase (after time 204d).
  • a ⁇ C ⁇ (VINP-VINM)-A ⁇ C ⁇ (VINM-VINP) 2A ⁇ C ⁇ VIN at the summing node of the input of the differential operational amplifier 250, the transferred voltage is A ⁇ VIN-VREF/2 at the output of the differential operational amplifier 250.
  • multiple of these DACs may be used in parallel by having a circuit with n voltage reference charging circuits 202 (n times in parallel) in order to go beyond a 5-level resolution.
  • a difficulty of having multiple 5-level DACs in parallel is the matching between the capacitors.
  • each DAC has a different, independent input and each input can be either +2/+1/0/-1/-2.
  • the mismatch in the capacitor pair (e.g., 232a, 232b) in the differential structure is not considered since only the differential charge is integrated further, therefore, even if the capacitors are not perfectly matched on the + and the - side of the differential structure, it is equivalent to have a perfect matching with the average of the capacitors for the pure differential transfer. Therefore the system can be simplified and it can be considered that the capacitors on each side of the differential structure are equal.
  • n DACs can be used in parallel with each one of these having a Cref(k) capacitor and transferring in(k) ⁇ Cref(k) ⁇ Vref, where in(k) is an integer that can charge transfer since all DACs are in parallel. If all the capacitors are perfectly equal to Cref, and if there are n DACs in parallel, the charge transfers are comprised between 2n ⁇ Cref ⁇ Vref and -2n ⁇ Cref ⁇ Vref with a granularity of 1 ⁇ Cref ⁇ Vref. This results in 4n+1 levels total. So with n 5-level DACs, a circuit having 4n+1 levels of resolution is achieved if the capacitors are the same unit capacitors. The linearity is maintained if the capacitors are perfectly matched.
  • FIG. 4 shown in FIG. 4 is a configuration more particularly showing the n voltage reference blocks.
  • the switching control unit 260 ( FIG. 2 ) may be used to control the switching of corresponding switches to achieve the desired output levels.
  • the last column represents a normalized sum. 0 may also be obtained with a C ⁇ VREF/4 transfer on P1 and a -C ⁇ VREF/2 transfer on P2.
  • FIG. 5 supposes perfect matching. Difficulties may arise because in all likelihood, the capacitors will not be matched but it is still desired to maintain the linearity of the DAC.
  • the ultimate goal is to have the total charge transferred always proportional to the sum of all Cref(k) capacitors. This is possible if a sequence of charge transfers is processed by the DAC. At each input processed, the DAC linearity may not be guaranteed, but after a certain number of transfers, the linearity can be maintained if the total charge transferred is considered.
  • the DAC In a sigma-delta ADC, the DAC is typically used in the feedback loop of the modulator and the output of the DAC is constantly integrated during a conversion. So as long as the linearity of the DAC is maintained, even if it comes after several integrations, it will not impact the linearity of the delta-sigma ADC (provided that the modulator loop stability is not degraded during the sequencing). In other words, a dynamic element matching or dynamic weight averaging technique can be applied to maintain DAC linearity.
  • all DACs in parallel may have a 2Cref(k)Vref charge transfer except one that only needs a 1 ⁇ Cref(j) ⁇ Vref charge transfer.
  • This DAC number j has a different charge transfer than all others.
  • one of the DACs has a single transfer, the transfer is not 2n-1 ⁇ Sum(Cref(k))Vref/n but 2Sum(Cref(k))Vref, k different than j + Cref(j)Vref.
  • the difference from an integer number of Sum(Cref(k)) ⁇ Vref transfer is -Cref(j) ⁇ Vref.
  • the sequence can register this difference (-1 on the j-th cap) and can try to compensate for it with another DAC input. For example if the DAC input is +1, the shortest way to compensate this difference is to do a simple transfer on the j-th cap: Cref(j)Vref.
  • the DAC charge transfer is proportional to the Sum(Cref(k))Vref and the DAC linearity is maintained.
  • the complimentary to a 2n (2n-m) can follow the complementary sequence to cancel the DAC non linearity.
  • a chopper modulated Vref can be used and have the charge transfers in each DAC in parallel follow the sequences as shown, for example, in commonly-assigned U.S. patent 7,994,958 in order to cancel the offset in each DAC.
  • an odd transfer and an even transfer at the input of each DAC can be defined.
  • An even transfer is when an input of the DAC is even (+/-2 or 0) and an odd transfer is when the input is odd (+/-1, +/-3).
  • the even transfers cancel the offset of the Vref per the teachings of the US 7,994,958 .
  • the odd transfers need a sequence of 2 samples to completely cancel the offset. These sequences need to be performed on each DAC individually to cancel completely the offset at the output of the DAC.
  • a randomization of these sequences of 2 samples per DAC can be realized to further break output tones in the output spectrum.
  • the goal with a two capacitor (CI and C2, corresponding to a two DAC, e.g., 202a, 202b) design is to be sure to have the same number of transfers using C1 and C2 for +VREF and -VREF.
  • This is already the case for even transfers, i.e., (inputs of 4/2/0/-2/- 4), and for these, there are no matching issues.
  • This is shown with reference to FIG. 6 .
  • the result is 5 levels with perfect linearity.
  • C1 and C2 transfers have to be different, but multiple combinations are possible. That is, by varying the combinations over time with a predefined sequence and averaging can make the number of C1 and C2 transfers the same.
  • an average of combinations may be obtained that is proportional to C1+C2.
  • the DAC will be linear.
  • the sequence to get the average to be proportional to C1+C2 can be only 2 samples long (n samples minimum if using n caps).
  • FIG. 7 illustrates sequences that will average every sequence of independent odd transfers and are proportional to C1+C2.
  • sequences may also cancel the offset of the VREF if VREF is chopped between P1 and P2.
  • FIG. 8 This is shown by way of example in FIG. 8 . More particularly, shown in FIG. 8 is a table of the transfers on C1 and C2. The four samples 1-4 have transfer sequences with the starting C1 or C2 chosen randomly to avoid a periodic pattern.
  • the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” or any other variation thereof, are intended to cover a non-exclusive inclusion.
  • a process, product, article, or apparatus that comprises a list of elements is not necessarily limited only those elements but may include other elements not expressly listed or inherent to such process, process, article, or apparatus.

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Claims (15)

  1. Convertisseur numérique-analogique, DAC, du type à transfert de charges pertinent en vue d'une utilisation dans un modulateur sigma-delta, comprenant :
    une unité de commutation de condensateurs exploitable de manière à générer « 4n+1» niveaux de sortie, dans lequel « n » est un nombre entier, et n ≥ 2, comprenant :
    « n » unités de commutation (202a, ..., n) configurées chacune de manière à générer cinq quantités de charge espacées de manière égale, et couplées en parallèle, de sorte que des premières bornes de « n » paires de condensateurs de référence (232a, b) peuvent être couplées soit avec un signal de référence positif, soit avec un signal de référence négatif (VREFP, VREFM) ;
    un contrôleur de commutation (230) configuré de manière à commander les « n » unités de commutation (202a, ..., n) en vue de générer des motifs de commutation pour chaque niveau de la pluralité de niveaux de sortie, dans lequel chaque motif comprend une phase de charge et une phase à transfert de charges ;
    dans lequel les secondes bornes des « n » paires de condensateurs de référence (232a, b) sont couplées en parallèle, respectivement ;
    dans lequel, pour les transferts de charges pairs, une combinaison de commutation unique est fournie de sorte que la somme de la totalité des transferts de charges est proportionnelle à une somme des capacités des paires de condensateurs (232a, b) des « n » unités de commutation, et dans lequel, pour les transferts de charges impairs, une moyenne de différentes combinaisons de commutation est fournie, dans lequel la somme de la totalité des transferts de charges des différentes combinaisons de commutation est proportionnelle à une somme des capacités des paires de condensateurs (232a, b) des « n » unités de commutation (202a, ..., n) ;
    dans lequel un transfert de charges est pair lorsqu'une entrée du convertisseur DAC est paire, et un transfert de charges est impair lorsqu'une entrée au niveau du convertisseur DAC est impaire.
  2. Convertisseur DAC selon la revendication 1, dans lequel les commutateurs pour chacune des « n » unités de commutation (202a, ..., n) sont commandés indépendamment.
  3. Convertisseur DAC selon la revendication 1 ou 2, dans lequel des transferts de charges peuvent être mis en œuvre pendant une première phase et/ou une seconde phase pour chaque combinaison de commutation.
  4. Convertisseur DAC selon l'une quelconque des revendications précédentes, dans lequel deux combinaisons de commutation sont utilisées pour chaque entrée de convertisseur DAC impaire.
  5. Convertisseur DAC selon la revendication 4, dans lequel, pour une séquence de deux entrées de convertisseur DAC impaires subséquentes présentant la même valeur, l'une parmi les première et seconde combinaisons de commutation est choisie de manière aléatoire pour la première entrée de convertisseur DAC impaire, dans lequel l'autre séquence de commutation respective est utilisée pour la seconde entrée de convertisseur DAC impaire.
  6. Convertisseur DAC selon la revendication 3, dans lequel n = 2, et dans lequel des valeurs d'entrée numérique normalisées sont constituées de 0, ±1, ±2, ±3 et ±4 ;
    dans lequel, pour une valeur normalisée de 4, une combinaison de commutation associée transfère une charge de C∗Vref dans chaque unité de commutation pendant chacune des première et seconde phases ;
    dans lequel, pour une valeur de 3, une première combinaison de commutation transfère une charge de C∗Vref dans la première unité de commutation pendant chacune des première et seconde phases et une charge de C∗Vref dans la seconde unité de commutation uniquement pendant la première phase ou la seconde phase, et une seconde combinaison de commutation transfère une charge de C∗Vref dans la seconde unité de commutation pendant chacune des première et seconde phases, et une charge de C∗Vref dans la première unité de commutation uniquement pendant la première phase ou la seconde phase ;
    dans lequel, pour une valeur de 2, une combinaison de commutation associée transfère une charge de C∗Vref uniquement pendant la première phase ou la seconde phase dans chaque unité de commutation ;
    dans lequel, pour une valeur de 1, une première combinaison de commutation transfère une charge de C∗Vref dans la première unité de commutation uniquement pendant la première phase ou la seconde phase et aucune charge n'est transférée dans la seconde unité de commutation, et une seconde combinaison de commutation transfère une charge de C∗Vref dans la seconde unité de commutation uniquement pendant la première phase ou la seconde phase et aucune charge n'est transférée dans la première unité de commutation ;
    dans lequel, pour une valeur de 0, aucun transfert de charges n'a lieu ;
    dans lequel « C » représente une capacité et « Vref » représente une tension de la tension de référence ; et
    dans lequel des valeurs négatives transfèrent des charges respectives en utilisant une tension de référence négative.
  7. Modulateur sigma-delta comprenant :
    un convertisseur DAC selon l'une quelconque des revendications précédentes ;
    une seconde unité de commutation (201) pour coupler des premières bornes d'une paire de condensateurs d'entrée (230a, b) avec soit un signal d'entrée positif, soit un signal d'entrée négatif ;
    dans lequel les secondes bornes des paires de condensateurs d'entrée (230a, b) et des « n » paires de condensateurs de référence (232a, b) sont couplées en parallèle, respectivement.
  8. Modulateur sigma-delta selon la revendication 3, comprenant en outre un réseau de commutation (210a, b) couplant les secondes bornes des condensateurs d'entrée et de référence avec un amplificateur différentiel (250).
  9. Procédé de fonctionnement d'un convertisseur numérique-analogique, DAC, du type à transfert de charge, comprenant les étapes ci-dessous consistant à :
    générer « 4n +1 » tensions de sortie avec un étage de condensateur commuté, dans lequel « n » est un nombre entier, et n ≥ 2, comprenant « n » agencements de commutation de tension de référence individuels (202a, ..., n) configurés chacun de manière à générer cinq quantités de charge espacées de manière égale, et comprenant chacun une paire de condensateurs (232a, b) avec des sorties couplées en parallèle ; et
    commander chaque agencement de commutation de tension de référence (202a, ..., n) en vue de générer des motifs de commutation pour chacune des « 4n+1» tensions de sortie, dans lequel chaque motif comprend une phase de charge et une phase à transfert de charges ;
    dans lequel, pour des transferts de charges pairs, une configuration de commutation unique est mise en œuvre de sorte que la somme de la totalité des transferts de charges est proportionnelle à une somme des capacités des paires de condensateurs (232a, b) des « n » agencements de commutation de tension de référence (202a, ..., n), et dans lequel pour des transferts de charges impairs, une moyenne de différentes combinaisons de commutation est mise en œuvre, dans lequel la somme de la totalité des transferts de charges des différentes combinaisons de commutation est proportionnelle à une somme des capacités des « n » paires de condensateurs (232a, b) des « n » agencements de commutation de tension de référence (202a, ..., n) ;
    dans lequel un transfert de charges est pair lorsqu'une entrée du convertisseur DAC est paire, et un transfert de charges est impair lorsqu'une entrée au convertisseur DAC est impaire.
  10. Procédé selon la revendication 9, dans lequel les commutateurs pour chacune des « n » unités de commutation (202a, ..., n) sont commandés indépendamment.
  11. Procédé selon l'une quelconque des revendications 9 à 10, dans lequel deux combinaisons de commutation sont utilisées pour chaque entrée de condensateur DAC impaire.
  12. Procédé selon la revendication 11, dans lequel, pour une séquence de deux entrées de condensateur DAC impaires subséquentes présentant la même valeur, l'une parmi les première et seconde combinaisons de commutation est choisie de manière aléatoire pour la première entrée de condensateur DAC impaire, dans lequel l'autre séquence de commutation respective étant utilisée pour la seconde entrée de condensateur DAC impaire.
  13. Procédé selon l'une quelconque des revendications 9 à 12, dans lequel des transferts de charges peuvent être mis en œuvre pendant une première phase et une seconde phase pour chaque combinaison de commutation, et dans lequel n = 2 et des valeurs d'entrée numérique normalisées sont constituées de 0, ±1, ±2, ±3 et ±4,
    dans lequel, pour une valeur normalisée de 4, une combinaison de commutation associée transfère une charge de C∗Vref dans chaque agencement de commutation de tension de référence (202) pendant chacune des première et seconde phases ;
    dans lequel, pour une valeur de 3, une première combinaison de commutation transfère une charge de C∗Vref dans le premier agencement de commutation de tension de référence (202a) pendant chacune des première et seconde phases et une charge de C∗Vref dans le second agencement de commutation de tension de référence (202b) uniquement pendant la première phase ou la seconde phase, et une seconde combinaison de commutation transfère une charge de C∗Vref dans le second agencement de commutation de tension de référence (202b) pendant chacune des première et seconde phases, et une charge de C∗Vref dans le premier agencement de commutation de tension de référence (202a) uniquement pendant la première phase ou la seconde phase ;
    dans lequel, pour une valeur de 2, une combinaison de commutation associée transfère une charge de C∗Vref uniquement pendant la première phase ou la seconde phase dans chaque agencement de commutation de tension de référence (202) ;
    dans lequel, pour une valeur de 1, une première combinaison de commutation transfère une charge de C∗Vref dans le premier agencement de commutation de tension de référence (202a) uniquement pendant la première phase ou la seconde phase et aucune charge n'est transférée dans le second agencement de commutation de tension de référence (202b), et une seconde combinaison de commutation transfère une charge de C∗Vref dans le second agencement de commutation de tension de référence (202b) uniquement pendant la première phase ou la seconde phase et aucune charge n'est transférée dans le premier agencement de commutation de tension de référence (202a) ;
    dans lequel, pour une valeur de 0, aucun transfert de charges n'a lieu ;
    dans lequel « C » représente une capacité et « Vref » représente une tension de la tension de référence ; et
    dans lequel des valeurs négatives transfèrent des charges respectives en utilisant une tension de référence négative.
  14. Procédé selon la revendication 13 ou convertisseur DAC selon la revendication 6, dans lequel la capacité est la capacité efficace d'une paire de capacités couplées en série.
  15. Procédé selon l'une quelconque des revendications 9 à 14, dans lequel les tensions de sortie générées par le convertisseur DAC sont combinées avec une unité de commutation de signal d'entrée (201) comprenant une paire de condensateurs d'entrée (230a, b) qui peut être couplée avec un signal d'entrée positif ou un signal d'entrée négatif, et dans lequel les secondes bornes des paires de condensateurs d'entrée (230a, b) et des « n » paires de condensateurs de référence (232a, b) sont couplées en parallèle.
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TWI624154B (zh) 2018-05-11
CN105075124A (zh) 2015-11-18
CN105075124B (zh) 2018-11-06
US20140253355A1 (en) 2014-09-11
WO2014164511A1 (fr) 2014-10-09
KR20150126606A (ko) 2015-11-12
US8970416B2 (en) 2015-03-03
EP2974032A1 (fr) 2016-01-20

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