EP2909861A1 - Image sensor having improved quantum efficiency at large wavelengths - Google Patents

Image sensor having improved quantum efficiency at large wavelengths

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Publication number
EP2909861A1
EP2909861A1 EP13776834.7A EP13776834A EP2909861A1 EP 2909861 A1 EP2909861 A1 EP 2909861A1 EP 13776834 A EP13776834 A EP 13776834A EP 2909861 A1 EP2909861 A1 EP 2909861A1
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EP
European Patent Office
Prior art keywords
layer
active layer
active
matrix
ohms
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
EP13776834.7A
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German (de)
French (fr)
Inventor
Thierry Ligozat
Pierre Fereyre
Frédéric Mayer
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Teledyne e2v Semiconductors SAS
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e2v Semiconductors SAS
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Application filed by e2v Semiconductors SAS filed Critical e2v Semiconductors SAS
Publication of EP2909861A1 publication Critical patent/EP2909861A1/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/1461—Pixel-elements with integrated switching, control, storage or amplification elements characterised by the photosensitive area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1464—Back illuminated imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14632—Wafer-level processed structures

Definitions

  • the invention relates to CMOS image sensors on a silicon substrate.
  • a high-performance image sensor must respond to multiple contradictory constraints: reduction of pixel size to improve resolution and size or cost of manufacture; but, however, setting up several transistors in each pixel to read the signal notably in instantaneous shooting mode ('snapshot' mode, with integration time common to all the pixel lines); high electron storage capacity in each pixel to maximize linear illumination measurement dynamics without pixel saturation; maximum sensitivity for low light conditions with as little noise as possible, etc.
  • the spectrum of lunar reflection is approximately uniform in the visible and near infrared range, but natural luminescence in the absence of a moon is much lower in the visible range than in the near infrared.
  • An object of the invention is therefore to improve the quality of the image sensors by improving the quantum efficiency of the detection, that is to say the ratio between the number of electronic charges collected in a photosensitive surface and the number of photons received by this surface, in the near infrared (from about 750 nanometers to 1100 nanometers), without impairing the detection in the visible range (from about 400 nanometers to 800 nanometers), and while maintaining a technological compatibility with manufacturing electronic processing circuits formed on the same integrated circuit chip as the sensor.
  • the invention proposes an image sensor formed on an integrated circuit chip from a silicon substrate of a first conductivity type, comprising:
  • this sensor being characterized in that the active monocrystalline silicon layer has a resistivity of at least 500 ohms. cm if this active layer is an epitaxial layer in contact with the silicon substrate of the first conductivity type and at least 2000 ohms. cm if this active layer is constituted directly by the upper part of the silicon substrate, and in that the control circuit portions and the reading circuits are formed in at least one doped overall box, of the same type as the active layer of monocrystalline silicon and having a resistivity of at most 40 ohms. cm, this box being formed in the active layer and not including the matrix of pixels.
  • the box formed in this layer starts from the surface of the active layer, whether or not it is an epitaxial layer, and preferably has a depth of a few microns (preferably about 2 to 5 microns). micrometers) to allow normal operation of the MOS transistors.
  • This layer itself contains the boxes useful for the realization of the constituent elements of the CMOS technology (transistors, capacitors, diodes, etc.). If the active monocrystalline silicon layer is an epitaxial layer, the thickness of this layer is preferably between 10 micrometers and 50 micrometers; the caisson does not descend over the entire depth of the epitaxial active layer.
  • This structure clearly divides the image sensor chip into an area reserved for the matrix and an area reserved for the electronic control and reading circuits external to the matrix; these zones are distinguished by the doping different from the active layer, since the active layer in the zone reserved for the control and reading circuits has a much lower resistivity (that of the doped box) than the active layer in the zone reserved for the pixel matrix. There is a direct link between doping and resistivity, the resistivity is even lower than the doping is strong.
  • the protective structures against electrostatic discharges will be better controlled. If the pixel array is formed in an epitaxial active layer, an active layer resistivity of 500 to 2000 ohms is preferably selected. cm. If it is formed directly in the upper part of a non-epitaxial silicon substrate (substrate obtained by drawing the ingot and sawing the ingot without epitaxial growth on the sawed edge), the substrate will preferably be given a resistivity of 5,000 to 10,000. ohms. cm.
  • the invention is also applicable in the case of a thinned sensor illuminated by its rear face, that is to say a sensor in which all or almost all of the starting silicon substrate has been eliminated. by its rear face, retaining only the active layer itself carried by its front face on another substrate (transfer substrate). In that case, it is the sensitivity in blue rather than in the near infrared that can be improved.
  • FIG. 1 shows schematically in top view an integrated image sensor on silicon comprising a matrix of pixels and electronic circuits external to the matrix;
  • FIG. 2 represents a global box, diffused in a layer of the same type of conductivity but less doped, the box not enclosing the region corresponding to the matrix of pixels;
  • FIG. 3 represents an alternative embodiment in which the box does not enclose the matrix, a ring for grounding the substrate surrounding the matrix, or a protection ring surrounding the matrix;
  • FIG. 4 represents a section of the sensor at the boundary between the matrix and the overall box
  • FIG. 5 represents the quantum efficiency curves as a function of the wavelength for a pixel according to the invention and a pixel of conventional technology.
  • Figure 1 shows the conventional constitution of an image sensor formed on an integrated circuit chip IC; it comprises an MP matrix of rows and columns of active pixels, each pixel comprising a photodiode and MOS transistors.
  • the transistors are used for pixel selection, control of start and end of integration time, and conversion of a quantity of generated photo charges into a voltage level representing the illumination of the pixel.
  • CTRL control circuits include sequencers and line addressing circuits for line-by-line pixel selection, etc.
  • RD readout circuits include sampling circuits that collect analog voltage levels produced by pixels, and analog-to-digital conversion circuits; they may also include other signal processing functions.
  • the integrated circuit is formed from a highly doped silicon substrate, of low resistivity (for example from 1 to 50 milliohms.cm), covered with an active layer of monocrystalline silicon which is a layer less doped epitaxial and therefore of higher resistivity (typically 5 to 30 ohms cm). It is assumed in the following that the epitaxial active layer is of type P, but it could be of N type and in this case all types of conductivity which will now be indicated must be reversed.
  • the photodiodes of the pixels N-type diffusion in the P-type active layer, the N-type diffusion being most often covered with a P-type surface layer
  • the other circuit elements of the pixel for example the sources and drains of NMOS transistors of the pixel,
  • the thickness of the epitaxial active layer in the structure of Figure 1 is about 5 to 10 microns.
  • the photodiodes are formed in an active monocrystalline silicon layer which has a much higher resistivity than in the prior art, typically a resistivity of at least 500 ohms.cm for the layer epitaxial, ie at least 20 to 50 times more than in the prior art.
  • the control circuits CTRL and read RD and more generally all the electronic circuits located outside the perimeter PR of the pixel matrix, are placed in at least one deep global box DPW P type (for an active layer of type P) shown in dashed area in FIG. 2. This box is deeper than the individual boxes of type N of PMOS transistors of the circuits.
  • Its depth is preferably at least 2 to 4 micrometers, in any case less than or equal to the depth of the active epitaxial layer. Its doping, higher than that of the active layer, is such that it has a resistivity much lower than that of the active layer; the resistivity of the overall box DPW is at most 30 ohms. cm and preferably between 5 and 10 ohms. cm.
  • the box does not cover the surface of the matrix MP or even a part of the matrix, that is to say that the edges of the box stop, if we go from the outside to the inside of the matrix, before the perimeter PR of the matrix, as seen in Figure 2.
  • the box, the active layer and the substrate are of the same type of conductivity, here P.
  • the control and reading circuits CTRL and RD external to the matrix, or at least portions thereof, are included in the overall P-type DPW box and the PMOS transistors of these circuits are formed in individual N-type boxes. less deep than the overall DPW box.
  • the individual N type casings may have a depth of about 1 micron.
  • global box is meant that large circuit portions including many transistors and other circuit elements are included in the same box.
  • Figure 2 shows a single overall box, but it is understood that for practical reasons it could be envisaged to subdivide this box into several different overall boxes, for example a respective overall box for CTRL circuits and another for RD circuits. It may also happen that some elements of these circuits are formed in an N-type deep well, but the invention is concerned here with those of the circuit elements which are formed in a type P deep well of the same type as the layer. active but of different doping.
  • the active layer is an epitaxial layer; this layer is formed on a silicon substrate which is a slice sawn in a silicon ingot formed by drawing in a molten silicon bath. The surface of the slice is polished.
  • the epitaxial layer is much less doped than the substrate.
  • the latter is of the same type of conductivity as the active layer; it is preferably of the heavily doped type P.
  • the active layer is not formed by an epitaxial layer on the surface of the substrate but it is formed by the upper part of the substrate itself consisting of the slice sawn in the silicon ingot; in this case, the resistivity of the active layer (again of the same type of conductivity as the substrate) is preferably even higher; it is at least 2,000 ohms. cm and preferably greater than 5,000 ohms. cm.
  • the silicon ingot is prepared with low doping which leads to this high resistivity.
  • the pixel array is surrounded by two concentric peripheral rings AN1 and AN2, and the DPW box does not encompass the matrix or these two peripheral rings.
  • the inner ring AN1 closer to the perimeter PR of the matrix, consists of a P-type diffusion, strongly doped and electrically connected to a mass; it is used to set the potential of the active layer to zero throughout the region of the matrix MP to form a ground plane.
  • the outer ring AN2 is a strongly doped N-type diffusion and connected to a general positive supply potential Vdd; it serves to create a deep depletion zone tending to prevent parasitic charges from propagating from the outside to the inside of the matrix region MP.
  • FIG. 4 represents a section of the sensor structure according to the invention, this section being taken along line IV-IV of FIG. 3, in the region of the boundary between the matrix MP and the overall deep well DPW.
  • the structure comprises a P-type silicon substrate 10 (suppressed during manufacture in the case of a thinned sensor illuminated by the rear face), and an active layer 12 of monocrystalline silicon of the same low-doped type (P-) at the top of the substrate.
  • Peripheral rings AN1 type P + and AN2 type N + are scattered from the surface.
  • the pixel array is formed in the MP region surrounded by the peripheral rings, using the weakly doped P-type silicon of the active layer to form the anode of the photodiodes; the cathode is formed by an N-type surface diffusion in this active layer, and this diffusion may itself be covered with a P-type surface diffusion electrically connected to the anode.
  • Channel regions of transistors pixels are constituted by the active layer (whose doping can be locally adjusted to adjust the threshold voltage).
  • the RD reading and CTRL control circuits are formed in the P-type DPW box, outside the matrix and the peripheral rings and much more doped than the active layer.
  • the channel region of the NMOS transistors of these circuits is constituted by the global box DPW (or by specific boxes) with possibly a local adjustment of the doping to adjust the threshold voltage;
  • the PMOS transistors of these circuits are formed in individual shallow (about 1 micron) N-shaped wells, shallower than the overall well, diffused from the surface of the overall well; the channel region of these PMOS transistors is constituted by the individual boxes; again, channel doping can be adjusted to adjust the threshold voltage.
  • the active monocrystalline silicon layer is an epitaxial layer deposited on a heavily doped silicon substrate of the same conductivity type having a resistivity of 1 to 20 milliohms.cm.
  • the epitaxial layer has a depth preferably greater than 10 microns and preferably between 10 and 50 microns. Its resistivity is greater than 500 ohms. cm and preferably between 500 and 3000 ohms. cm.
  • the active layer is formed by the monocrystalline silicon substrate itself and is of the same type of conductivity as the substrate.
  • the substrate is weakly doped, its resistivity being at least 2000 ohms. cm and preferably between 5000 ohms. cm and 10,000 ohms. cm.
  • the thickness of the substrate may be 700 microns for example for an unthinned sensor.
  • the image sensor can be thinned and illuminated by the back side, ie after the formation of the matrix MP and the electronic circuits on the front face of the active layer.
  • the silicon substrate is bonded by this front face to a transfer substrate and then the rear face of the starting substrate is thinned until only the active layer (epitaxial or non-epitaxial) of a thickness of a few microns to a few tens micrometers. This is the substrate of report which ensures the mechanical resistance during the manufacture and after the manufacture.
  • the depletion zone which naturally forms under the photodiodes is deeper, which significantly improves the collection of charges. generated by deep photons.
  • the largest wavelengths to which silicon is sensitive penetrate deeper into the silicon, they effectively contribute to the production of electrons without these electrons dispersing in the substrate to neighboring pixels.
  • the spatial resolution is improved. This particularly concerns near-infrared wavelengths, since silicon is photosensitive in a wavelength range from 250 nanometers (near ultraviolet) to a little more than 1050 nanometers (near infrared).
  • the depth of the active layer (in the case where it is constituted by an epitaxial layer or in the case of a thinned sensor, is chosen sufficient to be able to capture as much as possible the wavelengths ranging from 800 to 1100 nanometers; this depth is then chosen preferably greater than 15 micrometers and better still greater than 30 micrometers, whereas in the prior art it is rather less than 5 micrometers.With a depth greater than 15 micrometers, or better still 30 micrometers, it is considered a large proportion of photons with wavelengths ranging from about 800 nanometers to 1100 nanometers can be captured.
  • FIG. 5 gives as an illustration a curve in solid lines representing the quantum efficiency for a pixel according to the invention of 5.3 micrometers of side illuminated by the front face and covered with a microlens.
  • the dotted line curve represents the quantum efficiency for a similar pixel but of standard technology.

Abstract

The invention relates to an image sensor particularly suitable for low-light vision (particularly night vision). The sensor is formed on an integrated circuit (IC) chip from a silicon substrate and includes: an array (MP) of rows and columns of active pixels, each including at least one photodiode and transistors; and circuits (CTRL) for controlling said array, located outside the array, and signal reading circuits (RD) located outside the array. The photodiodes of the sensor are formed in an active monocrystalline silicon layer, the resistivity of which is at least 500 ohms/cm if said active layer is an epitaxial layer on the silicon substrate and at least 2,000 ohms/cm if said active layer consists of the top portion of the silicon substrate. The control circuits (CTRL) and the circuits (RD) for reading the sensor are formed in at least one doped total casing (DPW) of the same type as the active monocrystalline silicon layer and having a resistivity no higher than 30 ohms/cm. Said casing is formed in the active layer and does not include the array.

Description

CAPTEUR D'IMAGE A EFFICACITE QUANTIQUE AMELIOREE DANS LES GRANDES LONGUEURS D'ONDE  IMAGE SENSOR WITH IMPROVED QUANTUM EFFICIENCY IN LARGE WAVELENGTHS
L'invention concerne les capteurs d'image de technologie CMOS sur substrat de silicium. The invention relates to CMOS image sensors on a silicon substrate.
Un capteur d'image performant doit répondre à de multiples contraintes contradictoires : réduction de la taille des pixels pour améliorer la résolution et l'encombrement ou le coût de fabrication ; mais cependant mise en place de plusieurs transistors dans chaque pixel pour lire le signal notamment en mode de prise de vue instantanée (mode 'snapshot', avec temps d'intégration commun à toutes les lignes de pixels) ; capacité de stockage d'électrons élevée dans chaque pixel pour maximiser la dynamique de mesure linéaire d'éclairement sans saturation des pixels ; sensibilité maximale pour les conditions de faible éclairement avec un bruit aussi faible que possible, etc.  A high-performance image sensor must respond to multiple contradictory constraints: reduction of pixel size to improve resolution and size or cost of manufacture; but, however, setting up several transistors in each pixel to read the signal notably in instantaneous shooting mode ('snapshot' mode, with integration time common to all the pixel lines); high electron storage capacity in each pixel to maximize linear illumination measurement dynamics without pixel saturation; maximum sensitivity for low light conditions with as little noise as possible, etc.
De nuit, la lumière provient soit de la lune, soit, en l'absence de lune, de la luminescence naturelle du ciel nocturne ("night glow" en anglais), provenant des galaxies lointaines et également de la réflexion de la lumière solaire sur les particules dispersées dans l'espace atmosphérique ou interplanétaire. On sait mesurer le spectre de luminescence naturelle ou lunaire, qui peut être exprimé en nombre de photons reçus par seconde et par centimètre carré pour une tranche de longueurs d'onde donnée (par exemple de 10 nanomètres en 10 nanomètres).  At night, light comes either from the moon or, in the absence of a moon, from the natural luminescence of the night sky ("glow" in English), coming from distant galaxies and also from the reflection of sunlight on particles dispersed in the atmospheric or interplanetary space. It is known to measure the natural or lunar luminescence spectrum, which can be expressed as the number of photons received per second and per square centimeter for a given wavelength range (for example 10 nanometers in 10 nanometers).
Typiquement, le spectre de la réflexion lunaire est à peu près uniforme, dans le domaine visible et le proche infrarouge, mais la luminescence naturelle en l'absence de lune est beaucoup plus faible dans le domaine visible que dans le proche infrarouge.  Typically, the spectrum of lunar reflection is approximately uniform in the visible and near infrared range, but natural luminescence in the absence of a moon is much lower in the visible range than in the near infrared.
En l'absence de lune, on peut estimer à 5 à 15 le nombre de photons reçus par un pixel de 5x5 micromètres la nuit pendant un temps d'exposition de 1 /25 de seconde à 1 /60 de seconde c'est-à-dire pendant une durée de trame classique d'une prise d'image animée. Ces photons sont en grande majorité dans l'infrarouge proche et non dans les longueurs d'onde visibles.  In the absence of a moon, one can estimate at 5 to 15 the number of photons received by a 5x5 micrometer pixel at night during an exposure time of 1/25 of a second to 1/60 of a second, that is to say for a conventional frame duration of an animated image capture. These photons are mostly in the near infrared and not in the visible wavelengths.
Il est donc important, pour la prise d'image en faible lumière et notamment en vision de nuit, d'augmenter autant que possible la sensibilité du détecteur dans le proche infrarouge, sachant par ailleurs que le silicium présente une capacité de conversion de photons en électrons jusqu'à des longueurs d'onde pouvant atteindre 1 100 nanomètres. It is therefore important, for low-light image capture and particularly for night vision, to increase as much as possible the sensitivity of the detector in the near infrared, knowing moreover that silicon has a capacity to convert photons into electrons up to wavelengths up to 1100 nanometers.
Un but de l'invention est donc d'améliorer la qualité des capteurs d'image en améliorant l'efficacité quantique de la détection, c'est-à-dire le rapport entre le nombre de charges électroniques collectées dans une surface photosensible et le nombre de photons reçus par cette surface, dans le proche infrarouge (de 750 nanomètres environ à 1 100 nanomètres), sans nuire à la détection dans le domaine visible (de 400 nanomètres environ à 800 nanomètres), et tout en conservant une compatibilité technologique avec la fabrication de circuits électroniques de traitement formés sur la même puce de circuit intégré que le capteur.  An object of the invention is therefore to improve the quality of the image sensors by improving the quantum efficiency of the detection, that is to say the ratio between the number of electronic charges collected in a photosensitive surface and the number of photons received by this surface, in the near infrared (from about 750 nanometers to 1100 nanometers), without impairing the detection in the visible range (from about 400 nanometers to 800 nanometers), and while maintaining a technological compatibility with manufacturing electronic processing circuits formed on the same integrated circuit chip as the sensor.
Pour cela, l'invention propose un capteur d'image formé sur une puce de circuit intégré à partir d'un substrat de silicium d'un premier type de conductivité, comprenant : For this purpose, the invention proposes an image sensor formed on an integrated circuit chip from a silicon substrate of a first conductivity type, comprising:
- une matrice de lignes et colonnes de pixels actifs comprenant chacun au moins une photodiode et des transistors formés dans une couche active de silicium monocristallin du premier type de conductivité formée à la surface du substrat,  a matrix of rows and columns of active pixels each comprising at least one photodiode and transistors formed in an active monocrystalline silicon layer of the first conductivity type formed on the surface of the substrate,
- des portions de circuits de commande de la matrice, extérieurs à la matrice, et des portions de circuits de lecture de signal, extérieurs à la matrice,  portions of control circuits of the matrix, external to the matrix, and portions of signal reading circuits, external to the matrix,
ce capteur étant caractérisé en ce que la couche active de silicium monocristallin a une résistivité d'au moins 500 ohms. cm si cette couche active est une couche épitaxiée en contact avec le substrat de silicium du premier type de conductivité et d'au moins 2 000 ohms. cm si cette couche active est constituée directement par la partie supérieure du substrat de silicium, et en ce que les portions de circuits de commande et les circuits de lecture sont formés dans au moins un caisson global dopé, de même type que la couche active de silicium monocristallin et ayant une résistivité d'au plus 40 ohms. cm, ce caisson étant formé dans la couche active et n'incluant pas la matrice de pixels.  this sensor being characterized in that the active monocrystalline silicon layer has a resistivity of at least 500 ohms. cm if this active layer is an epitaxial layer in contact with the silicon substrate of the first conductivity type and at least 2000 ohms. cm if this active layer is constituted directly by the upper part of the silicon substrate, and in that the control circuit portions and the reading circuits are formed in at least one doped overall box, of the same type as the active layer of monocrystalline silicon and having a resistivity of at most 40 ohms. cm, this box being formed in the active layer and not including the matrix of pixels.
Le caisson formé dans cette couche part de la surface de la couche active, qu'elle soit ou non une couche épitaxiale, et a de préférence une profondeur de quelques micromètres (de préférence d'environ 2 à 5 micromètres) afin de permettre un fonctionnement normal des transistors MOS. Cette couche contient elle-même les caissons utiles à la réalisation des éléments constitutifs de la technologie CMOS (transistors, capacités, diodes, etc.). Si la couche active de silicium monocristallin est une couche épitaxiale, l'épaisseur de cette couche est de préférence comprise entre 10 micromètres et 50 micromètres ; le caisson ne descend donc pas sur toute la profondeur de la couche active épitaxiale. The box formed in this layer starts from the surface of the active layer, whether or not it is an epitaxial layer, and preferably has a depth of a few microns (preferably about 2 to 5 microns). micrometers) to allow normal operation of the MOS transistors. This layer itself contains the boxes useful for the realization of the constituent elements of the CMOS technology (transistors, capacitors, diodes, etc.). If the active monocrystalline silicon layer is an epitaxial layer, the thickness of this layer is preferably between 10 micrometers and 50 micrometers; the caisson does not descend over the entire depth of the epitaxial active layer.
Cette structure divise clairement la puce de capteur d'image en une zone réservée à la matrice et une zone réservée aux circuits électroniques de commande et de lecture extérieurs à la matrice ; ces zones se distinguent par le dopage différent de la couche active, puisque la couche active dans la zone réservée aux circuits de commande et de lecture a une résistivité beaucoup plus faible (celle du caisson dopé) que la couche active dans la zone réservée à la matrice de pixels. Il y a un lien direct entre le dopage et la résistivité, la résistivité étant d'autant plus faible que le dopage est fort. This structure clearly divides the image sensor chip into an area reserved for the matrix and an area reserved for the electronic control and reading circuits external to the matrix; these zones are distinguished by the doping different from the active layer, since the active layer in the zone reserved for the control and reading circuits has a much lower resistivity (that of the doped box) than the active layer in the zone reserved for the pixel matrix. There is a direct link between doping and resistivity, the resistivity is even lower than the doping is strong.
Cela permet en particulier de faire des circuits de commande et de lecture qui fonctionnement de manière correcte, avec plus de fiabilité que si ces circuits étaient formés directement dans une couche active dont on aurait augmenté fortement la résistivité pour des raisons liées au bon fonctionnement de la matrice de pixels. En particulier, les structures de protection contre les décharges électrostatiques seront mieux contrôlées. Si la matrice de pixels est formée dans une couche active épitaxiale, on choisira de préférence une résistivité de couche active de 500 à 2 000 ohms. cm. Si elle est formée directement dans la partie supérieure d'un substrat de silicium non épitaxié (substrat obtenu par tirage de lingot et sciage du lingot sans épitaxie sur la tranche sciée), on donnera au substrat de préférence une résistivité de 5 000 à 10 000 ohms. cm.  In particular, this makes it possible to make control and readout circuits that operate in a correct way, with greater reliability than if these circuits were formed directly in an active layer whose resistivity would have been greatly increased for reasons related to the proper operation of the pixel matrix. In particular, the protective structures against electrostatic discharges will be better controlled. If the pixel array is formed in an epitaxial active layer, an active layer resistivity of 500 to 2000 ohms is preferably selected. cm. If it is formed directly in the upper part of a non-epitaxial silicon substrate (substrate obtained by drawing the ingot and sawing the ingot without epitaxial growth on the sawed edge), the substrate will preferably be given a resistivity of 5,000 to 10,000. ohms. cm.
On notera que l'invention est aussi applicable dans le cas d'un capteur aminci éclairé par sa face arrière, c'est-à-dire un capteur dans lequel la totalité ou la quasi-totalité du substrat de silicium de départ a été éliminée par sa face arrière, ne conservant que la couche active elle-même reportée par sa face avant sur un autre substrat (substrat de report). Dans ce cas, c'est la sensibilité dans le bleu plutôt que dans le proche infrarouge qui peut être améliorée. It will be noted that the invention is also applicable in the case of a thinned sensor illuminated by its rear face, that is to say a sensor in which all or almost all of the starting silicon substrate has been eliminated. by its rear face, retaining only the active layer itself carried by its front face on another substrate (transfer substrate). In that case, it is the sensitivity in blue rather than in the near infrared that can be improved.
D'autres caractéristiques et avantages de l'invention apparaîtront à la lecture de la description détaillée qui suit et qui est faite en référence aux dessins annexés dans lesquels : Other features and advantages of the invention will appear on reading the detailed description which follows and which is given with reference to the appended drawings in which:
- la figure 1 représente schématiquement en vue de dessus un capteur d'image intégré sur silicium comprenant une matrice de pixels et des circuits électroniques extérieurs à la matrice ;  - Figure 1 shows schematically in top view an integrated image sensor on silicon comprising a matrix of pixels and electronic circuits external to the matrix;
- la figure 2 représente un caisson global, diffusé dans une couche de même type de conductivité mais moins dopé, le caisson n'englobant pas la région correspondant à la matrice de pixels ;  FIG. 2 represents a global box, diffused in a layer of the same type of conductivity but less doped, the box not enclosing the region corresponding to the matrix of pixels;
- la figure 3 représente une variante de réalisation dans laquelle le caisson n'englobe ni la matrice, ni un anneau de mise à la masse du substrat entourant la matrice , ni un anneau de protection entourant la matrice ;  FIG. 3 represents an alternative embodiment in which the box does not enclose the matrix, a ring for grounding the substrate surrounding the matrix, or a protection ring surrounding the matrix;
- la figure 4 représente une coupe du capteur à la frontière entre la matrice et le caisson global ;  FIG. 4 represents a section of the sensor at the boundary between the matrix and the overall box;
- la figure 5 représente les courbes d'efficacité quantique en fonction de la longueur d'onde pour un pixel selon l'invention et un pixel de technologie classique.  FIG. 5 represents the quantum efficiency curves as a function of the wavelength for a pixel according to the invention and a pixel of conventional technology.
La figure 1 représente la constitution classique d'un capteur d'image formé sur une puce de circuit intégré IC ; il comprend une matrice MP de lignes et de colonnes de pixels actifs, chaque pixel comprenant une photodiode et des transistors MOS. Les transistors servent à la sélection du pixel, à la commande de début et fin de temps d'intégration, et à la conversion d'une quantité de charges photo générées en un niveau de tension représentant l'éclairement du pixel. A l'extérieur de la matrice, on trouve des circuits électroniques qu'on peut diviser sommairement en deux catégories : des circuits de commande CTRL, et des circuits de lecture RD. Les circuits de commande CTRL comprennent notamment des séquenceurs et des circuits d'adressage des lignes pour la sélection des pixels ligne par ligne, etc. Les circuits de lecture RD comprennent des circuits d'échantillonnage qui recueillent les niveaux de tension analogique produits par les pixels, et des circuits de conversion analogique-numérique ; ils peuvent comprendre aussi d'autres fonctions de traitement de signal. Figure 1 shows the conventional constitution of an image sensor formed on an integrated circuit chip IC; it comprises an MP matrix of rows and columns of active pixels, each pixel comprising a photodiode and MOS transistors. The transistors are used for pixel selection, control of start and end of integration time, and conversion of a quantity of generated photo charges into a voltage level representing the illumination of the pixel. Outside the matrix, there are electronic circuits that can be roughly divided into two categories: control circuits CTRL, and read circuits RD. CTRL control circuits include sequencers and line addressing circuits for line-by-line pixel selection, etc. RD readout circuits include sampling circuits that collect analog voltage levels produced by pixels, and analog-to-digital conversion circuits; they may also include other signal processing functions.
Dans l'art antérieur, le circuit intégré est formé à partir d'un substrat de silicium fortement dopé, de faible résistivité (par exemple de 1 à 50 milliohms.cm), recouvert d'une couche active de silicium monocristallin qui est une couche épitaxiale moins dopée et donc de plus forte résistivité (typiquement de 5 à 30 ohms. cm). On suppose dans la suite que la couche active épitaxiale est de type P, mais elle pourrait être de type N et dans ce cas tous les types de conductivité qui vont maintenant être indiqués doivent être inversés.  In the prior art, the integrated circuit is formed from a highly doped silicon substrate, of low resistivity (for example from 1 to 50 milliohms.cm), covered with an active layer of monocrystalline silicon which is a layer less doped epitaxial and therefore of higher resistivity (typically 5 to 30 ohms cm). It is assumed in the following that the epitaxial active layer is of type P, but it could be of N type and in this case all types of conductivity which will now be indicated must be reversed.
Dans la couche active sont formés :  In the active layer are formed:
- les photodiodes des pixels (diffusion de type N dans la couche active de type P, la diffusion de type N étant le plus souvent recouverte d'une couche superficielle de type P),  the photodiodes of the pixels (N-type diffusion in the P-type active layer, the N-type diffusion being most often covered with a P-type surface layer),
- les autres éléments de circuit du pixel, par exemple les sources et drains de transistors NMOS du pixel,  the other circuit elements of the pixel, for example the sources and drains of NMOS transistors of the pixel,
- les transistors NMOS et d'autres éléments de circuit faisant partie des circuits de commande CTRL et des circuits de lecture RD ; les transistors PMOS des circuits CTRL et RD sont formés dans des caissons individuels (un caisson par transistor) de type N, peu profonds (maximum 1 micromètre de profondeur), diffusés dans la couche active,  the NMOS transistors and other circuit elements forming part of the control circuits CTRL and read circuits RD; the PMOS transistors of the circuits CTRL and RD are formed in individual caissons (a box by transistor) of N type, shallow (maximum 1 micrometer depth), diffused in the active layer,
- les capacités MOS et les diodes.  - MOS capabilities and diodes.
L'épaisseur de la couche active épitaxiale dans la structure de la figure 1 est d'environ 5 à 10 micromètres.  The thickness of the epitaxial active layer in the structure of Figure 1 is about 5 to 10 microns.
Selon l'invention, on prévoit d'abord que les photodiodes sont formées dans une couche active de silicium monocristallin qui a une résistivité beaucoup plus forte que dans l'art antérieur, typiquement une résistivité d'au moins 500 ohms.cm pour la couche épitaxiale, soit au moins 20 à 50 fois plus que dans l'art antérieur. De plus, on prévoit que les circuits de contrôle CTRL et de lecture RD, et plus généralement tous les circuits électroniques situés en dehors du périmètre PR de la matrice de pixels, sont placés dans au moins un caisson global profond DPW de type P (pour une couche active de type P) représenté en zone pointillée sur la figure 2. Ce caisson est plus profond que les caissons individuels de type N des transistors PMOS des circuits. Sa profondeur est de préférence de 2 à 4 micromètres au minimum, en tous cas inférieure ou égale à la profondeur de la couche active épitaxiale. Son dopage, plus élevé que celui de la couche active, est tel qu'il a une résistivité beaucoup plus faible que celle de la couche active ; la résistivité du caisson global DPW est d'au plus 30 ohms. cm et de préférence comprise entre 5 et 10 ohms. cm. Le caisson n'englobe pas la surface de la matrice MP ni même d'une partie de la matrice, c'est-à-dire que les bords du caisson s'arrêtent, si on se dirige de l'extérieur vers l'intérieur de la matrice, avant le périmètre PR de la matrice, comme on le voit sur la figure 2. Le caisson, la couche active et le substrat sont de même type de conductivité, ici P. According to the invention, it is first provided that the photodiodes are formed in an active monocrystalline silicon layer which has a much higher resistivity than in the prior art, typically a resistivity of at least 500 ohms.cm for the layer epitaxial, ie at least 20 to 50 times more than in the prior art. In addition, it is expected that the control circuits CTRL and read RD, and more generally all the electronic circuits located outside the perimeter PR of the pixel matrix, are placed in at least one deep global box DPW P type (for an active layer of type P) shown in dashed area in FIG. 2. This box is deeper than the individual boxes of type N of PMOS transistors of the circuits. Its depth is preferably at least 2 to 4 micrometers, in any case less than or equal to the depth of the active epitaxial layer. Its doping, higher than that of the active layer, is such that it has a resistivity much lower than that of the active layer; the resistivity of the overall box DPW is at most 30 ohms. cm and preferably between 5 and 10 ohms. cm. The box does not cover the surface of the matrix MP or even a part of the matrix, that is to say that the edges of the box stop, if we go from the outside to the inside of the matrix, before the perimeter PR of the matrix, as seen in Figure 2. The box, the active layer and the substrate are of the same type of conductivity, here P.
Les circuits de commande et de lecture CTRL et RD extérieurs à la matrice, ou au moins des portions de ces circuits, sont compris dans le caisson global DPW de type P et les transistors PMOS de ces circuits sont formés dans des caissons individuels de type N moins profonds que le caisson global DPW. Les caissons individuels de type N peuvent avoir une profondeur de 1 micromètre environ. Par caisson global on entend que de larges portions de circuit incluant de nombreux transistors et autres éléments de circuit sont inclus dans un même caisson. La figure 2 montre un seul caisson global, mais on comprend que pour des raisons pratiques on pourrait envisager de subdiviser ce caisson en plusieurs caissons globaux différents, par exemple un caisson global respectif pour les circuits CTRL et un autre pour les circuits RD. Il peut arriver aussi que certains éléments de ces circuits soient formés dans un caisson profond de type N, mais l'invention s'intéresse ici à ceux des éléments de circuit qui sont formés dans un caisson profond de type P de même type que la couche active mais de dopage différent.  The control and reading circuits CTRL and RD external to the matrix, or at least portions thereof, are included in the overall P-type DPW box and the PMOS transistors of these circuits are formed in individual N-type boxes. less deep than the overall DPW box. The individual N type casings may have a depth of about 1 micron. By global box is meant that large circuit portions including many transistors and other circuit elements are included in the same box. Figure 2 shows a single overall box, but it is understood that for practical reasons it could be envisaged to subdivide this box into several different overall boxes, for example a respective overall box for CTRL circuits and another for RD circuits. It may also happen that some elements of these circuits are formed in an N-type deep well, but the invention is concerned here with those of the circuit elements which are formed in a type P deep well of the same type as the layer. active but of different doping.
Dans une première réalisation, la couche active est une couche épitaxiale ; cette couche est formée sur un substrat de silicium qui est une tranche sciée dans un lingot de silicium formé par tirage dans un bain de silicium fondu. La surface de la tranche est polie. La couche épitaxiale est beaucoup moins dopée que le substrat. Ce dernier est de même type de conductivité que la couche active ; il est de préférence de type P fortement dopé. Dans une deuxième réalisation, la couche active n'est pas formée par une couche épitaxiée à la surface du substrat mais elle est formée par la partie supérieure du substrat lui-même constitué par la tranche sciée dans le lingot de silicium ; dans ce cas, la résistivité de la couche active (là encore de même type de conductivité que le substrat) est de préférence encore plus élevée ; elle est d'au moins 2 000 ohms. cm et de préférence supérieure à 5 000 ohms. cm. Le lingot de silicium est préparé avec le faible dopage qui conduit à cette forte résistivité. In a first embodiment, the active layer is an epitaxial layer; this layer is formed on a silicon substrate which is a slice sawn in a silicon ingot formed by drawing in a molten silicon bath. The surface of the slice is polished. The epitaxial layer is much less doped than the substrate. The latter is of the same type of conductivity as the active layer; it is preferably of the heavily doped type P. In a second embodiment, the active layer is not formed by an epitaxial layer on the surface of the substrate but it is formed by the upper part of the substrate itself consisting of the slice sawn in the silicon ingot; in this case, the resistivity of the active layer (again of the same type of conductivity as the substrate) is preferably even higher; it is at least 2,000 ohms. cm and preferably greater than 5,000 ohms. cm. The silicon ingot is prepared with low doping which leads to this high resistivity.
Dans les deux cas, de préférence, comme représenté à la figure 3, la matrice de pixels est entourée de deux anneaux périphériques concentriques AN1 et AN2, et le caisson DPW n'englobe ni la matrice ni ces deux anneaux périphériques. L'anneau intérieur AN1 , plus proche du périmètre PR de la matrice, est constitué d'une diffusion de type P, fortement dopée et reliée électriquement à une masse ; il sert à bien fixer à zéro le potentiel de la couche active dans toute la région de la matrice MP pour constituer un plan de masse. L'anneau extérieur AN2 est une diffusion de type N fortement dopée et relié à un potentiel général d'alimentation positif Vdd ; il sert à créer une zone de déplétion profonde tendant à empêcher des charges parasites de se propager de l'extérieur vers l'intérieur de la région de matrice MP.  In both cases, preferably, as shown in Figure 3, the pixel array is surrounded by two concentric peripheral rings AN1 and AN2, and the DPW box does not encompass the matrix or these two peripheral rings. The inner ring AN1, closer to the perimeter PR of the matrix, consists of a P-type diffusion, strongly doped and electrically connected to a mass; it is used to set the potential of the active layer to zero throughout the region of the matrix MP to form a ground plane. The outer ring AN2 is a strongly doped N-type diffusion and connected to a general positive supply potential Vdd; it serves to create a deep depletion zone tending to prevent parasitic charges from propagating from the outside to the inside of the matrix region MP.
La figure 4 représente une coupe de la structure de capteur selon l'invention, cette coupe étant faite selon la ligne IV-IV de la figure 3, dans la région de la frontière entre la matrice MP et le caisson profond global DPW. La structure comprend un substrat de silicium 10 de type P (supprimé au cours de la fabrication dans le cas d'un capteur aminci éclairé par la face arrière), et une couche active 12 de silicium monocristallin de même type faiblement dopée (P-) à la partie supérieure du substrat. Les anneaux périphériques AN1 de type P+ et AN2 de type N+ sont diffusés à partir de la surface.  FIG. 4 represents a section of the sensor structure according to the invention, this section being taken along line IV-IV of FIG. 3, in the region of the boundary between the matrix MP and the overall deep well DPW. The structure comprises a P-type silicon substrate 10 (suppressed during manufacture in the case of a thinned sensor illuminated by the rear face), and an active layer 12 of monocrystalline silicon of the same low-doped type (P-) at the top of the substrate. Peripheral rings AN1 type P + and AN2 type N + are scattered from the surface.
La matrice de pixels est formée dans la région MP entourée par les anneaux périphériques, en utilisant le silicium de type P- faiblement dopé de la couche active pour former l'anode des photodiodes ; la cathode est formée par une diffusion superficielle de type N dans cette couche active, et cette diffusion peut elle-même être recouverte d'une diffusion superficielle de type P reliée électriquement à l'anode. Les régions de canal des transistors des pixels sont constitués par la couche active (dont le dopage peut être localement ajusté pour régler la tension de seuil). The pixel array is formed in the MP region surrounded by the peripheral rings, using the weakly doped P-type silicon of the active layer to form the anode of the photodiodes; the cathode is formed by an N-type surface diffusion in this active layer, and this diffusion may itself be covered with a P-type surface diffusion electrically connected to the anode. Channel regions of transistors pixels are constituted by the active layer (whose doping can be locally adjusted to adjust the threshold voltage).
Les circuits de lecture RD et de commande CTRL sont formés dans le caisson DPW de type P, extérieur à la matrice et aux anneaux périphériques et beaucoup plus dopé que la couche active. La région de canal des transistors NMOS de ces circuits est constituée par le caisson global DPW (ou par des caissons spécifiques) avec éventuellement un ajustement local du dopage pour régler la tension de seuil ; les transistors PMOS de ces circuits sont formés dans des caissons individuels peu profonds (environ 1 micromètre) de type N, moins profonds que le caisson global, diffusés à partir de la surface du caisson global ; la région de canal de ces transistors PMOS est constituée par les caissons individuels ; là encore, le dopage du canal peut être ajusté pour régler la tension de seuil.  The RD reading and CTRL control circuits are formed in the P-type DPW box, outside the matrix and the peripheral rings and much more doped than the active layer. The channel region of the NMOS transistors of these circuits is constituted by the global box DPW (or by specific boxes) with possibly a local adjustment of the doping to adjust the threshold voltage; the PMOS transistors of these circuits are formed in individual shallow (about 1 micron) N-shaped wells, shallower than the overall well, diffused from the surface of the overall well; the channel region of these PMOS transistors is constituted by the individual boxes; again, channel doping can be adjusted to adjust the threshold voltage.
Dans la première réalisation de l'invention, la couche active de silicium monocristallin est une couche épitaxiale déposée sur un substrat de silicium fortement dopé de même type de conductivité ayant une résistivité de 1 à 20 milliohms.cm. La couche épitaxiale a une profondeur de préférence supérieure à 10 micromètres et de préférence comprise entre 10 et 50 micromètres. Sa résistivité est supérieure à 500 ohms. cm et de préférence comprise entre 500 et 3000 ohms. cm.  In the first embodiment of the invention, the active monocrystalline silicon layer is an epitaxial layer deposited on a heavily doped silicon substrate of the same conductivity type having a resistivity of 1 to 20 milliohms.cm. The epitaxial layer has a depth preferably greater than 10 microns and preferably between 10 and 50 microns. Its resistivity is greater than 500 ohms. cm and preferably between 500 and 3000 ohms. cm.
Dans la deuxième réalisation, dépourvue de couche épitaxiale, la couche active est formée par le substrat de silicium monocristallin lui-même et est de même type de conductivité que le substrat. Dans ce cas, le substrat est faiblement dopé, sa résistivité étant d'au moins 2 000 ohms. cm et de préférence comprise entre 5 000 ohms. cm et 10 000 ohms. cm. L'épaisseur du substrat peut être de 700 micromètres par exemple pour un capteur non aminci.  In the second embodiment, devoid of an epitaxial layer, the active layer is formed by the monocrystalline silicon substrate itself and is of the same type of conductivity as the substrate. In this case, the substrate is weakly doped, its resistivity being at least 2000 ohms. cm and preferably between 5000 ohms. cm and 10,000 ohms. cm. The thickness of the substrate may be 700 microns for example for an unthinned sensor.
Dans les deux réalisations, le capteur d'image peut être du type aminci et éclairé par la face arrière, c'est-à-dire qu'après la formation de la matrice MP et des circuits électroniques sur la face avant de la couche active, le substrat de silicium est collé par cette face avant sur un substrat de report puis la face arrière du substrat de départ est amincie jusqu'à ne conserver que la couche active (épitaxiale ou non) d'une épaisseur de quelques micromètres à quelques dizaines de micromètres. C'est le substrat de report qui assure la tenue mécanique pendant la fabrication et après la fabrication. In both embodiments, the image sensor can be thinned and illuminated by the back side, ie after the formation of the matrix MP and the electronic circuits on the front face of the active layer. , the silicon substrate is bonded by this front face to a transfer substrate and then the rear face of the starting substrate is thinned until only the active layer (epitaxial or non-epitaxial) of a thickness of a few microns to a few tens micrometers. This is the substrate of report which ensures the mechanical resistance during the manufacture and after the manufacture.
Dans le cas d'un éclairement par la face avant, et du fait de la forte résistivité du silicium de la couche active, la zone de déplétion qui se forme naturellement sous les photodiodes est plus profonde, ce qui améliore très sensiblement la collecte des charges électriques générées par les photons en profondeur. Comme les longueurs d'onde les plus grandes auxquelles est sensible le silicium pénètrent plus profondément dans le silicium elles contribuent efficacement à la production d'électrons sans que ces électrons se dispersent dans le substrat vers des pixels voisins. La résolution spatiale en est améliorée. Cela concerne tout particulièrement les longueurs d'onde du proche infrarouge, sachant que le silicium est photosensible dans une gamme de longueurs d'onde allant de 250 nanomètres (proche ultraviolet) à un peu plus de 1050 nanomètres (proche infrarouge). La profondeur de la couche active (dans le cas où elle est constituée par une couche épitaxiale ou dans le cas d'un capteur aminci, est choisie suffisante pour pouvoir capter le plus possible les longueurs d'onde allant de 800 à 1 100 nanomètres ; cette profondeur est alors choisie de préférence supérieure à 15 micromètres et, mieux, supérieure à 30 micromètres, alors que dans l'art antérieur elle est plutôt inférieure à 5 micromètres. Avec une profondeur supérieure à 15 micromètres, ou mieux 30 micromètres, on considère qu'on peut capter une large proportion des photons de longueurs d'onde allant de 800 nanomètres environ à 1 100 nanomètres. In the case of illumination by the front face, and because of the high resistivity of the active layer silicon, the depletion zone which naturally forms under the photodiodes is deeper, which significantly improves the collection of charges. generated by deep photons. As the largest wavelengths to which silicon is sensitive penetrate deeper into the silicon, they effectively contribute to the production of electrons without these electrons dispersing in the substrate to neighboring pixels. The spatial resolution is improved. This particularly concerns near-infrared wavelengths, since silicon is photosensitive in a wavelength range from 250 nanometers (near ultraviolet) to a little more than 1050 nanometers (near infrared). The depth of the active layer (in the case where it is constituted by an epitaxial layer or in the case of a thinned sensor, is chosen sufficient to be able to capture as much as possible the wavelengths ranging from 800 to 1100 nanometers; this depth is then chosen preferably greater than 15 micrometers and better still greater than 30 micrometers, whereas in the prior art it is rather less than 5 micrometers.With a depth greater than 15 micrometers, or better still 30 micrometers, it is considered a large proportion of photons with wavelengths ranging from about 800 nanometers to 1100 nanometers can be captured.
L'aptitude à mesurer la lumière à faible niveau allant du rouge au proche infrarouge est donc meilleure que dans l'art antérieur, ce qui est important pour la vision de nuit, et ceci sans détériorer les qualités des circuits électroniques de contrôle et de lecture. Ces circuits fonctionneraient en effet moins bien s'ils étaient réalisés directement dans un substrat trop résistif. C'est le cas en particulier des circuits de référence de tension, indispensables dans les circuits électroniques du capteur, qui ne fonctionneraient pas bien s'ils étaient formés directement dans une couche active de résistivité supérieure à 500 ohms. cm. Cela peut être aussi le cas de résistances formées dans le substrat ou de capacités dont une armature est formée par le substrat et dont le diélectrique est lié à la déplétion du substrat, de transistors bipolaires, etc. The ability to measure light at a low level ranging from red to near infrared is therefore better than in the prior art, which is important for night vision, and without deteriorating the qualities of the electronic control and reading circuits. . These circuits would indeed work less well if they were made directly in a substrate too resistive. This is particularly the case for voltage reference circuits, which are indispensable in the electronic circuits of the sensor, which would not work well if they were formed directly in an active resistivity layer greater than 500 ohms. cm. This can also be the case of resistances formed in the substrate or capacities including a reinforcement is formed by the substrate and whose dielectric is related to the depletion of the substrate, bipolar transistors, etc.
La figure 5 donne à titre d'illustration une courbe en traits pleins représentant l'efficacité quantique pour un pixel selon l'invention de 5,3 micromètres de côté éclairé par la face avant et recouvert d'une microlentille. Par comparaison, la courbe en traits pointillés représente l'efficacité quantique pour un pixel semblable mais de technologie standard.  FIG. 5 gives as an illustration a curve in solid lines representing the quantum efficiency for a pixel according to the invention of 5.3 micrometers of side illuminated by the front face and covered with a microlens. By comparison, the dotted line curve represents the quantum efficiency for a similar pixel but of standard technology.

Claims

REVENDICATIONS
1 . Capteur d'image formé sur une puce de circuit intégré (IC) à partir d'un substrat de silicium (12) d'un premier type de conductivité, comprenant : 1. An image sensor formed on an integrated circuit (IC) chip from a silicon substrate (12) of a first conductivity type, comprising:
- une matrice (MP) de lignes et colonnes de pixels actifs comprenant chacun au moins une photodiode et des transistors formés dans une couche active de silicium monocristallin du premier type de conductivité formée à la surface du substrat,  a matrix (MP) of rows and columns of active pixels each comprising at least one photodiode and transistors formed in an active monocrystalline silicon layer of the first conductivity type formed on the surface of the substrate,
- des circuits (CTRL) de commande de la matrice, extérieurs à la matrice, et des circuits (RD) de lecture de signal, extérieurs à la matrice, ce capteur étant caractérisé en ce que la couche active (10) de silicium monocristallin a une résistivité d'au moins 500 ohms. cm si cette couche active est une couche épitaxiée en contact avec le substrat de silicium du premier type de conductivité et d'au moins 2 000 ohms. cm si cette couche active est constituée par la partie supérieure du substrat de silicium, et en ce que les circuits de commande (CTRL) et les circuits de lecture (RD) sont formés dans au moins un caisson global dopé (DPW), de même type que la couche active de silicium monocristallin et ayant une résistivité inférieure ou égale à 30 ohms. cm, ce caisson étant formé dans la couche active et n'incluant pas la matrice de pixels.  matrix control circuits (CTRL) external to the matrix and signal reading circuits (RD) external to the matrix, this sensor being characterized in that the active layer (10) of monocrystalline silicon has a resistivity of at least 500 ohms. cm if this active layer is an epitaxial layer in contact with the silicon substrate of the first conductivity type and at least 2000 ohms. cm if this active layer is constituted by the upper part of the silicon substrate, and in that the control circuits (CTRL) and the reading circuits (RD) are formed in at least one doped overall box (DPW), and type as the active monocrystalline silicon layer and having a resistivity of less than or equal to 30 ohms. cm, this box being formed in the active layer and not including the matrix of pixels.
2. Capteur d'image selon la revendication 1 , caractérisé en ce que le caisson a une profondeur d'environ 2 à 5 micromètres à partir de la surface de la couche active. An image sensor according to claim 1, characterized in that the box has a depth of about 2 to 5 micrometers from the surface of the active layer.
3. Capteur d'image selon l'une des revendications 1 et 2, caractérisé en ce que la couche active de silicium monocristallin est une couche épitaxiale de résistivité comprise entre 500 et 2 000 ohms. cm. 3. Image sensor according to one of claims 1 and 2, characterized in that the active monocrystalline silicon layer is an epitaxial layer of resistivity between 500 and 2000 ohms. cm.
4. Capteur d'image selon la revendication 3, caractérisé en ce que l'épaisseur de la couche épitaxiale est comprise entre 10 micromètres et 50 micromètres. 4. An image sensor according to claim 3, characterized in that the thickness of the epitaxial layer is between 10 micrometers and 50 micrometers.
5. Capteur d'image selon l'une des revendications 1 et 2, caractérisé en ce que la couche active est constituée par la partie supérieure d'un substrat de silicium non épitaxié de résistivité comprise entre 5 000 et 10 000 ohms.cm. 5. An image sensor according to one of claims 1 and 2, characterized in that the active layer is constituted by the upper part of a non-epitaxial silicon substrate with a resistivity of between 5,000 and 10,000 ohms.cm.
6. Capteur d'image selon l'une des revendications 1 à 5, destiné à un éclairement par la face arrière, dans lequel la totalité ou la quasi-totalité du substrat de silicium de départ, sur la couche active duquel a été réalisée la matrice de pixels, a été éliminé par sa face arrière, ne conservant que la couche active elle-même reportée par sa face avant sur un autre substrat. 6. An image sensor according to one of claims 1 to 5, for an illumination by the rear face, in which all or almost all of the starting silicon substrate, on the active layer of which has been realized the matrix of pixels, was eliminated by its rear face, retaining only the active layer itself carried by its front face on another substrate.
EP13776834.7A 2012-10-18 2013-10-16 Image sensor having improved quantum efficiency at large wavelengths Withdrawn EP2909861A1 (en)

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