EP2901294A4 - Protocole de socket de réseau sur puce - Google Patents

Protocole de socket de réseau sur puce

Info

Publication number
EP2901294A4
EP2901294A4 EP13842232.4A EP13842232A EP2901294A4 EP 2901294 A4 EP2901294 A4 EP 2901294A4 EP 13842232 A EP13842232 A EP 13842232A EP 2901294 A4 EP2901294 A4 EP 2901294A4
Authority
EP
European Patent Office
Prior art keywords
network
chip socket
socket protocol
protocol
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP13842232.4A
Other languages
German (de)
English (en)
Other versions
EP2901294A1 (fr
Inventor
Philippe Boucard
Jean-Jacques Lecler
Boris Boutillier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Technologies Inc
Original Assignee
Qualcomm Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/626,758 external-priority patent/US9471538B2/en
Priority claimed from US13/626,766 external-priority patent/US9225665B2/en
Application filed by Qualcomm Technologies Inc filed Critical Qualcomm Technologies Inc
Priority to EP22196229.3A priority Critical patent/EP4123468A1/fr
Publication of EP2901294A1 publication Critical patent/EP2901294A1/fr
Publication of EP2901294A4 publication Critical patent/EP2901294A4/fr
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/403—Bus networks with centralised control, e.g. polling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/1735—Network adapters, e.g. SCI, Myrinet
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7825—Globally asynchronous, locally synchronous, e.g. network on chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Computer And Data Communications (AREA)
EP13842232.4A 2012-09-25 2013-09-24 Protocole de socket de réseau sur puce Ceased EP2901294A4 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP22196229.3A EP4123468A1 (fr) 2012-09-25 2013-09-24 Protocole de socket de réseau sur puce

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/626,758 US9471538B2 (en) 2012-09-25 2012-09-25 Network on a chip socket protocol
US13/626,766 US9225665B2 (en) 2012-09-25 2012-09-25 Network on a chip socket protocol
PCT/US2013/061295 WO2014052261A1 (fr) 2012-09-25 2013-09-24 Protocole de socket de réseau sur puce

Related Child Applications (1)

Application Number Title Priority Date Filing Date
EP22196229.3A Division EP4123468A1 (fr) 2012-09-25 2013-09-24 Protocole de socket de réseau sur puce

Publications (2)

Publication Number Publication Date
EP2901294A1 EP2901294A1 (fr) 2015-08-05
EP2901294A4 true EP2901294A4 (fr) 2016-08-10

Family

ID=50388890

Family Applications (2)

Application Number Title Priority Date Filing Date
EP22196229.3A Pending EP4123468A1 (fr) 2012-09-25 2013-09-24 Protocole de socket de réseau sur puce
EP13842232.4A Ceased EP2901294A4 (fr) 2012-09-25 2013-09-24 Protocole de socket de réseau sur puce

Family Applications Before (1)

Application Number Title Priority Date Filing Date
EP22196229.3A Pending EP4123468A1 (fr) 2012-09-25 2013-09-24 Protocole de socket de réseau sur puce

Country Status (6)

Country Link
EP (2) EP4123468A1 (fr)
JP (1) JP6144348B2 (fr)
KR (1) KR101690568B1 (fr)
CN (1) CN104685480B (fr)
IN (1) IN2015MN00441A (fr)
WO (1) WO2014052261A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2529217A (en) * 2014-08-14 2016-02-17 Advanced Risc Mach Ltd Transmission control checking for interconnect circuitry
US11436185B2 (en) * 2019-11-15 2022-09-06 Arteris, Inc. System and method for transaction broadcast in a network on chip
CN117389931B (zh) * 2023-12-12 2024-05-03 芯动微电子科技(武汉)有限公司 适用于总线访问gpu核内存储器的协议转换模块及方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6826191B1 (en) * 1999-10-01 2004-11-30 Stmicroelectronics Ltd. Packets containing transaction attributes

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6477646B1 (en) * 1999-07-08 2002-11-05 Broadcom Corporation Security chip architecture and implementations for cryptography acceleration
US8087064B1 (en) * 2000-08-31 2011-12-27 Verizon Communications Inc. Security extensions using at least a portion of layer 2 information or bits in the place of layer 2 information
WO2002069575A1 (fr) * 2001-02-28 2002-09-06 Gotham Networks, Inc. Procedes et systeme utiles pour dispositif de routage de reseau
US6996651B2 (en) * 2002-07-29 2006-02-07 Freescale Semiconductor, Inc. On chip network with memory device address decoding
US7277449B2 (en) * 2002-07-29 2007-10-02 Freescale Semiconductor, Inc. On chip network
US6671275B1 (en) 2002-08-02 2003-12-30 Foundry Networks, Inc. Cross-point switch with deadlock prevention
CN100342370C (zh) * 2002-10-08 2007-10-10 皇家飞利浦电子股份有限公司 用于交换数据的集成电路和方法
US7181556B2 (en) * 2003-12-23 2007-02-20 Arm Limited Transaction request servicing mechanism
EP1735712A1 (fr) * 2004-03-26 2006-12-27 Koninklijke Philips Electronics N.V. Circuit integre et procede d'abandon d'une transaction
US7716409B2 (en) * 2004-04-27 2010-05-11 Intel Corporation Globally unique transaction identifiers
WO2007033363A2 (fr) * 2005-09-13 2007-03-22 Ist International, Inc. Systeme et procede permettant d'obtenir une connectivite par paquets entre des reseaux heterogenes
CN101379841A (zh) * 2005-09-13 2009-03-04 Ist国际公司 为提供异种网络之间的小包连通性和组分和小包之系统和方法
US20070245033A1 (en) * 2006-04-14 2007-10-18 Microsoft Corporation Link layer discovery and diagnostics
CN101501651A (zh) * 2006-08-08 2009-08-05 皇家飞利浦电子股份有限公司 电子设备和控制通信的方法
US8285912B2 (en) * 2009-08-07 2012-10-09 Arm Limited Communication infrastructure for a data processing apparatus and a method of operation of such a communication infrastructure
FR2951342B1 (fr) * 2009-10-13 2017-01-27 Arteris Inc Reseau sur puce a latence nulle
EP2333830B1 (fr) * 2009-12-07 2014-09-03 STMicroelectronics (Research & Development) Limited Un ensemble comprenant une première et une seconde matrice couplées par un bus multiplexé
EP2388707B1 (fr) * 2010-05-20 2014-03-26 STMicroelectronics (Grenoble 2) SAS Procédé et dispositif d'interconnexion, par exemple pour des systèmes sur puce
WO2011148925A1 (fr) * 2010-05-24 2011-12-01 日本電気株式会社 Dispositif semi-conducteur et procédé et système d'acheminement des données
FR2961048B1 (fr) 2010-06-03 2013-04-26 Arteris Inc Reseau sur puce avec caracteristiques de qualite-de-service
EP2444903A1 (fr) * 2010-09-29 2012-04-25 STMicroelectronics (Grenoble 2) SAS Agencement de réordonnancement

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6826191B1 (en) * 1999-10-01 2004-11-30 Stmicroelectronics Ltd. Packets containing transaction attributes

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
MASOUD DANESHTALAB ET AL: "A Low-Latency and Memory-Efficient On-chip Network", NETWORKS-ON-CHIP (NOCS), 2010 FOURTH ACM/IEEE INTERNATIONAL SYMPOSIUM ON, IEEE, PISCATAWAY, NJ, USA, 3 May 2010 (2010-05-03), pages 99 - 106, XP031707260, ISBN: 978-1-4244-7085-3 *
See also references of WO2014052261A1 *
SEIFI M R ET AL: "A clustered NOC in group communication", TENCON 2008 - 2008, TENCON 2008. IEEE REGION 10 CONFERENCE, IEEE, PISCATAWAY, NJ, USA, 19 November 2008 (2008-11-19), pages 1 - 5, XP031414565, ISBN: 978-1-4244-2408-5 *
WOO-CHEOL KWON ET AL: "In-network reorder buffer to improve overall NoC performance while resolving the in-order requirement problem", DESIGN, AUTOMATION&TEST IN EUROPE CONFERENCE&EXHIBITION, 2009. DATE '09, IEEE, PISCATAWAY, NJ, USA, 20 April 2009 (2009-04-20), pages 1058 - 1063, XP032317643, ISBN: 978-1-4244-3781-8, DOI: 10.1109/DATE.2009.5090821 *
XU YANG, ZHANG QING LI, FU FANG-FA , YU MING-YAN, LIU CHENG: "NISAR: An AXI Compliant On-chip NI Architecture OfferingTransaction Reordering Processing", 25 October 2007 (2007-10-25), XP002759391, Retrieved from the Internet <URL:http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4415774> [retrieved on 20160630] *

Also Published As

Publication number Publication date
CN104685480B (zh) 2017-07-14
CN104685480A (zh) 2015-06-03
KR101690568B1 (ko) 2016-12-28
IN2015MN00441A (fr) 2015-09-11
KR20150063433A (ko) 2015-06-09
JP6144348B2 (ja) 2017-06-07
EP4123468A1 (fr) 2023-01-25
EP2901294A1 (fr) 2015-08-05
JP2015535991A (ja) 2015-12-17
WO2014052261A1 (fr) 2014-04-03

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