EP2891168B1 - Agencement de circuit d'excitation d'un relais bistable - Google Patents

Agencement de circuit d'excitation d'un relais bistable Download PDF

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Publication number
EP2891168B1
EP2891168B1 EP13753170.3A EP13753170A EP2891168B1 EP 2891168 B1 EP2891168 B1 EP 2891168B1 EP 13753170 A EP13753170 A EP 13753170A EP 2891168 B1 EP2891168 B1 EP 2891168B1
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EP
European Patent Office
Prior art keywords
voltage
series
circuit arrangement
relay
output
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Active
Application number
EP13753170.3A
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German (de)
English (en)
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EP2891168A1 (fr
Inventor
Matthias Lück
Gerd Wollenhaupt
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SMA Solar Technology AG
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SMA Solar Technology AG
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Publication of EP2891168A1 publication Critical patent/EP2891168A1/fr
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01HELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H47/00Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current
    • H01H47/22Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current for supplying energising current for relay coil
    • H01H47/226Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current for supplying energising current for relay coil for bistable relays
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01HELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H47/00Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current
    • H01H47/22Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current for supplying energising current for relay coil
    • H01H47/32Energising current supplied by semiconductor device
    • H01H47/325Energising current supplied by semiconductor device by switching regulator
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01HELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H47/00Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current
    • H01H47/002Monitoring or fail-safe circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01HELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H50/00Details of electromagnetic relays
    • H01H50/44Magnetic coils or windings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01HELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H50/00Details of electromagnetic relays
    • H01H50/64Driving arrangements between movable part of magnetic circuit and contact
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01HELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H47/00Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current
    • H01H47/22Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current for supplying energising current for relay coil
    • H01H47/32Energising current supplied by semiconductor device

Definitions

  • the invention relates to a circuit arrangement for driving a bistable relay, wherein a coil of the bistable relay is arranged in a series circuit with a capacitor, wherein the series circuit for switching on the bistable relay via a first semiconductor switch is connected to a supply voltage and to turn off the relay via a second semiconductor switch is shorted.
  • Bistable relays are preferably used when both switching states - switched on and off - are taken for a longer period of time. Instead of a permanent energization of a coil of the relay in a monostable relay energization is only required for the period of switching between the switching states in the bistable relay.
  • a relay is generally understood to mean an electromagnetically operated switching device, that is to say a low-power relay as well as a DC or AC contactor designed for higher powers.
  • bistable relay occupies a defined switching state when the supply voltage fails
  • the bistable relay is common, such as in the document JP S57 60 632 A is described, arranged in the aforementioned series connection with a capacitor.
  • the energy stored in the capacitor can be used to bring the relay into a defined switching state, usually in the off state.
  • capacitor usually an electrolytic capacitor is used.
  • the above-mentioned circuit arrangement can be suitable for such a bistable relay, in which the switching on or off of the relay via power surges of different polarity by a single coil of the relay, hereinafter called relay coil, takes place or for a bistable relay, in each case one separate relay coil for the on or off is present.
  • the publication US 4,533,972 shows a circuit arrangement for driving a bistable relay, wherein a capacitor is provided in series with a relay coil. There is provided a voltage stabilization of the voltage applied to the series circuit. In this way, the relay coil can be protected from fluctuations in the supply voltage, but it is also here a capacitor with a correspondingly high capacitance in series with the relay coil needed.
  • At least one voltage regulator is provided, which regulates the voltage applied to the relay coil of the bistable relay voltage so that it does not exceed a predetermined voltage.
  • the voltage applied to the relay coil voltage is controlled so that it does not exceed a predetermined voltage
  • the voltage applied directly to the relay coil is limited. Due to the limitation of the voltage across the relay coil flows due to the given internal resistance of the relay coil according to a limited in its height current through the relay coil. Thus, the current flow through the capacitor is limited, since this is largely given by the current flowing through the relay coil current. Due to the limited current flow in the capacitor, the time constant during charging or discharging of the capacitor is also limited, whereby the duration of the current surge is extended by the relay coil with respect to a circuit arrangement without the at least one voltage regulator.
  • the relay coil for switching on or off the relay on the one in its voltage level, so that damage to the relay coil can be prevented, and on the other hand extends the duration of the surge to actuate the relay at the same capacity of the capacitor.
  • the capacitance of the capacitor can be chosen smaller than in a circuit arrangement without the at least one voltage regulator.
  • the first and the second semiconductor switch can each be separate elements. Alternatively it is possible to implement the function of the first and / or second semiconductor switch by switching elements of the at least one voltage regulator.
  • a first and / or second voltage regulator are provided, each having an input, an output and a control connection, wherein at the voltage controlled output relative to the control connection sets a voltage whose absolute value does not exceed a predetermined voltage, and wherein the Input with the first and second semiconductor switches and the output and the control terminal are each connected to an output terminal for the relay coil.
  • the first or second voltage regulator in each case has a series transistor whose control input is connected in each case via a series circuit of a Zener diode and a diode to the control terminal and is connected in each case via a resistor to the input.
  • the diode and the Zener diode are connected antiserially to one another within their series connection.
  • the series transistors of the first and of the second voltage regulator are complementary to one another, in particular NPN or PNP bipolar transistors or n-channel or p-channel MOSFETs.
  • Fig. 1 shows a circuit arrangement for driving a bistable relay in a first embodiment in a schematic representation.
  • the circuit arrangement has a connection 11 for a positive supply voltage of V +, a connection 12 (ground connection, GND ground) and a control input 13. Parallel to the terminal 11 and the ground terminal 12, a smoothing capacitor 8 is arranged.
  • the bistable relay is connected to its coil 1, hereafter referred to as relay coil 1, via a first output terminal 14 and a second output terminal 15 connected to the circuit arrangement.
  • the relay switches depending on a level at the control input 13 and depending on whether the terminal 11 for the supply voltage V + with respect to the ground terminal 12 is at least applied to a predetermined minimum voltage.
  • a discriminator 10 For monitoring the magnitude of the supply voltage V +, a discriminator 10 is provided which outputs a logic signal at an output. If the level of the supply voltage reaches or exceeds the minimum voltage, a signal with the logic level "1" is present at the output of the discriminator 10, otherwise a signal with the logic level "0".
  • the output of the discriminator 10 is connected to an input of a logic module 9, the control input 13 to a further input of this logic module 9.
  • the logic module 9 is designed as a NAND gate, so that at its output only a signal of logic "0" is applied , if both inputs are at logical "1".
  • the relay turns on (is set) when the output of the logic device 9 is a signal of logic "0".
  • a signal of logic "1" at the output of the logic module 9 switches the bistable relay off (will reset).
  • the relay is thus set when both a supply voltage V + of sufficient level (greater than or equal to the minimum voltage) is present, as well as the control input 13 with a logic level of logic "1" is applied.
  • the relay is reset.
  • a reverse switching logic can be realized. It can be provided that the logic signals assume levels in accordance with the TTL logic.
  • voltage values of other common logic levels such. B. LVTTL, CMOS 1.8V, CMOS 2.5V or CMOS 5V to control the relay at the control input 13 possible.
  • the relay coil 1 is connected in series with a capacitor 2.
  • the capacitor 2 is arranged between the second output terminal 15 and the ground terminal 12.
  • the first output terminal 14 is connected via a first voltage regulator 100 and a first semiconductor switch 5 to the terminal 11 for the positive supply voltage V +.
  • the first semiconductor switch 5 is designed in this embodiment as a MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) whose control input (gate terminal) via a resistor 6 is also connected to the terminal 11 for the positive supply voltage V +.
  • the gate terminal of the first semiconductor switch 5 via the switching path of another semiconductor switch 3, here also a MOSFET, connected to the output of the logic device 9.
  • the control terminal (gate terminal) of the further semiconductor switch 3 is held by a reference voltage source 4 at a predetermined potential relative to the ground potential GND. The predetermined potential is chosen so that the semiconductor switch 3 blocks at a logic level of logic "1" at the output of the logic device 9 and conducts at a logic level of logic "0".
  • the first voltage regulator 100 is arranged. This has an input 111, with which it is connected to the first semiconductor switch 5 and an output 112, with which it is connected via the first output terminal 14 to the relay coil 1. In addition, it has a control input 113, with which it is also connected via the second output terminal 15 to the relay coil 1.
  • the first voltage regulator 100 is designed as a series regulator, with a series transistor 101, which is arranged with its switching path between the input 111 and the output 112. In the present case, the series transistor 101 is an NPN bipolar transistor.
  • the control input (base) of the series transistor 101 is connected via a resistor 104 to the input 111 and via a series circuit of a Zener diode 102 and a diode 103 to the control input 113.
  • the series transistor 101 of the first voltage regulator 100 is turned on and the first output terminal 14 for the relay coil 1 is subjected to a positive potential.
  • the function of the first semiconductor switch 5 can also be taken over by the voltage regulator 100, specifically by a semiconductor switch of the voltage regulator 100, in particular the series transistor 101. It is possible, for example, to connect the control input of the series transistor 101 to the output of the logic module 9 and to control it such that the series transistor 101 only becomes conductive and is used for regulation when the output of the transistor Logic module 9 has a level of logic "0".
  • the control of the series transistor can optionally via other switching elements, such as diodes and / or one or more small power transistors, carried out to combine the switching function with the control function.
  • one of the current through the relay coil 1 leading transistors can be saved.
  • the first output terminal 14 for the relay coil 1 is further connected via a second voltage regulator 200 and a second semiconductor switch 7 to ground potential GND.
  • the second voltage regulator 200 likewise has a series transistor 201 whose switching path extends from an input 211 of the second voltage regulator 200 to an output 212 which is connected to the first output terminal 14 for the relay coil 1.
  • a control input 213 is connected to the second output terminal 15 for the relay coil 1.
  • the second voltage regulator 200 is constructed in mirror image symmetry with respect to the first voltage regulator 100 and is designed to regulate an output voltage 212 which is negative in relation to the control feed 213 in its height. Accordingly, a PNP transistor complementary to the series transistor 101 is used as the series transistor 201.
  • the second semiconductor switch 7 is a MOSFET whose control input (gate connection) is connected to the output of the logic module 9 of the circuit arrangement.
  • the voltage applied to the relay coil 1 is regulated by the first and second voltage regulators 100, 200 so that their absolute value does not exceed a predetermined voltage.
  • the second semiconductor switch 7 With a potential of logic "0" at the output of the logic module 9, the second semiconductor switch 7 is opened and corresponding to the series transistor 201 of the second voltage regulator 200 non-conductive.
  • the second voltage regulator 200 can be disregarded.
  • the capacitor 2 Accordingly flows due to the switched first semiconductor switch 5 and the conductive series transistor 101 of the first voltage regulator 100, a current flow through the relay coil 1 and the capacitor 2, on the one hand, the relay turns on and on the other, the capacitor 2 is charged.
  • the voltage applied between the first and the second output connection 14, 15 and therefore directly to the relay coil 1 is regulated by the first voltage regulator 100 such that it does not exceed a voltage predetermined by the zener diode 102 and the diode 103.
  • Due to the limitation of the voltage across the relay coil 1 flows due to the given internal resistance of the relay coil 1 in accordance with a limited in its height current through the relay coil 1. Accordingly, the current flow through the capacitor 2 is limited, as this largely by the relay coil 1 flowing stream is given.
  • the limited current flow in the capacitor 2 leads in these situations to a deviation from the exponential charging characteristic towards a delayed or current-limited charging of the capacitor 2. This results in a greater over the charging time of the capacitor 2 averaged "effective time constant", whereby the duration of the Power surge is extended by the relay coil 1 with respect to a circuit arrangement without the first voltage regulator.
  • the current impulse is limited by the relay coil 1 to turn on the relay on the one hand in its voltage level, so that damage to the relay coil 1 can be prevented, and on the other hand, the duration of the surge to turn on the relay extended at the same capacity of the capacitor.
  • the capacitance of the capacitor 2 can be selected smaller than in the case of a circuit arrangement without a first voltage regulator 100.
  • the diode 203 of the second voltage regulator 200 prevents a current flow via the control input 213 of the second voltage regulator 200.
  • the voltage level is higher than that of the reference voltage source 4, lock the other semiconductor switch 3 and the first semiconductor switch 5.
  • the second semiconductor switch 7 is conductive and thus also the series transistor 201 of second voltage regulator 200.
  • the capacitor 2 was due to the previous switching action (ie, the level at the output of the logic device 9 of logic "0" corresponds) almost charged to the value of the supply voltage V +.
  • the charge stored in the capacitor 2 now discharges correspondingly via the second voltage regulator 200 and the relay coil 1.
  • the diode 103 of the first voltage regulator 100 prevents a flow of current from the capacitor 2 via the regulating connection 113.
  • the current flowing through the relay coil 1 impulse is of opposite polarity as when switching on the relay and turns it off accordingly.
  • the surge is limited in the amount of current and extended accordingly in its duration is.
  • the series transistor 201 of the second voltage regulator 200 may be directly and not via the second semiconductor switch 7 to be connected to the ground terminal 12, wherein the resistor 204 used in the voltage divider at the base of the series transistor 201, however, is still connected via the second semiconductor switch 7 to the ground terminal 12.
  • the function of the first semiconductor switch 5 is taken over by the series transistor 101 of the first voltage regulator 100
  • the function of the second semiconductor switch 7 can be taken over by the second series transistor 201 of the second voltage regulator 200 with suitable control.
  • Fig. 2 shows an alternative embodiment of the circuit according to Fig. 1
  • the present circuit arrangement is suitable for driving a bistable relay with two relay coils 1a, 1b.
  • the relay is set in a current surge through a first of the two relay coils, for example, the relay coil 1a, and at a surge through the second of the two relay coils, for example, the relay coil 1b, reset.
  • Both relay coils 1a, 1b are connected to one of their terminals together with the second output terminal 15 of the circuit arrangement.
  • the other terminal of the first relay coil 1a is connected to the output 112 of the first voltage regulator 100 and the other terminal of the second relay coil 1b is connected to the output 212 of the second voltage regulator 200.
  • the two terminals 112, 212 are not directly connected to each other, corresponding to two first output terminals 14a, 14b are provided to connect the relay coils 1a, 1b to the circuit arrangement.
  • a surge to set the relay is supplied to the relay coil 1a, a surge to reset the relay coil 1b.
  • the voltage applied to the relay coils 1a, 1b is limited in their height both when setting and when resetting by the voltage regulator 100 or 200.
  • Fig. 3 shows a second embodiment of a circuit arrangement for driving a bistable relay.
  • Like reference numerals in this embodiment denote the same or equivalent elements as in the first embodiment.
  • the circuit in the second embodiment substantially corresponds to that of the first embodiment, the description of which reference is hereby made.
  • the circuit arrangement shown is also used for the first and the second voltage regulator 100, 200 MOSFETs as series transistors 101 and 201.
  • complementary series transistors 101, 201 are used, in this case an n-channel MOSFET as a series transistor 101 of the first voltage regulator 100, and a p-channel MOSFET as a series transistor 201 of the second voltage regulator 200.
  • resistors 105, 205 originating from the first output terminal 14 are each connected to the control input (gate). Terminal) of the series transistors 101, 201.
  • These resistors can be very high-impedance and do not affect the other functionality of the circuit arrangement.
  • the resistors 105, 205 omitted even when using MOSFET transistors as series transistors 101, 201.

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Relay Circuits (AREA)
  • Direct Current Feeding And Distribution (AREA)

Claims (11)

  1. Disposition de circuit pour le contrôle d'un relais bistable, dans laquelle une bobine de relais (1, 1a, 1b) du relais bistable est branchée en série avec un condensateur (2), le branchement en série étant relié, pour l'activation du relais bistable, par l'intermédiaire d'un premier commutateur semi-conducteur (5), avec une tension d'alimentation (V+) et, pour la désactivation du relais bistable, court-circuité au moyen d'un deuxième commutateur semi-conducteur (7), caractérisée en ce qu'au moins un régulateur de tension (100, 200) est prévu, lequel régule la tension appliquée à la bobine de relais (1, 1a, 1b) du relais bistable de façon à ce qu'elle ne dépasse pas une tension prédéterminée, un premier régulateur de tension (100) étant prévu, lequel comprend une entrée (111), une sortie (112) et un raccordement de régulation (113), une tension apparaissant au niveau de la sortie régulée en tension (112) par rapport au raccordement de régulation (113), dont la valeur absolue ne dépasse pas une tension prédéterminée, l'entrée (111) étant reliée avec le premier commutateur semi-conducteur (5) et la sortie (112) et le raccordement de régulation (113) étant reliés chacun avec un raccordement de sortie (14, 15) pour la bobine de relais (1, 1a, 1b).
  2. Disposition de circuit selon la revendication 1, dans laquelle le premier régulateur de tension (100) comprend un transistor à passage direct (101) dont l'entrée de commande est reliée avec le raccordement de régulation (113) par l'intermédiaire d'un branchement en série d'une diode Zener (102) et d'une diode (103) et est reliée avec l'entrée (111) par l'intermédiaire d'une résistance (104).
  3. Disposition de circuit selon la revendication 2, dans laquelle la diode (103) et la diode Zener (102) sont branchées entre elles de manière anti-sérielle à l'intérieur de leur branchement en série.
  4. Disposition de circuit selon l'une des revendications 1 à 3, dans laquelle un deuxième régulateur de tension (200) est prévu, lequel comprend une entrée (211), une sortie (212) et un raccordement de régulation (213), une tension apparaissant au niveau de la sortie régulée en tension (212) par rapport au raccordement de régulation (213), dont la valeur absolue ne dépasse pas une tension prédéterminée et l'entrée (211) étant reliée avec le raccordement à la masse (12) et la sortie (212) et le raccordement de régulation (213) étant reliés chacun avec un des raccordements de sortie (14, 15) de la bobine de relais (1, 1a, 1b).
  5. Disposition de circuit selon la revendication 4, dans laquelle le deuxième régulateur de tension (200) comprend un transistor à passage direct (201), dont l'entrée de commande est reliée avec le raccordement de régulation (213) par l'intermédiaire d'un branchement en série d'une diode Zener (202) et d'une diode (203) et est reliée avec l'entrée (211) par l'intermédiaire d'une résistance (204), l'entrée (211) étant reliée par l'intermédiaire du deuxième commutateur semi-conducteur (7) avec le raccordement à la masse (12).
  6. Disposition de circuit selon la revendication 4, dans laquelle le deuxième régulateur de tension (200) comprend un transistor à passage direct (201), dont l'entrée de commande est reliée avec le raccordement de régulation (213) par l'intermédiaire d'un branchement en série d'une diode Zener (202) et d'une diode (203) et est reliée avec le deuxième commutateur semi-conducteur (7) par l'intermédiaire d'une résistance (204) .
  7. Disposition de circuit selon la revendication 5 ou 6, dans laquelle la diode (203) et la diode Zener (202) sont branchées, à l'intérieur de leur branchement en série, de manière anti-sérielle entre elles.
  8. Disposition de circuit selon l'une des revendications 5 à 7, dans laquelle l'anode de la diode Zener (102) est reliée par l'intermédiaire du raccordement de sortie (15) pour la bobine de relais (1, 1a, 1b) avec la cathode de la diode Zener (202).
  9. Disposition de circuit selon l'une des revendications 5 à 7, dans laquelle la cathode de la diode (103) est reliée par l'intermédiaire du raccordement de sortie (15) pour la bobine de relais (1, 1a, 1b) avec l'anode de la diode (203).
  10. Disposition de circuit selon l'une des revendications 5 à 7, dans laquelle le transistor à passage direct (101) du premier régulateur de tension (100) et le transistor à passage direct (201) du deuxième régulateur de tension (200) sont de types complémentaires entre eux, plus particulièrement des transistors bipolaires NPN ou PNP ou des MOSFET à canal n ou à canal p.
  11. Disposition de circuit selon l'une des revendications 1 à 10, dans laquelle les premier et deuxième commutateurs semi-conducteurs (5, 7) sont reliés avec une entrée de commande (13) de la disposition de circuit de façon à ce qu'ils soient conducteurs ou bloqués de manière inverse entre eux en fonction d'un niveau d'entrée numérique au niveau de l'entrée de commande (13).
EP13753170.3A 2012-08-29 2013-08-21 Agencement de circuit d'excitation d'un relais bistable Active EP2891168B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102012107953.6A DE102012107953B3 (de) 2012-08-29 2012-08-29 Schaltungsanordnung zum Ansteuern eines bistabilen Relais
PCT/EP2013/067378 WO2014033029A1 (fr) 2012-08-29 2013-08-21 Agencement de circuit d'excitation d'un relais bistable

Publications (2)

Publication Number Publication Date
EP2891168A1 EP2891168A1 (fr) 2015-07-08
EP2891168B1 true EP2891168B1 (fr) 2019-07-31

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ID=49035584

Family Applications (1)

Application Number Title Priority Date Filing Date
EP13753170.3A Active EP2891168B1 (fr) 2012-08-29 2013-08-21 Agencement de circuit d'excitation d'un relais bistable

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US (1) US9870889B2 (fr)
EP (1) EP2891168B1 (fr)
DE (1) DE102012107953B3 (fr)
WO (1) WO2014033029A1 (fr)

Families Citing this family (5)

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Publication number Priority date Publication date Assignee Title
CN103996567B (zh) * 2014-05-27 2016-06-22 华为技术有限公司 接触器驱动电路
FR3036222B1 (fr) 2015-05-13 2017-04-28 Stmicroelectronics Rousset Procede de commande d'un changement d'etat de fonctionnement d'un organe electromecanique, par exemple un relais, et dispositif correspondant
DE102018128328A1 (de) * 2018-11-13 2020-05-14 Phoenix Contact Gmbh & Co. Kg Steuerschaltung
US10978258B2 (en) * 2019-01-21 2021-04-13 Eaton Intelligent Power Limited Direct current circuit breaker device
CN109510556B (zh) * 2019-01-22 2023-12-19 库顿电子科技(厦门)有限公司 一种三相电机的正反转模块

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4533972A (en) * 1982-01-13 1985-08-06 Omron Tateisi Electronics Co. Electronic switching device having reduced power consumption

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2747607C2 (de) * 1977-10-24 1991-05-08 Sds-Elektro Gmbh, 8024 Deisenhofen Schaltungsanordnung zur Ansteuerung eines bistabilen Relais
JPS5760632A (en) * 1980-09-25 1982-04-12 Matsushita Electric Works Ltd Latching relay driving circuit
US5079667A (en) * 1989-01-26 1992-01-07 Matsushita Electric Works, Ltd. Relay driving circuit for a latch-in relay
JP4561321B2 (ja) * 2004-11-09 2010-10-13 サンケン電気株式会社 ソレノイド駆動装置
CN100517541C (zh) * 2005-01-08 2009-07-22 艾默生网络能源系统有限公司 一种双稳态接触器驱动电路

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4533972A (en) * 1982-01-13 1985-08-06 Omron Tateisi Electronics Co. Electronic switching device having reduced power consumption

Also Published As

Publication number Publication date
US9870889B2 (en) 2018-01-16
DE102012107953B3 (de) 2014-02-13
WO2014033029A1 (fr) 2014-03-06
EP2891168A1 (fr) 2015-07-08
US20150162154A1 (en) 2015-06-11

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