EP2819154B1 - Verfahren zur Herstellung einer verspannten Halbleiterstruktur - Google Patents

Verfahren zur Herstellung einer verspannten Halbleiterstruktur Download PDF

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EP2819154B1
EP2819154B1 EP13173380.0A EP13173380A EP2819154B1 EP 2819154 B1 EP2819154 B1 EP 2819154B1 EP 13173380 A EP13173380 A EP 13173380A EP 2819154 B1 EP2819154 B1 EP 2819154B1
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Prior art keywords
layer
semiconductor structure
strained semiconductor
sacrificial layer
relaxed buffer
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English (en)
French (fr)
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EP2819154A1 (de
Inventor
Seung Hun Lee
Liesbeth Witters
Roger Loo
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Interuniversitair Microelektronica Centrum vzw IMEC
Samsung Electronics Co Ltd
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Interuniversitair Microelektronica Centrum vzw IMEC
Samsung Electronics Co Ltd
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Priority to EP13173380.0A priority Critical patent/EP2819154B1/de
Priority to KR1020130153311A priority patent/KR102142587B1/ko
Priority to JP2014128501A priority patent/JP2015008291A/ja
Priority to US14/313,928 priority patent/US9299563B2/en
Publication of EP2819154A1 publication Critical patent/EP2819154A1/de
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching

Definitions

  • the present invention relates to a method for forming a strained semiconductor structure, the structure being stained in order to improve the performance of the structure.
  • CMOS complementary metal oxide semiconductor
  • FinFET Fin Field Effect Transistor
  • the FinFET technology relies on a multi-gate transistor structure that offers performance improvements compared to existing planar CMOS devices.
  • the gate of the device is generally wrapped over the conducting source-drain channel.
  • US 2009/0142892 A1 relate particularly to a semiconductor device having a thin strained relaxation buffer pattern and to a method of fabricating it. It discloses a method of fabricating a semiconductor device including forming a buffer pattern on a substrate, the buffer pattern including germanium, recrystallizing the buffer pattern to form a strained relaxation buffer pattern, and forming a tensile silicon cap on the strained relaxation buffer pattern, the cap being under tensile strain.
  • EP 1439570 A1 relates to an epitaxial multilayer buffer suitable for the creation of high mobility devices on top of a semiconductor substrate. It further relates to a method to fabricate sich a buffer.
  • a semiconductor device comprising a substrate and having on its top at least a thin strain relaxed buffer, consisting of three layers, characterized in that all three layers of said thin strain relaxed buffer have an essentially constant Ge concentration and said three layers are a first epitaxial layer of Si 1-x Ge x , x being the Ge concentration, a second epitaxial layer of Si 1-x Ge x ; C on said first epitaxial layer, the amount of C being at least 0.3 %, a third epitaxial layer of Si 1-x Ge x on said second layer.
  • An object of the present invention is to alleviate the above mentioned drawbacks and problems.
  • the invention is based on the realization that prior art methods for fabricating stained semiconductor structures involves challenging processes for removal of oxides from a strain relaxed buffer (SRB) layer comprising for instance SiGe or SiC. Removal of oxide from the SRB layer is critical for efficient and high yield fabrication of the strained semiconductor structures. The presence of oxides on the SRB layers may lead to variations in the recess being formed. Further, oxide residues on the SRB layer may lead to surface roughness and defects in the strained semiconductor structures being formed on the SRB layer, which in turn may lead to reduced device performance. Oxide removal from surfaces such as SiGe is, moreover, known to be challenging and commonly involves complicated pre-cleaning and high temperature baking steps. Consequences of the elevated temperatures, typically 700 - 800 °C, during baking is that roughening of the SiGe surface, Ge-migration and/or Ge coalescence may occur, which may in turn reduce device performance.
  • SRB strain relaxed buffer
  • the inventors By using a sacrificial layer on the top of the SRB layer the inventors have realized that oxide formation and atom migration on the SRB layer may be counteracted when forming the strained semiconductor structure. This is a novel concept and counteracts many of the problems mentioned above.
  • the method therefore provides well-controlled trench recess formation and improved regrowth of the strained semiconductor structure. High temperature baking steps may moreover be omitted.
  • Shallow trench isolation should be understood as a standard technique to form electrically isolated regions, often referred to as active regions, in conventional semiconductor devices.
  • STI shallow trenches are etched in the semiconductor material or materials and a thin oxide liner is thermally grown on the trench walls. The trench is then refilled with a thick insulating material. The resulting structure is referred to as a STI structure.
  • sacrificial layer should be understood as a semiconductor layer that is formed on top of the SRB layer in order to counteract oxidation of a surface of the SRB being in contact with the sacrificial layer.
  • the sacrificial layer is later removed and thus sacrificed, such that at least part of the SRB layer is exposed.
  • strained semiconductor structure is in the context of the present application to be construed as a structure that is under compressive or tensile strain.
  • the strained semiconductor structure further refers to any strained semiconductor structure suitable for integration in semiconductor devices such as multi-gate transistors, utilizing strained regions.
  • said sacrificial layer may comprise Ge or Si.
  • the sacrificial layer may consist of Ge or Si.
  • the sacrificial layer may have a thickness of 2 - 50 nm, preferably 20 - 40 nm or 5 - 20 nm.
  • An advantage of using a sacrificial layer having a thickness of 20 - 40 nm is that the strong etch selectivity between the sacrificial layer and the SRB layer allows for an etching which substantially only etches the sacrificial layer. It is hence possible to via the thickness of the sacrificial layer tailor the depth of the STI structure and the thickness of the strained semiconductor structure.
  • a sacrificial layer having a thickness of 20 - 40 nm is referred to as a thick sacrificial layer.
  • a sacrificial layer having a thickness of 5 - 20 nm has the advantage that if defects or dislocations are present at the interface between the sacrificial layer and the SRB layer, these defects may be removed as the etching may involve also removing a portion of the SRB layer i.e. a portion beyond the initial interface.
  • the wording thin should therefore be construed as a thickness small enough such that also a portion of the SRB layer may be etched.
  • a sacrificial layer having a thickness of 5 - 20 nm is referred to as a thin sacrificial layer.
  • a SRB layer surface may be provided which is suitable as a starting surface for regrowth.
  • said etching may further comprise etching a portion of said strain relaxed buffer or SRB layer.
  • said etching may be performed using gas comprising HCI.
  • HCl is known to have large etch selectivity between Ge and Si, i.e. Ge is etched at higher speed than Si allowing for improved recess control when etching the sacrificial layer and/or the SRB layer.
  • said strained semiconductor structure may comprise Ge or Si. This is advantageous as the mobility in strained Ge or Si is improved as compared to their relaxed crystal structures. Moreover the strain in the Ge or Si layer may be tuned by for instance by changing the Ge content in a SiGe SRB layer being adjacent to the strained semiconductor structure.
  • said removing at least a portion of an oxide layer on said sacrificial layer, said etching through said sacrificial layer such that a portion of said strain relaxed buffer layer is exposed, and said forming said strained semiconductor structure on said exposed portion of said strain relaxed buffer layer may be performed in-situ in an epitaxial growth chamber system.
  • a controlled environment may be provided such that oxidation of the sacrificial layer, the SRB layer, and the strained semiconductor structure may be counteracted. As a result a more even recess may be obtained allowing for the formation of an improved strained semiconductor structure.
  • the wording epitaxial growth chamber system should be understood as any system having an enclosed volume that may be connected to an apparatus for epitaxial growth.
  • Epitaxy is the process of layer-by-layer growth of a material of a particular crystal structure and composition on top of another material.
  • Common types of epitaxial techniques include vapour phase, liquid phase, and solid phase growth in accordance with the source of the atoms being used for the growth.
  • vapour phase liquid phase
  • solid phase growth in accordance with the source of the atoms being used for the growth.
  • a vacuum or a gas atmosphere is produced such that a controlled environment is provided where for instance contamination and oxidation may be counteracted.
  • the growth chamber of the apparatus for epitaxial growth is preferably a single- or multi-chamber system which may allow for efficient formation of an improved strained semiconductor structure.
  • said strained semiconductor structure may be formed by epitaxial growth. This is advantageous as epitaxial growth allows for fabrication of semiconductor materials having superior material quality as the material structure and composition may be controlled at the atomic level.
  • said removing may be performed using gas comprising HF and/or HBr.
  • HF and HBr may be used to remove oxide from, for example, Si and Ge surfaces.
  • a termination layer may be formed on top of the surfaces, which counteracts reoxidation.
  • the method may further comprise doping of said sacrificial layer. This provides additional measures to tailor the etch selectivity, which leads to better recess control, as increased doping of Ge or Si results in faster etching of the respective materials.
  • said oxide layer is a native oxide layer.
  • the method further comprises providing said strain relaxed buffer layer on a substrate. This is advantageous as the stability of said strain relaxed buffer layer is improved. Also handling of the strain relaxed buffer layer is facilitated.
  • said strain relaxed buffer layer may comprise a SiGe material.
  • SRB layer thereby provides a suitable base layer upon which Ge or Si can be grown with high material quality.
  • Si has a smaller lattice constant than SiGe resulting in tensile strained Si
  • Ge has a larger lattice constant than SiGe resulting in compressively strained Ge. It is thereby possible to achieve both p-FET and n-FET operation.
  • the SiGe material may have a Ge content in the range 40 - 90%, preferably 50 - 75%.
  • the preferred range of 50 - 75% of Ge is advantageous as it may provide sufficient strain in the strained semiconductor structure and further counteracts dislocation formation in the strained semiconductor structure, i.e. allows for an increased critical thickness of the strained semiconductor structure.
  • the strain relaxed buffer layer may comprise a SiC material. It is advantageous to use SiC as it has a smaller lattice spacing or constant than Si. The use of SiC is therefore resulting in a compressive strain in a strained semiconductor structure of Si, which is also suitable for FET operation. Hence the option to use SiGe or SiC in the strain relaxed buffer layer improves flexibility when designing integrated circuits based on strained semiconductor structures.
  • the SiC material may have a C content in the range 0.01 - 10%, preferably 0.1 - 5%.
  • the preferred range of 0.1 - 5% of C is advantageous as it provides sufficient strain in the strained semiconductor structure and further counteracts dislocation formation in the strained semiconductor structure.
  • Fig.1 illustrates a method 100 for forming a strained semiconductor structure.
  • the method 100 comprises providing a strain relaxed buffer layer 102 an a substrate 202, providing a sacrificial layer on the strain relaxed buffer layer 104, forming a shallow trench isolation structure through the sacrificial layer 106 and partly through the strain relaxed buffer layer 204, whereby the trench is filled with an insulating material, removing at least a portion of an oxide layer on the sacrificial layer 108, wherein said oxide layer is a native oxide layer, etching through the sacrificial layer such that a portion of the strain relaxed buffer layer is exposed 110 and forming the strained semiconductor structure on the exposed portion of the strain relaxed buffer layer 112.
  • the method 100 is based on the realization that by using a sacrificial layer on the top of the strain relaxed buffer layer or SRB layer oxide formation and atom migration on the SRB layer may in relation to prior art be counteracted when forming the strained semiconductor structure.
  • the method therefore provides well-controlled trench recess and improved regrowth of the strained semiconductor structure.
  • Fig. 2 illustrates the formation 200 of a strained semiconductor structure 212 according to a currently preferred embodiment of the present invention.
  • a SRB layer 204 is provided by epitaxial growth on a semiconductor substrate 202.
  • the substrate 202 provides stability of the SRB layer 204 and easy handling.
  • the SRB layer 204 is of SiGe and the substrate 202 is an un-patterned Si substrate, often referred to as a blanket substrate.
  • the Ge content of the SiGe is according to this example increased during the epitaxial growth such that dislocations and stress in the material caused by the lattice mismatch between Ge and Si is counteracted.
  • the thickness of the SiGe film may be, for example, from about 1 micrometer to 10 micrometers.
  • a thinner SRB layer 204 may lead to higher threading dislocation density (TDD) as that the SRB layer 204 cannot effectively release strain in the SiGe, which result in defects and less strain in the strained semiconductor structure.
  • TDD threading dislocation density
  • a thicker SRB layer 204 could lead to problems associated with wafer bending. In general, care should be taken to avoid dislocations while not unduly limiting a thickness of the SiGe.
  • a Ge content of 50 - 75% is accordingly preferably reached at the uppermost part of the SRB layer 204. This is advantageous as strained Ge of a higher quality may be grown on top of SiGe having this material composition. A higher quality of the strained Ge may lead to a strained semiconductor structure 212 having lower surface roughness, lower defect density and/or higher strain.
  • the dislocation density in the Ge may be reduced.
  • a preferably 20 - 40 nm thick sacrificial layer 206 of Ge is fabricated on top of the SRB layer 204. It is preferred that the fabrication comprises epitaxial growth within the same epitaxial growth chamber system used for fabricating the SRB layer 204. This counteracts contamination during fabrication and facilitates efficient epitaxial growth.
  • T is substantially equal to T'.
  • a suitable thickness range for the strained semiconductor 212 structure may be 20 - 40 nm, with a preferred thickness range of 30 - 40 nm.
  • electrically isolated regions 209 may be formed as the trenches are filled with an insulating material, such as silicon dioxide.
  • Oxide (not shown) on the sacrificial layer 206 is then removed from the sacrificial layer 206 using gas comprising HF and/or HBr.
  • gas comprising HF and/or HBr.
  • RIE reactive-ion etching
  • plasma cleaning and/or dry etching may be used for removing the oxide.
  • Etching, using gas comprising HCI, is then performed through the sacrificial layer 206 such that at least a portion 210 of the SRB layer 204 is exposed.
  • An advantage of using a thick (20 - 40 nm) sacrificial layer 206 of Ge is that the high etch selectivity of HCI allows for substantial etching of the sacrificial layer 206 only.
  • Ge is etched about 10 times faster than Si.
  • a well-controlled trench recess may be provided which allows for improved regrowth of the strained semiconductor structure 212, which is finally fabricated on the exposed portion 210 of the SRB layer 204. It is again preferred that the fabrication of the strained semiconductor structure 212 is done by epitaxial growth.
  • the fabrication is performed within the same epitaxial growth chamber system. It is, however, realized that the fabrication may be performed in a plurality of separated systems, between which the substrate 202 may be transferred in ambient conditions or using transfer systems utilizing a controlled environment such as vacuum or gas environment.
  • the strain level in the strained Ge structure may be altered by adjusting the Ge content in the SiGe material.
  • the strain increases the mobility of the carriers in the Ge material leading to improved device performance.
  • the removing 108 at least a portion of an oxide layer on the sacrificial layer 206, the etching 110 through the sacrificial layer 206 such that a portion 210 of the SRB layer 204 is exposed, and/or said forming 112 the strained semiconductor structure 212 on the exposed portion 210 of the SRB layer 204 are preferably performed in an epitaxial growth chamber system.
  • an epitaxial growth chamber system By performing the above in a controlled environment inside the epitaxial growth chamber system, oxidation of the sacrificial layer 206, the SRB layer 204, and the strained semiconductor structure 212 may be counteracted. As a result an improved recess in terms of smoothness may be obtained.
  • the SRB layer 204 may instead be made of SiC and the thick (20 - 40 nm) sacrificial layer may be of Si or Ge.
  • the strained semiconductor structure 212 may according to this embodiment be made of Si. SiC has a smaller lattice spacing or constant than Si and as a result, the strained semiconductor structure 212 is under compressive strain. Such structures are as discussed above suitable for FET operation.
  • the SiC material has a C content in the range 0.01 - 10%, preferably 0.1 - 5%.
  • the preferred range of 0.1 - 5% of C is advantageous as it provides sufficient strain in the strained semiconductor structure 212 and further counteracts dislocation formation in the strained semiconductor structure 212.
  • Fig. 3 illustrates the formation 300 of a strained semiconductor structure 312 according to another currently preferred embodiment of the present invention.
  • a SRB layer 204 is provided by epitaxial growth on a semiconductor substrate 202.
  • the substrate 202 provides stability of the SRB layer 204 and facilitates easy handling.
  • the SRB layer 204 is of SiGe and the substrate 202 is of blanket Si.
  • the Ge content of the SiGe is according to this example increased during the epitaxial growth such that dislocations and stress in the material caused by the lattice mismatch between Ge and Si is counteracted.
  • a Ge content of 50 - 75% is preferably reached at the uppermost part of the SRB layer 204.
  • High quality Ge may be grown on top of SiGe having this material composition, i.e. the dislocation density in the Ge may be reduced.
  • a preferably 5 - 20 nm thin sacrificial layer 306 of Ge is fabricated, preferably by epitaxial growth, on top of the SRB layer 204.
  • a Ge sacrificial layer 306 as oxide removal from Ge surfaces is more effective as compared to SiGe surfaces.
  • a thin (5 - 20 nm) sacrificial layer 306 having a thickness t has the advantage that if, for instance, defects or dislocations are present at the interface 310 between sacrificial layer 306 and the SRB layer 204, these will be removed during the etching. This is achieved as the etching also involves removing a portion of the SRB layer 204 i.e. etching beyond the initial interface 310.
  • the regrown strained semiconductor structure 312 of Ge has a thickness, t', which according to this embodiment is larger than the thickness t of the sacrificial layer 306. It is, however, to be understood that any suitable thicknesses may be used below the critical thickness of the material used for forming the strained semiconductor structure 312.
  • t' thickness of the sacrificial layer 306.
  • a thin (5 - 20 nm) sacrificial layer 306 of Si may be used.
  • An advantage of using Si is that oxide removal from the Si surface is improved as compared to removing oxide from a SiGe surface. Moreover the etching rates are different for Si and SiGe which allows for improved processing of the strained semiconductor structures 312.
  • An additional advantage is that there is only limited Si migration on the Si surface, even at elevated temperatures such as during a high-temperature baking, which improves the surface smoothness of the sacrificial layer 306 leading to improved formation of the strained semiconductor structure 312.
  • the SRB layer 204 may be made of SiC and the thin (5 - 20 nm) sacrificial layer 306 of Si or Ge.
  • the strained semiconductor structure 312 is according to this embodiment of Si.
  • the SiC material has a C content in the range 0.01 - 10%, preferably 0.1 - 5%.
  • the method 100 may further comprise doping of the sacrificial layer.
  • This provides additional measures to tailor the etch selectivity, leading to improved recess control, as increased doping of Ge or Si results in altered etch rates for the respective materials.
  • strain inducing elements may include phosphorus, boron, nitrogen or tin.
  • the doping may be performed during the growth process in an epitaxial growth chamber system using a dopant source or by ion implantation.
  • a SiC layer may also for example be provided on the substrate 202 like Si according to the disclosure above for a SiGe SRB layer.
  • the substrate 202 is preferable un-patterned Si which simplifies device fabrication, but could also be patterned as is realized by a person skilled in the art.
  • the strained semiconductor structure 212, 312 may comprise SiGe or Ge where the strain is induced by increasing the Ge content.
  • the Ge content of the strained semiconductor structure 212, 312 may be higher than the Ge content of SiGe buffer layer 204, and preferably substantially pure Ge.
  • the Ge content of the strained semiconductor structure 212, 312 may be constant throughout its whole volume.
  • the Ge content of the strained semiconductor structure 212, 312 may be increased from a lower value at the base, adjacent to the SRB layer 204, to the top of the structure 212, 312.
  • the strained semiconductor structure 212, 312 comprises SiC where the strain is induced by increasing the C content.
  • the C content of the strained semiconductor structure 212, 312 may be higher than the C content of SiC buffer and preferably between 0.1 - 2% C.

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Claims (14)

  1. Verfahren (100) zum Bilden einer verspannten Halbleiterstruktur (212, 312), umfassend
    Bereitstellen (102) einer spannungsrelaxierten Pufferschicht (204) auf einem Substrat (202),
    Bilden (104) einer Opferschicht (206, 306) auf der spannungsrelaxierten Pufferschicht (204),
    Bilden (106) einer flachen Grabenisolationsstruktur (208) durch die Opferschicht (206, 306) und teilweise durch die spannungsrelaxierte Pufferschicht (204), wobei der Graben mit einem isolierenden Material gefüllt wird,
    Entfernen (108) mindestens eines Abschnitts einer Oxidschicht auf der Opferschicht (206, 306), wobei es sich bei der Oxidschicht um eine native Oxidschicht handelt,
    Ätzen (110) durch die Opferschicht (206, 306) derart, dass ein Abschnitt (210) der spannungsrelaxierten Pufferschicht (204) freigelegt wird,
    Bilden (112) der verspannten Halbleiterstruktur (212, 312) auf dem freigelegten Abschnitt (210) der spannungsrelaxierten Pufferschicht (204).
  2. Verfahren (100) nach Anspruch 1, wobei die Opferschicht (206, 306) Ge oder Si umfasst.
  3. Verfahren (100) nach Anspruch 1 oder 2, wobei die Opferschicht (206, 306) eine Dicke von 2 bis 50 nm, vorzugsweise 20 bis 40 nm oder 5 bis 20 nm aufweist.
  4. Verfahren (100) nach einem der Ansprüche 1 bis 3, wobei das Ätzen (110) weiter das Ätzen (110) eines Abschnitts der spannungsrelaxierten Pufferschicht (204) umfasst.
  5. Verfahren (100) nach einem der Ansprüche 1 bis 4, wobei das Ätzen (110) unter Verwendung von Gas durchgeführt wird, das HCl umfasst.
  6. Verfahren (100) nach einem der Ansprüche 1 bis 5, wobei die verspannte Halbleiterstruktur (212, 312) Ge oder Si umfasst.
  7. Verfahren (100) nach einem der Ansprüche 1 bis 6, wobei
    das Entfernen (108) mindestens eines Abschnitts einer Oxidschicht auf der Opferschicht (206, 306),
    das Ätzen (110) durch die Opferschicht (206, 306) derart, dass ein Abschnitt der spannungsrelaxierten Pufferschicht (204) freigelegt wird, und
    das Bilden (112) der verspannten Halbleiterstruktur (212, 312) auf dem freigelegten Abschnitt (210) der spannungsrelaxierten Pufferschicht (204)
    in-situ in einem Epitaxialwachstumskammersystem durchgeführt werden.
  8. Verfahren (100) nach einem der Ansprüche 1 bis 7, wobei das Entfernen (108) unter Verwendung von Gas durchgeführt wird, das HF und/oder HBr umfasst.
  9. Verfahren (100) nach einem der Ansprüche 1 bis 8, das weiter das Dotieren der Opferschicht (206, 306) umfasst.
  10. Verfahren (100) nach einem der Ansprüche 1 bis 9, das weiter das Bereitstellen der spannungsrelaxierten Pufferschicht (204) auf einem Substrat (202) umfasst.
  11. Verfahren (100) nach einem der Ansprüche 1 bis 10, wobei die spannungsrelaxierte Pufferschicht (204) ein SiGe-Material umfasst.
  12. Verfahren (100) nach Anspruch 11, wobei das SiGe-Material einen Ge-Gehalt im Bereich von 40 bis 90 %, vorzugsweise 50 bis 75 % aufweist.
  13. Verfahren (100) nach einem der Ansprüche 1 bis 10, wobei die spannungsrelaxierte Pufferschicht (204) ein SiC-Material umfasst.
  14. Verfahren (100) nach Anspruch 13, wobei das SiC-Material einen C-Gehalt im Bereich von 0,01 bis 10 %, vorzugsweise 0,1 bis 5 % aufweist.
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KR1020130153311A KR102142587B1 (ko) 2013-06-24 2013-12-10 응력 변형된 반도체 구조물 형성 방법
JP2014128501A JP2015008291A (ja) 2013-06-24 2014-06-23 歪み半導体構造を形成する方法
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CN104851781B (zh) * 2015-06-08 2020-04-14 国网智能电网研究院 一种n型低偏角碳化硅外延片的制备方法
US9685553B2 (en) * 2015-06-22 2017-06-20 Globalfoundries Inc. Generating tensile strain in bulk finFET channel
US9818825B2 (en) * 2015-10-27 2017-11-14 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
US9576857B1 (en) * 2016-03-02 2017-02-21 Globalfoundries Inc. Method and structure for SRB elastic relaxation
EP3486950B1 (de) * 2017-11-15 2020-05-27 IMEC vzw Verfahren zur herstellung eines gate-all-around feldeffekttransistors
US11444199B2 (en) * 2020-08-03 2022-09-13 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor device and a semiconductor device

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KR100782497B1 (ko) * 2006-11-20 2007-12-05 삼성전자주식회사 얇은 응력이완 버퍼패턴을 갖는 반도체소자의 제조방법 및관련된 소자
JP2010021235A (ja) * 2008-07-09 2010-01-28 Toshiba Corp 半導体装置及びその製造方法
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EP2819154A1 (de) 2014-12-31
US9299563B2 (en) 2016-03-29

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