EP2810307A1 - Empilement en métal à haute résistance et à faible température pour fixation de puce - Google Patents

Empilement en métal à haute résistance et à faible température pour fixation de puce

Info

Publication number
EP2810307A1
EP2810307A1 EP13743107.8A EP13743107A EP2810307A1 EP 2810307 A1 EP2810307 A1 EP 2810307A1 EP 13743107 A EP13743107 A EP 13743107A EP 2810307 A1 EP2810307 A1 EP 2810307A1
Authority
EP
European Patent Office
Prior art keywords
bonding layer
light emitting
emitting diode
percent
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP13743107.8A
Other languages
German (de)
English (en)
Inventor
Michael John Bergmann
Christopher D. Williams
Kevin Shawne Schneider
Kevin Haberern
Matthew Donofrio
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wolfspeed Inc
Original Assignee
Cree Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/361,569 external-priority patent/US9443903B2/en
Application filed by Cree Inc filed Critical Cree Inc
Publication of EP2810307A1 publication Critical patent/EP2810307A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

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    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
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Definitions

  • the present application relates to semiconductor device fabrication, and in particular to metal stacks for die attachment of semiconductor devices.
  • Solid state lighting systems including one- or two-dimensional arrays of solid state lighting devices are used for a number of lighting applications.
  • solid state lighting panels including arrays of solid state light emitting devices have been used as direct illumination sources, for example, in architectural and/or accent lighting.
  • Solid state lighting arrays are also commonly used as backlights for small liquid crystal display (LCD) screens, such as LCD display screens used in portable electronic devices.
  • LCD liquid crystal display
  • a solid state light emitting device may include, for example, a packaged light emitting device including one or more light emitting diodes (LEDs).
  • LEDs typically include semiconductor layers forming p-n junctions.
  • Organic LEDs which include organic light emission layers, are another type of solid state light emitting device.
  • a solid state light emitting device generates light through the recombination of electronic carriers, i.e. electrons and holes, in a light emitting layer or region.
  • an LCD backlight it is common to arrange LED devices in a linear array on a metal bar, called a "light bar”, which is arranged within an LCD backlight unit to emit light parallel to the LCD screen. The light is directed toward the LCD screen by a light guide in the LCD backlight unit.
  • LED devices that are attached to packages, heatsinks and/or submounts with silicone die attach.
  • silicone is not ideal. It is a poor thermal conductor, which may limit the reliability and/or performance of LED die and packages at the higher drive currents needed for higher light output.
  • Die attach metals may have better thermal conductivity than silicone. However, conventional die attach metals may be unsuited for attachment to plastic packages, such as those used in backlighting applications.
  • a typical die attach metal is a eutectic Au/Sn alloy, with 80% Au and 20% Sn (by weight).
  • the Au/Sn 80/20 alloy has good mechanical strength, reliability, and thermal conductivity, and is recognized as a standard die attach alloy.
  • a challenge with the AuSn 80/20 alloy die attach is the requirement of a hot reflow to form the bond, typically in the range of about 305 °C.
  • Many plastic packages or chip-on-board packages are adversely affected by exposure to elevated temperatures.
  • the packages may fail catastrophically at temperatures in excess of 300 °C, or may suffer material degradation, for example, browning and/or yellowing of the package, which reduces the reflectivity and hence the brightness of the package.
  • the overall voltage across the bar may also decrease, resulting in a need to drop the line (supply) voltage further to the operating voltage of the low- voltage bar that includes fewer, larger LED dice. This may require a more complicated power supply that has more dissipation loss, resulting in lower overall system efficiency.
  • a packaged light emitting diode includes a package surface, a semiconductor light emitting diode mounted on the package surface, and a metal stack on the light emitting diode.
  • the metal stack includes a bonding layer on the light emitting diode that contacts the package surface and provides mechanical attachment of the light emitting diode to the package surface.
  • the bonding layer includes gold, tin and nickel.
  • a weight percentage of tin in the bonding layer is greater than 20 percent and a weight percentage of gold in the bonding layer is less than about 75 percent.
  • the weight percentage of tin in the bonding layer may be greater than about 40 percent in some embodiments, and the weight percentage of gold in the bonding layer may be less than 10 percent.
  • a weight percentage of nickel in the bonding layer may be greater than 10 percent in some embodiments.
  • the thickness of the bonding layer may be greater than about 2 microns, in some embodiments greater than 2.5 microns, and in some embodiments may be at least about 3 microns.
  • the entire metal stack may be less than an 6 microns thick.
  • the weight percentage of tin in the bonding layer may be less than 80 percent. In some embodiments, the weight percentage of tin in the bonding layer may be between about 75 percent and 80 percent.
  • the weight percentage of gold the bonding layer may be less than about 5 percent, and in some embodiments, the weight percentage of gold the bonding layer may be less than about 2 percent.
  • the entire metal stack may contain an amount of less than 5 percent by weight.
  • the bonding layer may include a metal alloy that is more than 90 percent nickel and tin by weight. In some embodiments, the metal alloy of the bonding layer may be more than 95 percent nickel and tin by weight, and in some embodiments more than 97 percent nickel and tin by weight.
  • the bonding layer may include a metal alloy that is thermally stable at temperatures up to 260 degrees centigrade. In some embodiments, the metal alloy of the bonding layer may be thermally stable at temperatures up to 290 degrees centigrade. In further embodiments, the metal alloy of the bonding layer may be thermally stable at temperatures up to 310 degrees centigrade, and in still further, the metal alloy of the bonding layer may be thermally stable at temperatures up to 320 degrees centigrade.
  • the barrier layer may be formed of a material and having a thickness sufficient to reduce the formation or migration of free metals or alloys that have melting points lower than 300 degrees centigrade.
  • a light emitting diode structure includes a diode region and a metal stack on the diode region.
  • the metal stack includes a barrier layer on the diode region and a bonding layer on the barrier layer.
  • the barrier layer is between the bonding layer and the diode region.
  • the bonding layer includes gold, tin and nickel.
  • a weight percentage of tin in the bonding layer is at least about 70 percent, a weight percentage of gold in the bonding layer is less than about 10 percent, and a weight percentage of nickel in the bonding layer is at least about 19 percent.
  • Figure 1 is a plan view of a light emitting diode structure according to some embodiments.
  • Figure 2 is a cross-sectional view of a light emitting diode structure according to some embodiments taken along line A- A' of Figure 1.
  • Figure 3 is a cross-sectional view of a light emitting diode structure according to further embodiments.
  • Figure 4 is a bottom plan view of a light emitting diode structure according to further embodiments.
  • Figure 5 is a cross-sectional view of a metal bond pad stack according to some embodiments.
  • Figure 6 is a graph of a phase diagram for the Au-Sn material system.
  • Figure 7 is a cross-sectional view of a packaged device including a multiple active region light emitting diode according to some embodiments.
  • Figure 8 is a cross-sectional view of a packaged device including multiple single active region light emitting diodes according to some embodiments.
  • Figure 9 is a schematic diagram of a packaged device according to some embodiments.
  • Figures 10 and 11 are plan views of a light bars including a plurality of light emitting diodes according to some embodiments.
  • Figure 12 is a schematic diagram illustrating a backlight assembly for a liquid crystal display screen.
  • Figure 13 is a side cross-sectional view of a liquid crystal diode display according to some embodiments.
  • Figures 14A, 14B and 14C are cross-sectional views of light emitting diode structures according to further embodiments.
  • Figure 15 is a cross-sectional view of an LED die according to some embodiments mounted in a package.
  • Figure 16 is a cross-sectional view of a metal die attach pad according to some embodiments on a generic semiconductor LED die.
  • Figures 17A and 17B illustrate direct die attachment of an LED die including a metal stack according to some embodiments.
  • Figures 18A and 18B are graphs of differential scanning calorimetry (DSC) results for several different metal stacks including a metal stack according to the present invention.
  • Figures 19 A, 19B, 20 and 21 are cross-sectional views semiconductor LED die mounted in various packages using metal die attach stacks in accordance with some embodiments.
  • Embodiments of the present invention are directed towards methods and devices that may improve the thermal characteristics of a solid state lighting apparatus, such as a light bar, and in some cases may reduce the operating temperature of a solid state lighting apparatus.
  • Some embodiments provide a light emitting device die design including a plurality of isolated active junctions configured to be connected in series on the die. Providing a die with multiple junctions that are connected in series may allow the chip to produce a high light output while driving the chip at a relatively low current, thereby reducing the operating temperature of the device.
  • some embodiments provide a metal die attach for a light emitting device die that decreases the thermal resistance of a package incorporating the die, thereby potentially reducing the operating temperature of the device, while permitting the device to be manufactured using a lower temperature reflow that may not adversely affect plastic material in the device package.
  • Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention.
  • the thickness of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected.
  • embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing.
  • a typical die attach metal is a eutectic Au/Sn alloy, with 80% Au and 20% Sn (by weight).
  • the Au/Sn 80/20 alloy has good mechanical strength, reliability, and thermal conductivity, and is recognized as a standard die attach alloy.
  • an AuSn 80/20 alloy die attach may require a reflow in the range of about 305 °C, which can adversely affect plastic packages or chip-on-board packages.
  • Some embodiments provide a metal die attach including an Sn rich structure that reflows at temperatures less than 250 °C.
  • some embodiments provide an AuSn metal die attach that includes about 40% or more (by weight) of Sn.
  • the weight percent of Sn in the die attach structure may be greater than 60%, and in some embodiments the weight percent of Sn in the die attach structure may be greater than 70%. In some further embodiments, the weight percent of Sn in the die attach structure may be greater than 75%, and in still further embodiments the weight percent of Sn in the die attach structure may be greater than 90%.
  • the tin may melt at a lower temperature than an AuSn alloy having a comparable weight percentage of tin.
  • the weight percent of tin in the die attach structure may be greater than 20%.
  • a die attach structure may reflow and bond at temperatures less than 250 °C.
  • the lower reflow temperature of a metal die attach structure as described herein may allow the use of lower reflow temperatures, which may mitigate or reduce the negative effect of high temperature solder reflow on a plastic package body, while providing a metallic submount bond that has enhanced thermal properties, such as reduced thermal resistance, relative to a conventional die attach material, such as silicone.
  • a metal die attach structure as disclosed herein can remain stable during a RoHS (Restriction of Harmful Substances) - compliant package reflow, which allows temperatures up to 260 °C. That is, a metal stack according to some embodiments may have a reflow temperature less than about 250 °C, but once bonded may remain stable at temperatures above 260 °C.
  • RoHS Restriction of Harmful Substances
  • Figure 1 is a plan view of a light emitting diode die (or chip) 10 according to some embodiments, while Figure 2 is a cross sectional view of a light emitting diode structure according to some embodiments taken along line A-A' of Figure 1.
  • a light emitting diode die 10 is a unitary semiconductor device that includes a support layer 12 having a first face 12A and a second face 12B opposite the first face 12 A.
  • a diode region including a plurality of isolated active regions 14A-14D is on the first face 12A of the support layer 12.
  • the active regions 14A-14D may be isolated from one another by means of mesa isolation (as illustrated in Figures 1-2) or other techniques, such as implant isolation, trench isolation, etc.
  • Each of the active regions 14A-14D may include a single p-n junction.
  • the light emitting diode die 10 may be referred to as a multi -junction die.
  • This structure is not to be confused with a multiple quantum well diode structure, which is well known in the art.
  • a multiple quantum well structure has an active region that may include multiple stacked quantum wells in which recombination occurs to generate light.
  • a conventional multiple quantum well structure may still have only a single p-n junction.
  • a light emitting diode die 10 may have multiple isolated active regions, and hence may have multiple isolated p-n junctions.
  • Each of the isolated active regions includes an anode contact 15 and a cathode contact 17.
  • a die attach pad 30 is on the second face of the support layer.
  • the bond pad includes a gold-tin structure having a weight percentage of tin of 50% or more.
  • the light emitting diode die 10 may further include a first wirebond pad 18 on an anode contact 15 of a first one 14A of the isolated active regions and a second wirebond pad 20 on a cathode contact 17 of a second one 14D of the isolated active regions.
  • the isolated active regions 14A-14D may be connected in series by means of metal interconnects 28A, 28B and 28C which contact respective current spreading fingers 25A, 25B, 25C on the anode contacts 15.
  • metal interconnect 28 A may electrically connect the cathode contact 17 of the first one 14A of the isolated active regions and the anode contact 15 of the second one 14B of the isolated active regions.
  • Metal interconnect 28B may electrically connect the cathode contact 17 of the second one 14B of the isolated active regions and the anode contact 15 of the third one 14C of the isolated active regions.
  • metal interconnect 28C may electrically connect the cathode contact 17 of the third one 14C of the isolated active regions and the anode contact 15 of the fourth one 14D of the isolated active regions.
  • the isolated active regions 14A-14D may thereby be connected in electrical series by the electrical interconnects 28A-28C.
  • the isolated active regions 14A-14D may be connected in series to form an electronic device having a single anode contact (wire bond pad 18) and a single cathode contact (wire bond pad 20).
  • the LED die 10 can have many different semiconductor layers arranged in different ways. LED structures and their fabrication and operation are generally known in the art and only briefly discussed herein.
  • the layers of the LED die can be fabricated using known processes with a suitable process being fabrication using metal organic chemical vapor deposition (MOCVD).
  • MOCVD metal organic chemical vapor deposition
  • the layers of the LED die generally include an active layer/region sandwiched between first and second oppositely doped epitaxial layers all of which are formed successively on a growth substrate. LEDs can be formed on a wafer and then singulated for mounting in a package. It is understood that the growth substrate can remain as part of the final singulated LED or the growth substrate can be fully or partially removed, and the epitaxial layers that constitute the diode region can be mounted on a carrier substrate.
  • the active region can include single quantum well (SQW), multiple quantum well (MQW), double heterostructure or super lattice structures.
  • SQW single quantum well
  • MQW multiple quantum well
  • the active region and doped layers may be fabricated from different material systems, with preferred material systems being Group-Ill nitride based material systems.
  • Group-Ill nitrides refer to those semiconductor compounds formed between nitrogen and the elements in the Group III of the periodic table, usually aluminum (Al), gallium (Ga), and indium (In).
  • AlGaN aluminum gallium nitride
  • AlInGaN aluminum indium gallium nitride
  • the doped layers are gallium nitride (GaN) and the active region is InGaN.
  • the doped layers may be AlGaN, aluminum gallium arsenide (AlGaAs) or aluminum gallium indium arsenide phosphide
  • the growth substrate can be made of many materials such at sapphire, silicon carbide, aluminum nitride (A1N), GaN, with a suitable substrate being a 4H polytype of silicon carbide, although other silicon carbide polytypes can also be used including 3C, 6H and 15R polytypes.
  • Silicon carbide has certain advantages, such as a closer crystal lattice match to Group III nitrides than sapphire and results in Group III nitride films of higher quality. Silicon carbide also has a very high thermal conductivity so that the total output power of Group-Ill nitride devices on silicon carbide are typically not limited by the thermal dissipation of the substrate (as may be the case with some devices formed on sapphire).
  • the LED die can be coated with one or more phosphors with the phosphors absorbing at least some of the LED light and emitting a different wavelength of light such that the device emits a combination of light from the LED and the phosphor.
  • the LED emits a white light
  • LED die can be coated and fabricated using many different methods, with one suitable method being described in U.S. patent application Ser. Nos. 11/656,759 and 11/899,790, both entitled “Wafer Level Phosphor Coating Method and Devices Fabricated Utilizing Method", and both of which are incorporated herein by reference.
  • the LEDs can be coated using other methods such an electrophoretic deposition (EPD), with a suitable EPD method described in U.S. patent application Ser. No. 11/473,089 entitled “Closed Loop Electrophoretic Deposition of Semiconductor Devices", which is also incorporated herein by reference. It is understood that LED packages according to the present invention can also have multiple LEDs of different colors, one or more of which may be white emitting.
  • the support layer 12 may be insulating or semi-insulating, and in some embodiments, the support layer may include semi-insulating silicon carbide, which is available from the assignee Cree, Inc.
  • the support layer 12 may be a growth substrate on which the epitaxial semiconductor layers that form the isolated active regions 14A-14D are grown.
  • the support layer may include a carrier layer on which the isolated active regions 14A-14D are supported.
  • the support layer may include a layer of a semi-insulating gallium nitride based semiconductor material on which the epitaxial semiconductor layers that form the isolated active regions 14A-14D are grown.
  • Semi-insulating SiC may include silicon carbide doped with deep level transition elements, such as vanadium, as described in U.S. Patent No. 5,856,231, the disclosure of which is incorporated herein by reference as if set forth herein, and/or may include high purity semi-insulating silicon carbide.
  • a high-purity semi- insulating (HPSI) silicon carbide boule may be formed using a seeded sublimation growth technique. Exemplary sublimation growth techniques are more fully described in U.S. Patent Publication No. 2001/0017374 and in U.S. Pat. Nos. 6,403,982, 6,218,680, 6,396,080, 4,866,005 and Re. 34,861, the disclosures of which are hereby incorporated herein by reference. Sublimation techniques may also include gas fed sublimation, continuous growth and high-temperature CVD.
  • the semiconductor light emitting device may be gallium nitride-based LEDs such as those devices manufactured and sold by Cree, Inc. of Durham, North Carolina.
  • the present invention may be suitable for use with LEDs and/or lasers as described in United States Patent Nos. 6,201,262; 6,187,606; 6,120,600; 5,912,477; 5,739,554; 5,631,190; 5,604,135; 5,523,589; 5,416,342; 5,393,993; 5,338,944;
  • the LEDs and/or lasers may be configured to operate such that light emission occurs through the substrate.
  • the substrate may be patterned so as to enhance light output of the devices as is described, for example, in the above-cited U.S. Patent Publication No. US
  • the light emitting devices may include a substrate that has been thinned, for example, by etching, mechanical lapping or grinding and polishing, to reduce the overall thickness of the structure.
  • Techniques for thinning a substrate are described in U.S. Patent Publication No. 2005/0151138 entitled “Methods Of Processing Semiconductor Wafer Backsides Having Light Emitting Devices (LEDS) Thereon And LEDs So Formed," the disclosure of which is hereby incorporated by reference as if set forth fully herein.
  • a substrate may be shaped or roughened using sawing, laser scribing or other techniques to introduce geometrical features such as angled sidewalls which may increase light extraction.
  • the substrate may be further etched to improve light extraction using for example the etch process described in US. Patent Publication No. 2005/0215000 entitled "Etching Of
  • the substrate may be remove entirely by substrate removal techniques such as the techniques taught in U.S. Patent Nos. 6,559,075, 6,071,795, 6,800,500 and/or 6,420,199 and/or U.S. Patent Publication No.
  • the isolated active regions 14A-14D are arranged in a row extending from a first end 12C of the support layer 12 to a second end 12D of the support layer 12 opposite the first endl2C.
  • the anode contact 15 of each of the isolated active regions 14A-14D may be provided on a side of the isolated active region nearest the first end 12C of the support layer 12, while the cathode contact 17 of each of the isolated active regions 14A-14D may be provided on a side of the isolated active region nearest the second end 12D of the support layer 12.
  • the light emitting diode die 10 may further include an insulating layer 29 on the support layer 12 and between respective ones of the active regions 14A- 14D.
  • the electrical interconnects 28A-28C may be at least partially provided on portions of the insulating layer 29. Moreover, other portions of the insulating layer 29 may be provided on the active regions 14A-14D and on the interconnects 28A-28C.
  • the insulating layer 29 may include, for example, an insulating material, such as silicon oxide, silicon nitride, polyimide, or any other suitable insulator.
  • the insulating layer 29 may include a single layer of insulating material and/or may be formed in multiple layers of the same or different material.
  • the insulating layer 29 may include an encapsulant material, such as silicone, epoxy resin, or the like. Furthermore, the insulating layer 29 may include phosphor materials, such as those described in U.S. Patent No. 6,853,010, entitled Phosphor-Coated Light Emitting Diodes Including Tapered Sidewalls and Fabrication Methods Therefor, and/or U.S. Patent No.
  • the wirebond pads 18, 20 may extend outside the insulating layer 29 to facilitate electrical contact to the die 10.
  • the light emitting device chip may include only one active region.
  • Figure 3 is a cross view of a light emitting device die 10' according to further embodiments, and Figure 4 is a bottom plan view of the light emitting device die 10'.
  • the isolated active regions 14A-14C, the wirebond pads 18, 20, the metal interconnects 28A-28C, the anodes 15, the cathodes 17 and the insulating layer 29 may all be similar to those described above with respect to Figures 1-2.
  • the die 10' includes a support layer 42 that has sidewalls 42C that are angled at an oblique angle to the upper and lower surfaces 42A, 42B of the support layer.
  • the sidewalls 42C may be angled inwardly from the upper surface 42A on which the isolated active regions are provided to the lower surface 42B of the support layer 42.
  • the metal die attach pad 30 may be formed on the lower surface 42B and not on the angled sidewalls 42C of the support layer 42 to enhance light extraction when the chip 10' is mounted, for example, to a submount.
  • FIG. 5 is a cross sectional view of a metal die attach pad 30 according to some embodiments.
  • the die attach pad 30 may include a metal stack including a layer of titanium 38 in direct contact with the support layer 12, 42, a layer of platinum 36 on the titanium layer 38, and a layer of nickel 32 on the platinum layer 36.
  • the titanium layer 38 may have a thickness of about 0.5 nm to about 25 nm, and in particular may have a thickness of about 10 nm.
  • the purpose of the titanium layer 38 is to promote adhesion.
  • the platinum layer 36 may have a thickness of about 100 nm to about 500 nm, and in particular may have a thickness of about 250 nm. The purpose of the platinum layer 36 is to reduce tin migration to the titanium layer 38 during the bonding process, and to form a platinum-tin phase with excess molten tin to enhance stability under operation and thermal exposure.
  • the nickel layer 32 may have a thickness of about 100 nm to about 500 nm, and in particular may have a thickness of about 200 nm. The purpose of the nickel layer 32 is to form a nickel-tin phase with excess molten tin during the bonding process, and to enhance stability under operation and thermal exposure.
  • the die attach pad 30 further includes a die attach (bonding) layer 34 that includes a first layer of gold 34A, a layer of tin 34B and a second layer of gold 34D.
  • the die attach pad 30 may also include a layer of nickel 34C between the layer of tin 34B and the second layer of gold 34D.
  • the purpose of the nickel layer 34C is to reduce diffusion of gold from the second gold layer 34D into the tin layer 34C during the deposition process.
  • the nickel layer 34C may have a thickness between about 50 nm and about 400 nm, and in particular may have a thickness of about 200 nm.
  • a thickness of the layer of tin 34B may be about three times a combined thickness of the first layer of gold 34A and the second layer of gold 34D.
  • the weight percentage of tin in the die attach layer 34 and/or in the die attach pad 30, may be about 40% or more.
  • the weight percentage of tin in the bond pad may be at least about 50%, and in still further embodiments, the weight percentage of tin in the bond pad may be at least about 60%.
  • the weight percentage of tin in the bond pad may be at least about 70%), in still further embodiments, the weight percentage of tin in the bond pad may be at least about 75%, and in yet further embodiments, the weight percentage of tin in the bond pad may be at least about 90%.
  • metal layers including for example one or more reflective layers of silver and/or aluminum, may be provided in the metal stack between the die attach layer 34 and the support layer 12, 42.
  • Figure 6 is a graph of a phase diagram for the Au-Sn material system.
  • temperature is shown on the ordinate (y-axis) while weight percent of tin is shown on the abscissa (x-axis).
  • y-axis ordinate
  • x-axis weight percent of tin
  • an alloy created during the melting and solidifying of the Au and Sn in the metal die attach pad 30 will not pass through the eutectic point E that exists in the AuSn system at about 20% Sn by weight (corresponding to about 29% tin by atomic percentage), as illustrated in Figure 6.
  • the Au and Sn in the die attach pad 30 will melt at a relatively low temperature as the temperature of the die attach pad 30 is raised, and the high-Sn content melt will then solidify to an alloy that has a melting temperature that is greater than the melting temperature of the 80/20 eutectic alloy, and in particular a melting temperature that is greater than 260 °C.
  • the metal stack includes a layer of pure tin which has a melting point of about 230 °C, a bonding process below 250 °C will be sufficient to melt the tin layer.
  • the molten tin in contact with the gold, nickel, and platinum layers in the stack will solidify as various gold-tin and platinum-tin phases. These phases have higher melting points than pure tin according to their respcective phase diagrams, and will therefore be thermally stable up to 260C under operation and thermal exposure.
  • Figure 7 is a cross sectional view of a package 50 including a multiple active region light emitting diode 10, 10' according to some embodiments.
  • the package 50 includes a submount 55, which may include a thermally conductive material, such as aluminum nitride, copper, aluminum or the like.
  • a reflector 56 is on the submount 55 and surrounds a die mounting region on an upper surface of the submount 55.
  • the reflector 55 may be formed of a material that has specular reflective properties, such as aluminum, or it may be formed of a diffuse reflector, such as white plastic.
  • a multiple active region light emitting diode 10, 10' as described above is mounted on a bond pad or metal bonding region (not shown) in the die mounting region using the metal die attach pad 30 for die attach, and the device 10' is electrically connected to the package through wirebonds to the first and second bond pads 51 A, 5 IB, which are electrically connected to anode and cathode pads 52, 54, respectively, of the package 50, for example, through conductive vias in the submount 55 (not shown).
  • a separate metal pad 53 may be provided to enhance thermal conduction from the package 50 to an external heat sink (not shown).
  • a package 50 includes a unitary light emitting diode chip that includes a plurality (e.g. four) separate active regions on a common substrate. The plurality of active regions are connected in series, so that the package 50 may have a single anode contact 52 and a single cathode contact 54.
  • a package 50 as illustrated in Figure 7 may have particular advantages when used in a backlight for a liquid crystal display (LCD), because the package may emit an increased amount of light for a given level of current, and the package may have a higher forward voltage drop than a conventional package that includes only one LED chip or two LED chips connected in series.
  • LCD liquid crystal display
  • a package 50 may have a forward voltage that is greater than about 6 volts.
  • the package may have a forward voltage of about 9V or more, and in some embodiments the package may have a forward voltage of about 12 volts or more.
  • a plurality of packages 50 may be provided in series in a structure, such as an LCD backlight unit.
  • the packages 50 may each have a high level of light emission and also a high forward voltage, so that the overall forward voltage of the series may be better matched to the output voltage of a DC power supply that provides current to the LED structure.
  • Figure 8 is a cross sectional view of a packaged device 50' including multiple single active region light emitting diodes according to further embodiments.
  • the package 50' is similar to the package 50 illustrated in Figure 7. However, instead of one multi-junction LED chip, the package 50 includes a plurality of singulated single-junction LED chips 60A-60D connected in electrical series by wirebonds 51.
  • a package 50' may have similar advantages for use in LCD backlighting, as the package may generate increased light output for a given level of current while having a higher forward voltage drop over a single packaged component.
  • FIG. 9 is a schematic diagram of a packaged device 50, 50' according to some embodiments.
  • a packaged device 50, 50' may include a single package body having a single anode contact 52 and a single cathode contact 54 made to a group of light emitting diode junctions 14, 60 coupled in electrical series.
  • Figure 10 is a plan view of a light bar 90 including a plurality of light emitting devices 10 according to some embodiments.
  • a light bar 90 includes an elongated support member 70, and a plurality of light emitting devices 1 OA- IOC mounted on the elongated support member 70.
  • Each of the light emitting diode chips 1 OA- IOC may have a structure as illustrated in Figures 1-4.
  • each of the light emitting diode chips 1 OA- IOC may include a support layer 12, 42 having a first face and a second face opposite the first face, a diode region on the first face of the support layer 12, 42, and a die attach pad 30 on the second face of the support layer 12, 42.
  • Each of the bond pads includes a gold-tin structure having a weight percentage of tin greater than 40%.
  • the light emitting diode chips 1 OA- IOC are mounted to the elongated support member by their respective bond pads 30, so that heat generated during operation of the light emitting devices 1 OA- IOC may be at least partially dissipated through the light bar.
  • the light emitting diode chips 1 OA- IOC may be connected in electrical series via anode and cathode contacts 62A-62C, 64A-64C as illustrated in Figure 10. thus, the active regions 14A-14D of each of the light emitting diode chips 1 OA- IOC may be connected in electrical series.
  • Light output from the light bar 90 may thereby enhanced even though the light bar includes fewer light emitting devices 1 OA- IOC, because the light bar 90 still includes a large number of active regions 14A-14D.
  • the light bar can be run at lower current than a light bar having a similar number of conventional light emitting devices with similar active junction areas.
  • the overall level of voltage that is applied to be light bar 90 may be better matched to an external power supply, so that less voltage must be dropped outside the light bar, thereby decreasing the complexity of a system in which the light bar is used.
  • Figure 11 is a plan view of a light bar 90' including a plurality of multiple emitter light emitting diode packages 50 A to 50C according to some embodiments.
  • the LED packages 50A to 50C may have a structure similar to the package 50 illustrated in Figure 7 and/or the package 50' illustrated in Figure 8.
  • the LED packages 50A to 50C may be connected in electrical series. Accordingly, the light bar 90' may have fewer light emitters (the packaged devices 50A to 50C) with higher light emission and higher forward voltage than a light bar that included packages with only one or two LED junctions per package.
  • FIG. 12 is a partial exploded diagram illustrating portions of a backlight assembly for a liquid crystal display screen
  • Figure 13 is a side cross sectional view of an LCD display panel 98 according to some embodiments.
  • a backlight assembly may include a diffuser sheet 95 and a plurality of light bars 90, 90', each including a plurality of light emitters 10, 50 arranged in a linear array to transmit light into an edge of the diffuser sheet 95.
  • Light emitted by the light bars 90, 90' is diffused by the diffuser sheet and transmitted in a direction normal to the figure shown in Figure 12 into an LCD screen 96 to provide
  • Figures 14A, 14B and 14C are cross views of light emitting diode structures according to further embodiments.
  • the light emitting diode structures 11A and 1 IB may be mounted in a flip-chip configuration.
  • the light emitting diode structure 11 A may include a substrate 12, which may be a growth substrate or a carrier substrate on which an active region 15 is provided.
  • the active region 15 may include a p-type epitaxial region 15A and an n- type epitaxial region 15B layered on the substrate 12.
  • a cathode contact 13 is on the substrate 12, while a die attach pad 35 is on the p-type epitaxial region 15A and provides an anode contact for the diode 11 A.
  • the die attach pad 35 may have a structure as described above with respect to Figure 5, and, accordingly, may be configured to reflow at low temperatures but solidify to provide a bond that is stable at high temperatures.
  • the light emitting diode structure 1 IB may be similar to the light emitting diode structure 11 A, except that the substrate 12 has been removed using conventional substrate removal techniques.
  • the light emitting diode structure 11C may be similar to the light emitting diode structure 1 IB, except that the die attach pad 35 is on the n-type epitaxial region 15B and an anode contact 17 is on the p-type epitaxial region 15 A.
  • Embodiments of the present invention may be particularly suitable for direct die attach mounting of an LED die to a package including a submount.
  • the LED die 100 mounted by direct die attachment in a package 200 is illustrated in Figure 15.
  • the LED die 100 includes a diode region 110 having first and second opposing faces 110a, 1 10b, respectively, and including therein an n-type layer 1 12 and a p-type layer 1 14.
  • Other layers or regions may be provided, which may include quantum wells, buffer layers, etc., that need not be described herein.
  • An anode contact 160 ohmically contacts the p-type layer 114 and extends on a first face 110a.
  • the anode contact 160 may directly ohmically contact the p-type layer 1 14, or may ohmically contact the p-type layer 114 by way of one or more conductive vias 162 and/or other intermediate layers.
  • a cathode contact 170 ohmically contacts the n-type layer 112 and also extends on the first face 1 10a.
  • the cathode contact may directly ohmically contact the n-type layer 112, or may ohmically contact the n-type layer 112 by way of one or more conductive vias 172 and/or other intermediate layers. As illustrated in Figure 15, the anode contact 160 and that cathode contact 170 that both extend on the first face 110a are coplanar.
  • the diode region 110 also may be referred to herein as an "LED epi region", because it is typically formed epitaxially on a substrate 120.
  • a Group Ill-nitride based LED epitaxial structure 110 may be formed on a silicon carbide growth substrate.
  • the growth substrate may be present in the finished product.
  • the growth substrate may be removed.
  • another substrate may be provided that is different from the growth substrate.
  • a transparent substrate 120 such as a transparent silicon carbide growth substrate, is included on the second face 110b of the diode region 110.
  • the transparent substrate 120 includes a sidewall 120a and may also include an inner face 120c adjacent the second face 110b of the diode region 110 and an outer face 120b, remote from the inner face 120c.
  • the outer face 120b is of smaller area than the inner face 120c.
  • the sidewall 120a may be stepped, beveled and/or faceted, so as to provide the outer face 120b that is of smaller area than the inner face 120c.
  • the sidewall is an oblique sidewall 120a that extends at an oblique angle ⁇ , and in some embodiments at an obtuse angle, from the outer face 120b towards the inner face 120c.
  • An LED die 100 configured as described above in connection with Figure 15 may be referred to as “horizontal” or “lateral” LEDs, because both the anode and the cathode contacts thereof are provided on a single face of the LED. Horizontal LEDs may be contrasted with vertical LEDs in which the anode and cathode contacts are provided on opposite faces thereof.
  • a conformal layer 140 that comprises phosphor particles 142 is provided on the outer face 120b and on the oblique sidewall 120a.
  • the entire outer face 120b and the entire oblique sidewall 120a are covered with the phosphor layer 140.
  • the entire outer face 120b and/or the entire oblique sidewall 120a need not be covered with the phosphor layer 140.
  • the conformal phosphor layer 140 may be of uniform thickness on the outer face 120b and on the oblique sidewall 120a.
  • the diode region 110 is configured to emit blue light, for example light having a dominant wavelength of about 450-460nm, and the conformal layer comprises yellow phosphor, such as YAG:Ce phosphor.
  • the diode region 110 is configured to emit blue light upon energization thereof, as described above, and the conformal layer 140 may comprise a mixture of a yellow phosphor and red phosphor, such as a CASN-based phosphor.
  • the LED die 100 may be combined with a mounting substrate or submount 180 and a lens 190 to provide a packaged LED 200.
  • the submount 180 may include a submount body 182 that may comprise aluminum nitride (A1N).
  • A1N aluminum nitride
  • metal core substrates, printed circuit boards, lead frames and/or other conventional mounting substrates may be used to mount the LED die 100 in a flip-chip configuration.
  • the submount 180 includes a submount face 182a, and an anode pad 184 and a cathode pad 186 thereon.
  • the anode and cathode pads may comprise silver-plated copper and/or other conductive materials.
  • the LED die 100 is mounted on the submount 180, such that the first face 110a is adjacent the submount face 182a, the outer face 110b is remote from the submount 180, the anode contact 184 is adjacent the anode pad 160, and the cathode contact 186 is adjacent the cathode pad 170.
  • a metal stack 130 including a bonding layer as described herein is used to electrically, thermally and mechanically connect the anode contact 160 to the anode pad 184, and the cathode contact 170 to the cathode pad 186.
  • direct attachment of the anode contact 160 to the anode pad 184, and direct attachment of the cathode contact 170 to the cathode pad 186 may be provided, for example using thermocompression bonding and/or other techniques.
  • a packaged device anode 192 and a packaged device cathode 194 may be provided on package surface, such as a second face 182b of the submount body 182, and may be connected to the anode pad 184 and cathode pad 186, respectively, using internal vias and/or conductive layers that extend on and/or around the submount body 182.
  • the submount body 182 can be formed of many different materials with a preferred material being electrically insulating. Suitable materials include, but are not limited to ceramic materials such as aluminum oxide, aluminum nitride or organic insulators like polyimide (PI) and polyphthalamide (PPA). In other embodiments the submount body 182 can include a printed circuit board (PCB), sapphire or silicon or any other suitable material. For PCB embodiments different PCB types can be used such as standard FR-4 PCB, metal core PCB, or any other type of printed circuit board. As more fully described below, LED packages according to the present invention can be fabricated using a method that utilizes a submount panel sized to accommodate a plurality of submounts. Multiple LED packages can be formed on the panel, with the individual packages being singulated from the panel.
  • PCB printed circuit board
  • submounts 180 that may be used with embodiments described herein, are described in the 787 Publication that was cited above.
  • Various other embodiments of submounts 180 are described in U.S. Patent Application Publication 2009/0108281 to Keller et al, entitled Light Emitting Diode Package and Method for Fabricating Same, assigned to the assignee of the present application, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein (hereinafter referred to as "the '281 Publication").
  • the pad structure on the submount may be modified so as to be used with a horizontal LED die 100 of Figure 15, rather than the vertical LEDs described in the '281 Publication.
  • the packaged LED 200 may also include a lens 190 that extends from submount face 180a to surround the LED die 100.
  • the lens 190 may be a molded plastic lens, as described in detail in the '281 Publication, and may be fabricated on the submount according to techniques that are described in the '281 Publication, and/or other techniques. In some embodiments, the lens may be about 3.06 mm in diameter.
  • Figure 16 is a cross sectional view of a metal die attach pad 130 on a generic semiconductor LED die 100 according to some embodiments.
  • the die attach pad 130 may include a metal stack including an adhesion layer of, e.g., titanium 38 in direct contact with the LED die 100, and a barrier layer of, e.g., platinum 36 on the adhesion layer 38.
  • the adhesion layer 38 may have a thickness of about 5 nm to about 250 nm, and in particular may have a thickness of about 50 nm.
  • the barrier layer 36 may have a thickness of about 100 nm to about 500 nm, and in particular may have a thickness of about 150 nm.
  • the purpose of the barrier layer 36 is to reduce tin migration to the titanium layer 38 during the bonding process.
  • the barrier layer 36 may be formed of a material and having a thickness sufficient to substantially preclude the formation or migration of free metals or alloys that have melting points lower than 300 degrees centigrade.
  • a platinum barrier layer may form a platinum-tin phase with excess molten tin to enhance stability under operation and thermal exposure.
  • the metal stack 130 may include a reflector layer that may be surrounded by a barrier layer to protect the reflective layer.
  • the metal stack 130 may also include a metal that forms an ohmic contact with an underlying semiconductor layer.
  • a bonding layer 134 is provided on the barrier layer 36.
  • the bonding layer 134 includes a layer of nickel 134A on the barrier layer 36, a layer of tin 134B on the nickel layer 134A, and a layer of gold 134C on the tin layer 134B.
  • the bonding layer It is desirable for the bonding layer to reflow at relatively low temperatures when the LED die 100 is initially mounted to a carrier substrate, PCB, header, etc. Although the constituent layers 134A-134C of the bonding layer are deposited as discrete layers, once the device has been bonded, the bonding layer forms an alloy of metals that may have a different melting point than the individual metals have. It is desirable for the melting point of the alloyed bonding layer to be high enough for the bonding metal to be able to withstand subsequent high
  • the alloyed bonding layer it is desirable for the alloyed bonding layer to have a melting point that is at least about 250 degrees centigrade, and in some cases higher than 260 degrees centigrade.
  • the metal of the bonding layer 134 In addition to thermal stability, it is also important for the metal of the bonding layer 134 to have a high shear strength to enable the die attachment to survive mechanical stress, such as may be encountered during subsequent processing steps and/or during use of the device, without delaminating.
  • a weight percentage of nickel in the bonding layer may be at least about 10 percent.
  • a bonding layer having such a composition may have desirable thermal and/or mechanical characteristics, particularly for bonding an LED chip to a submount in a device package.
  • Increasing the thickness of tin in the metal stack to greater than 2 microns, and in some cases up to 3 microns or more, can reduce the formation of voids during the attachment process, which may improve the thermal resistance of the metal stack.
  • the nickel layer 134 A may have a thickness greater than about 400 nm, and in particular may have a thickness of about 600 nm. Because tin is relatively soft, it may be desirable to increase the amount of nickel in the bonding layer to increase the mechanical strength of the bonding layer.
  • the thickness of the layer of tin 34B may be greater than about 2 microns (2000 nm), in some cases greater than about 2.5 microns (2500 nm) and in some cases may be at least about 3 microns (3000 nm).
  • the entire metal stack including adhesion, barrier, bonding and other layers, may be less than an 6 microns thick to enhance the mechanical stability of the die attach.
  • the weight percentage of tin in the bonding layer may be less than 80 percent. In some embodiments, the weight percentage of tin in the bonding layer may be between about 70 percent and 80 percent. [00132] The weight percentage of gold the bonding layer 134 may be less than about 5 percent, and in some embodiments, the weight percentage of gold the bonding layer may be less than about 2 percent. The entire metal stack 130 may contain gold in an amount of less than 5 percent by weight.
  • the bonding layer may include a metal alloy that is more than 90 percent nickel and tin by weight. In some embodiments, the metal alloy of the bonding layer may be more than 95 percent nickel and tin by weight, and in some embodiments more than 97 percent nickel and tin by weight.
  • the bonding layer Prior to initial bonding, the bonding layer may have a relatively low initial melting temperature.
  • the initial melting temperature of the bonding layer may be less than 250 degrees centigrade. In some embodiments, the initial melting temperature of the bonding layer may be less than 240 degrees centigrade and in some embodiments less than 230 degrees centigrade.
  • the bonding layer may include a metal alloy that is thermally stable at temperatures up to 260 degrees centigrade. In some embodiments, the metal alloy of the bonding layer may be thermally stable at temperatures up to 290 degrees centigrade. In further embodiments, the metal alloy of the bonding layer may be thermally stable at temperatures up to 310 degrees centigrade, and in still further, the metal alloy of the bonding layer may be thermally stable at temperatures up to 320 degrees centigrade.
  • the LED die 100 including the metal stack 130 may be bonded onto a submount body 182, including a metal die attach pad 186.
  • the submount body 182 has a top surface including patterned conductive features that can include a die attach pad 186.
  • the LED can be mounted to the die attach pad 186 using known methods and material mounting such as using conventional solder materials that may or may not contain a flux material or dispensed polymeric materials that may be thermally and electrically conductive.
  • the size of the submount body 182 can vary depending on different factors, with one being the size of the LED.
  • the size of the package can be essentially of the same dimension as the effective heat spreading area in the attach pad.
  • the submount In a package having a 1 mm LED die, the submount can be approximately 3.5 mm by 3.5 mm; with a package having a 0.7 mm die it can be 3.2 mm by 3.2 mm and generally of square shape in both cases. It is further understood that the submount can have other shapes including circular, rectangular or other multiple sided shapes.
  • the die attach pad 186 can include much different material such as metals or other conductive materials.
  • the attach pad 186 includes copper deposited using known techniques such as plating. In typical plating process a titanium adhesion layer and copper seed layer are sequentially sputtered onto a substrate. Then, approximately 75 microns of copper is plated onto the copper seed layer. The resulting copper layer being deposited can then be patterned using standard lithographic processes. In other embodiments the layer can be sputtered using a mask to form the desired pattern. In further embodiments a capping layer of silver can be formed over the copper layer.
  • the die attach pad 186 can be plated or coated with additional metals or materials to the make the die attach pad 186 more suitable for mounting an LED die 100.
  • the die attach pad 186 can be plated with adhesive or bonding materials, or reflective and barrier layers.
  • the bonding layer melts, and the constituent layers of the bonding layer alloy to form an alloyed bonding layer 150 that is in some embodiments an alloy of nickel, tin and gold.
  • Figures 18A and 18B are graphs of differential scanning calorimetry (DSC) results for several different metal stacks.
  • DSC differential scanning calorimetry
  • thermoanalytical technique in which the difference in the amount of heat required to increase the temperature of a test sample and a reference sample is measured as a function of temperature. DSC analysis can be used to identify phase changes of a test sample.
  • Figure 18A illustrates DSC results for a first DSC test of three different metal stacks
  • Figure 18B illustrates DSC results for three repeated DSC tests of the three different metal stacks that have already been re-flowed and melted.
  • graph 202 is a graph of DSC results for a first metal stack (Stack A) consisting of 50 nm of titanium, 150 nm of platinum, 300 nm of nickel, 100 nm of gold, 2 microns of tin, and 30 nm of gold.
  • Graph 204 is a graph of DSC results for a second metal stack (Stack B) consisting of 15 nm of titanium, 200 nm of nickel, and 3 microns of 80/20 gold/tin.
  • Graph 206 is a graph of DSC results for a third metal stack (Stack C) consisting of 50 nm of titanium, 150 nm of platinum, 600 nm of nickel, 3 microns of tin, and 30 nm of gold.
  • Stack C had the lowest melting point at less than 230 degrees centigrade.
  • Stack A had a melting point of about 260 degrees centigrade, while Stack B had a melting point of about 285 degrees centigrade.
  • a metal stack including a bonding layer as described above may be well suited for lead-free manufacturing processes, which typically require relatively high temperatures.
  • a metal stack including a bonding layer as described above may be well suited for multiple lead-free reflow profiles that may be encountered during subsequent processing steps.
  • a metal stack including a bonding layer as described above may be highly durable, and may not significantly corrode even when subjected to extreme environments, such as high temperature, high humidity environments for extended time periods. Thus, such metal stacks may be well suited for long-lifetime applications in various different types of devices and/or packages.
  • Metal stacks as described herein may be particularly suitable for mounting LED devices to package submounts, as they provide mechanical and/or electrical attachments with high thermal stability and/or high thermal strength with high electrical conductivity and/or low thermal resistance.
  • Figures 19A, 19B, 20 and 21 are cross-sectional views semiconductor LED die mounted in various packages using metal die attach stacks in accordance with some embodiments.
  • Figure 19A shows an LED die 100 including a die attach metal stack 130 as disclosed above that is flip-chip mounted onto a submount including a submount body 182 and a die attach pad 186.
  • the LED die 100 includes a p-type region 114 and an n-type region 112.
  • the LED die may include a growth substrate on which the epitaxial layers comprising the LED are grown, a carrier substrate onto which the epitaxial layers are transferred, or no substrate.
  • the metal stack 130 includes adhesion and barrier layers 38, 36 and a eutectic bonding layer 134 on the adhesion and barrier layers.
  • the bonding layer 134 includes a layer of nickel 134A, a layer of tin 134B on the nickel layer 134A, and a layer of gold 134C on the tin layer 134B.
  • the die attach metal stack 130 of the LED die 100 is brought into contact with the die attach pad 186, and sufficient heat and/or force is applied to the die to cause the bonding layer to refiow, forming an alloyed bond layer 150 that holds the die 100 in place on the submount body 182.
  • An encapsulant, such as silicone, is then dispensed to form a dome lens on the submount body 182 over the attached die 100.
  • LED chips 100 may be mounted using a die attach metal stack 130 with the n-side down and wirebond connections 178 made to anode and cathode contacts 183, 185 formed on the p-type 1 14 and n-type 112 layers of the LED die 100, respectively.
  • multiple LED die 100 are mounted on a submount body 182 and wirebonded.
  • An encapsulant dam 172 is formed on the submount body, and a liquid encapsulant is dispensed onto the submount body within the encapsulant dam to cover the attached LED die.
  • Figure 21 illustrates embodiments in which multiple LED die 100 are flip-chip mounted onto a submount body 182 using die attach metal stacks 130 formed on the cathode and anode contacts 170, 160 on the n-type and p-type layers 114, 112 of the LED die that bond to respective die attach pads 186 on the submount body 182.
  • An encapsulant dome 190 is then formed on the submount body 182 over the attached LED die.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Device Packages (AREA)

Abstract

La présente invention concerne une structure de diode émettant de la lumière comportant une région de diode et un empilement en métal sur la région de diode. L'empilement en métal comporte une couche barrière sur la région de diode et une couche de liaison placée sur la couche barrière. La couche barrière se trouve entre la couche de liaison et la région de diode. La couche de liaison comprend de l'or, de l'étain et du nickel. Le pourcentage en poids de l'étain dans la couche de liaison est supérieur à 20 pour cent et le pourcentage en poids de l'or dans la couche de liaison est inférieur à 75 pour cent. Le pourcentage en poids du nickel dans la couche de liaison peut être supérieur à 10 pour cent.
EP13743107.8A 2012-01-30 2013-01-25 Empilement en métal à haute résistance et à faible température pour fixation de puce Withdrawn EP2810307A1 (fr)

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US13/361,569 US9443903B2 (en) 2006-06-30 2012-01-30 Low temperature high strength metal stack for die attachment
PCT/US2013/023041 WO2013116086A1 (fr) 2012-01-30 2013-01-25 Empilement en métal à haute résistance et à faible température pour fixation de puce

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US9601673B2 (en) 2014-11-21 2017-03-21 Cree, Inc. Light emitting diode (LED) components including LED dies that are directly attached to lead frames

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US7141828B2 (en) * 2003-03-19 2006-11-28 Gelcore, Llc Flip-chip light emitting diode with a thermally stable multiple layer reflective p-type contact
US7329905B2 (en) * 2004-06-30 2008-02-12 Cree, Inc. Chip-scale methods for packaging light emitting devices and chip-scale packaged light emitting devices
US8643195B2 (en) * 2006-06-30 2014-02-04 Cree, Inc. Nickel tin bonding system for semiconductor wafers and devices
US7910945B2 (en) * 2006-06-30 2011-03-22 Cree, Inc. Nickel tin bonding system with barrier layer for semiconductor wafers and devices
KR100854328B1 (ko) * 2006-07-07 2008-08-28 엘지전자 주식회사 발광 소자 패키지 및 그 제조방법
US7985970B2 (en) * 2009-04-06 2011-07-26 Cree, Inc. High voltage low current surface-emitting LED
WO2009119841A1 (fr) * 2008-03-28 2009-10-01 三菱化学株式会社 Composition de polysiloxane durcissable, et produit durci en polysiloxane, élément optique, élément pour l’industrie aérospatiale, dispositif semi-conducteur émettant de la lumière, système d’éclairage, et dispositif d’affichage d’image utilisant la composition de polysiloxane durcissable
TWI401825B (zh) * 2009-11-27 2013-07-11 Ind Tech Res Inst 發光二極體晶片的固晶方法及固晶完成之發光二極體

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