EP2746845A1 - Verfahren zur herstellung einer elektrode für einen ips-bildschirm - Google Patents

Verfahren zur herstellung einer elektrode für einen ips-bildschirm Download PDF

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Publication number
EP2746845A1
EP2746845A1 EP12877081.5A EP12877081A EP2746845A1 EP 2746845 A1 EP2746845 A1 EP 2746845A1 EP 12877081 A EP12877081 A EP 12877081A EP 2746845 A1 EP2746845 A1 EP 2746845A1
Authority
EP
European Patent Office
Prior art keywords
ito layer
etched
ito
layer
annealing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP12877081.5A
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English (en)
French (fr)
Other versions
EP2746845A4 (de
EP2746845B1 (de
Inventor
Yanfeng LIAN
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai AVIC Optoelectronics Co Ltd
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Shanghai AVIC Optoelectronics Co Ltd
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Publication of EP2746845A4 publication Critical patent/EP2746845A4/de
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods

Definitions

  • the present invention relates to the field of displays and particularly to a method of fabricating In-Plane Switching (IPS) screen electrode.
  • IPS In-Plane Switching
  • IPS In-Plane Switching
  • An IPS screen fabricated with this technology is predominantly characterized in that two electrodes are in the same plane and the alignment of liquid crystal molecules is optimized so that they are aligned horizontally. Being under an external pressure, the molecules are structurally depressed downward slightly but still generally appear horizontal without a distortion of an image and without degrading a picture in color. Due to the foregoing advantages, the IPS screen plays a role of increasing importance in the field of displays.
  • IPS screen electrodes include two Indium Tin Oxide (ITO) layers, which are a pixel ITO layer and a common ITO layer respectively.
  • ITO Indium Tin Oxide
  • the pixel ITO layer and the common ITO layer are typically fabricated concurrently in order to ensure the consistency of transmittance, resistivity and other important parameters between the pixel ITO layer and the common ITO layer.
  • concurrent fabrication of both the ITO layers may result in a lowered spacing between the respective ITO layers, which in turn may easily have the ITO layers electrically connected causing a short circuit, and the performance of the product may be lowered if the spacing between the respective ITO layers is ensured by reducing the line widths of the ITO layers.
  • Embodiments of the invention provide a method of fabricating an IPS screen electrode so as to address the problem in the prior art that concurrent fabrication of both a pixel ITO layer and a common ITO layer may result in a lowered spacing between the respective ITO layers, which may easily cause a short circuit.
  • An embodiment of the invention provides a method of fabricating an IPS screen electrode, the method including:
  • An embodiment of the invention provides a method of fabricating an IPS screen electrode, and in the method, firstly a first ITO layer is etched, and the etched first ITO layer is annealed, then a second ITO layer is etched, and finally the etched first ITO layer and the etched second ITO layer are annealed concurrently.
  • the etched first ITO layer is annealed after the first ITO layer is etched, subsequent etching of the second ITO layer will have no influence upon the annealed first ITO layer, thus making it possible to ensure the line widths of the two ITO layers and a spacing between the respective ITO layers to thereby effectively avoid the problem of a short circuit due to a too small spacing between the respective ITO layers.
  • Fig.1 is a process of fabricating an IPS screen electrode according to an embodiment of the invention, the process particularly including the following steps:
  • the first ITO layer may be exposed and developed to define a shape into which the first ITO layer is to be etched, and then the first ITO layer may be etched.
  • the exposed part thereof is the part to be etched away using oxalic acid, and the unexposed part is the part to remain, so after the first ITO layer is exposed and developed, the exposed part after being exposed and developed can be etched using oxalic acid.
  • the etched first ITO layer is annealed at the preset temperature and for the first preset length of time, which is referred to first annealing.
  • the second ITO layer is exposed and developed to define a shape into which the second ITO layer is to be etched, and then the second ITO layer is etched using oxalic acid.
  • the part to be etched using oxalic acid may further include the part of the annealed first ITO layer in addition to the exposed part of the second ITO layer, and since the first annealing has been performed on the etched first ITO layer, the annealed first ITO layer will not be etched away.
  • S104 annealing the etched first ITO layer and the etched second ITO layer for a second preset length of time at the preset temperature.
  • the etched first ITO layer and the etched second ITO layer are annealed concurrently for the second preset length of time at the same preset temperature as in the first annealing, which is referred to second annealing.
  • the preset temperature adopted for the first annealing and the second annealing may be controlled from 150 °C to 280 °C.
  • the foregoing sum of the first preset length of time and the second preset length of time may be controlled not to exceed 4 hours.
  • the two ITO layers are annealed at the same temperature, and also the two ITO layers are annealed for the approximate lengths of time, so the consistency of important parameters (e.g., resistivity, transmittance, etc.) between the two ITO layers can be ensured.
  • important parameters e.g., resistivity, transmittance, etc.
  • the first ITO layer can be a pixel ITO layer, and the second ITO layer can be a common ITO layer.
  • the first ITO layer can be a common ITO layer, and the second ITO layer can be a pixel ITO layer.
  • both the first ITO layer and the second ITO layer are etched to 4 micrometers ( ⁇ m) in line width, and there is a spacing of 3 micrometers ( ⁇ m) between the etched first ITO layer and the etched second ITO layer.
  • the first ITO layer is a common ITO layer and the second ITO layer is a pixel ITO layer.
  • Fig.2 is a sectional view of an electrode after the first ITO layer using as a common ITO layer is exposed and developed according to an embodiment of the invention, and as illustrated in Fig.2 , because the first ITO layer is a common ITO layer, it covers a data line with a line width of 3 ⁇ m.
  • the first ITO layer will be etched to 4 ⁇ m in line width, and in view of some etching loss, for example, 2 ⁇ m here, when the first ITO layer is etched after being exposed and developed in a practical application, then the line width of the first ITO layer is 6 ⁇ m after the first ITO layer is exposed and developed as illustrated in Fig.2 .
  • a blank part illustrated in Fig.2 is an exposed part after being exposed and developed, that is, the part to be etched away using oxalic acid, and the rest is the part to remain.
  • Fig.3 is an effect view of the exposed and developed first ITO layer as illustrated in Fig.2 after being etched according to an embodiment of the invention.
  • the line width of the exposed and developed first ITO layer is 6 ⁇ m and there is an etching loss of 2 ⁇ m during etching
  • the line width of the etched first ITO layer in as illustrated Fig.3 is 4 ⁇ m satisfying the standard.
  • the etched first ITO layer is annealed for a first preset length of time at a temperature from 150 °C to 280 °C, and then the second ITO layer is exposed and developed.
  • Fig.4 is a sectional view of an electrode after the second ITO layer using as a pixel ITO layer is exposed and developed according to an embodiment of the invention, and as illustrated in Fig.4 , the second ITO layer which is a pixel ITO layer will also be etched to 4 ⁇ m in line width, so in view of an etching loss of 2 ⁇ m, the line width of the second ITO layer is also 6 ⁇ m after the second ITO layer is exposed and developed.
  • the part to be etched using oxalic acid may further include the part of the first ITO layer subjected to etching and the first annealing in addition to the blank part, and the rest is the part to remain.
  • Fig.5 is an effect view of the exposed and developed second ITO layer as illustrated in Fig.4 after being etched according to an embodiment of the invention.
  • the line width of the exposed and developed second ITO layer is 6 ⁇ m and there is an etching loss of 2 ⁇ m during etching
  • the line width of the etched second ITO layer as illustrated in Fig.5 is 4 ⁇ m, satisfying the standard.
  • the first annealing has been performed on the etched first ITO layer before the second ITO layer is etched, when the part of the first ITO layer subjected to the first annealing as illustrated in Fig.4 is etched using oxalic acid, the first ITO layer will not be etched away. There is a spacing of 3 ⁇ m between the etched first ITO layer and the etched second ITO layer.
  • both the first ITO layer and the second ITO layer are 6 ⁇ m in line width, and there is a spacing of only 1 ⁇ m between the first ITO layer and the second ITO layer, which is almost undistinguishable by an exposure machine due to a limited resolution of the exposure machine. As a result, a short circuit may easily occur between the two ITO layers during etching.
  • the two ITO layers are fabricated in separate steps, where firstly the exposed and developed first ITO layer as illustrated in Fig.2 is etched to have the blank part as illustrated in Fig.2 etched away, and then the exposed and developed second ITO layer as illustrated in Fig.4 is etched. Particularly the blank part as illustrated in Fig.4 and the part of the annealed first ITO layer are etched (the part of the annealed first ITO layer will not be etched away), thus avoiding the problem of a short circuit between the two ITO layers due to a limited resolution of the exposure machine.
  • the first ITO layer and the second ITO layer are etched separately in two steps, the second etching will have no influence upon the initially formed ITO layer, and the lengths of time and the temperatures of both annealing are controlled effectively, thus making it possible to effectively control the line widths of the ITO layers and the spacing between the respective ITO layers while ensuring the differences in important parameters between the two ITO layers not to be significant to thereby avoid the problem of a short circuit due to a too small spacing between the ITO layers.
EP12877081.5A 2012-09-20 2012-11-21 Verfahren zur herstellung einer elektrode für einen ips-bildschirm Active EP2746845B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201210353106.0A CN103676344B (zh) 2012-09-20 2012-09-20 一种制造平面转换ips屏幕电极的方法
PCT/CN2012/084960 WO2014043992A1 (zh) 2012-09-20 2012-11-21 一种制造平面转换ips屏幕电极的方法

Publications (3)

Publication Number Publication Date
EP2746845A1 true EP2746845A1 (de) 2014-06-25
EP2746845A4 EP2746845A4 (de) 2015-03-25
EP2746845B1 EP2746845B1 (de) 2016-04-06

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EP12877081.5A Active EP2746845B1 (de) 2012-09-20 2012-11-21 Verfahren zur herstellung einer elektrode für einen ips-bildschirm

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EP (1) EP2746845B1 (de)
CN (1) CN103676344B (de)
WO (1) WO2014043992A1 (de)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6448158B2 (en) * 2000-08-04 2002-09-10 Hannstar Display Corp. Method of patterning an ITO layer
US20040119915A1 (en) * 2002-12-23 2004-06-24 Lg.Philips Lcd Co., Ltd. Liquid crystal display device and method of fabricating the same
US20120105781A1 (en) * 2010-10-28 2012-05-03 Ah-Ram Lee Liquid crystal display device and manufacturing method thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5191452A (en) * 1989-09-20 1993-03-02 Honeywell Inc. Active matrix liquid crystal display fabrication for grayscale
JP4902284B2 (ja) * 2006-07-14 2012-03-21 株式会社 日立ディスプレイズ 半透過型液晶表示装置
JP5372900B2 (ja) * 2010-12-15 2013-12-18 株式会社ジャパンディスプレイ 液晶表示装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6448158B2 (en) * 2000-08-04 2002-09-10 Hannstar Display Corp. Method of patterning an ITO layer
US20040119915A1 (en) * 2002-12-23 2004-06-24 Lg.Philips Lcd Co., Ltd. Liquid crystal display device and method of fabricating the same
US20120105781A1 (en) * 2010-10-28 2012-05-03 Ah-Ram Lee Liquid crystal display device and manufacturing method thereof

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2014043992A1 *

Also Published As

Publication number Publication date
EP2746845A4 (de) 2015-03-25
CN103676344A (zh) 2014-03-26
CN103676344B (zh) 2017-03-22
WO2014043992A1 (zh) 2014-03-27
EP2746845B1 (de) 2016-04-06

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