EP2721735B1 - Dispositif de commutation comprenant un commutateur statique et un circuit de commande associé - Google Patents

Dispositif de commutation comprenant un commutateur statique et un circuit de commande associé Download PDF

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Publication number
EP2721735B1
EP2721735B1 EP20120738085 EP12738085A EP2721735B1 EP 2721735 B1 EP2721735 B1 EP 2721735B1 EP 20120738085 EP20120738085 EP 20120738085 EP 12738085 A EP12738085 A EP 12738085A EP 2721735 B1 EP2721735 B1 EP 2721735B1
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EP
European Patent Office
Prior art keywords
uzk
voltage
switching
circuit
actuation
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EP20120738085
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German (de)
English (en)
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EP2721735A1 (fr
Inventor
Karsten Handt
Marc Hiller
Rainer Sommer
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Siemens AG
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Siemens AG
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/12—Modifications for increasing the maximum permissible switched current
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
    • H03K17/0828—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in composite switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/10—Modifications for increasing the maximum permissible switched voltage
    • H03K17/107—Modifications for increasing the maximum permissible switched voltage in composite switches

Definitions

  • the invention relates to a circuit arrangement with a semiconductor switch, which is connected via its control input to a drive circuit which is designed to switch the semiconductor switch in response to a predeterminable switching signal.
  • the circuit arrangement can be used in a frequency converter.
  • the invention also relates to a method for operating a semiconductor switch with associated drive circuit.
  • a circuit arrangement of this kind is known from WO 2008/032113 A1 known.
  • Such a circuit may be provided, for example, in a DC or an inverter of a controllable inverter, as it can be used to operate a three-phase machine.
  • an inverter 10 can be generated by means of a DC voltage Uzk in phase conductors 12, 14, 16 alternating currents 11, 12, 13, which together form a three-phase current, with which an electric machine 18 can be operated.
  • the DC voltage Uzk can be provided, for example, between two busbars ZK +, ZK- of an intermediate circuit of a frequency converter.
  • the phase conductors 12, 14, 16 each have a half-bridge 20, 22, 24 with the busbars ZK +, ZK- in the in FIG. 1 connected way shown. How the alternating currents I1, I2, I3 are generated is explained below in connection with the half-bridge 20. The same applies to the alternating currents I2 and I3 in conjunction with the half bridges 22 and 24th
  • the half-bridge 20 has two semiconductor power switches 26, 28, each of which has a transistor Tr1 and Tr2 and a diode V1 or V2 connected in anti-parallel with it. Via the semiconductor power switches 26, 28, the phase conductor 12 is once connected to the positive busbar ZK + and once with the minus busbar ZK-.
  • the transistors Tr1, Tr2 may be e.g. IGBT (insulated gate bipolar transistor) or MOSFET (metal oxide semiconductor field effect transistor) act.
  • the semiconductor power switches 26, 28 are each connected via a control line 30, 32 to a control unit 34.
  • the control unit 34 generates a clock signal 36, which is transmitted via the control line 30 to the semiconductor power switch 26.
  • the transistor Tr1 of the semiconductor power switch 26 is alternately switched to a conducting and a blocking state.
  • the control unit 34 transmits a push-pull signal to the semiconductor power switch 26, so that the transistor Tr2 of the semiconductor power switch 28 is switched in a push-pull manner to the transistor Tr1.
  • the alternating switching of the transistors Tr1 and Tr2 generates in the phase conductor 12 an alternating voltage and thus the alternating current I1.
  • correspondingly phase-shifted clock signals are transmitted by control unit 34 via further control lines to power switches of the remaining half-bridges 22 and 24.
  • the clock signals generated by the control unit 34 are usually not present in a form in order to be able to directly control a semiconductor power switch. Therefore, a control circuit 40 is connected upstream of a control input 38 of the semiconductor power switch 26, which generates a control voltage at the control input 38 as a function of the clock signal 36 by means of an amplifier circuit (not shown).
  • the control input 38 is in the case of a transistor whose gate or Base.
  • the semiconductor power switch 28 is a corresponding drive circuit and are also connected upstream of the circuit breakers of the bridges 22 and 24 corresponding drive circuits.
  • a large power e.g. more than 50 kW
  • a higher total operating voltage ie a higher DC voltage Uzk
  • this possibility is limited by the maximum blocking voltage capability of the semiconductor power switches Tr1, Tr2.
  • operating a semiconductor power switch at a voltage that is close to the maximum allowable reverse voltage causes greater wear of this device than operating at a significantly lower voltage.
  • a method for limiting a potential at the collector of a turn-off power semiconductor switch during a shutdown is described.
  • the method is provided for limiting the potential during a turn-off operation in a series connection of a plurality of identical power semiconductor switches. It is continuously determined an actual value of the collector potential and determined by an additional time measurement, an actual voltage gradient. If the voltage gradient is too great, that is, the collector voltage rises too fast over time, a drive signal is generated, by which the switch-off process is slowed down.
  • the circuit arrangement according to the invention has a series connection of at least two semiconductor switches, ie a series connection of the load paths of these semiconductor switches.
  • its load path is the collector-emitter path, drain-source path or anode-cathode path.
  • each drive circuit switches its associated semiconductor switch in the manner already described.
  • each drive circuit has a specific switching behavior, ie, for example, a specific switching delay or a regulating behavior, by which the voltage across the semiconductor switch is limited to a maximum value.
  • its switching behavior can be determined by at least one digital switching parameter in at least one of the drive circuits.
  • the value of the switching parameter can be changed, so that the switching behavior during operation, ie between two switching operations, is adjustable.
  • This has the advantage that the semiconductor switches can also be operated gently in a series connection.
  • an uneven voltage distribution would occur during the switching operations on the one hand and in the static blocking phase when all the semiconductor switches are turned off.
  • a current total value for at least one total operating variable of the series connection is determined.
  • the total value may therefore be e.g. be determined for at least one of the total operating variables described below: It can be determined a maximum value of a voltage drop across the series connection during a switching operation. This voltage value may be greater than the total operating voltage, for example, if inductors induce an additional voltage during the switching process. In the same way, a voltage value of a supply voltage, ie the total operating voltage, can be determined.
  • the total operating voltage is that electrical voltage which is generated by a voltage source whose output current is to be switched by means of the series connection.
  • Another value is a jitter value, by which a time offset between the beginning of switching operations of the drive circuits is specified. Such a time-shifted switching of the semiconductor switches, as caused by jitter, it may happen that the total operating voltage during the staggered switching of the individual semiconductor switches completely falls over one of these, whereby this is then excessively loaded.
  • At least one drive circuit is provided with a voltage monitoring device which is designed to monitor a voltage dropping across the semiconductor switch triggered by the drive circuit (for example, a collector-emitter voltage). If the voltage is greater than a threshold, the voltage monitor acts on the switching process to reduce the voltage to less than or equal to the threshold.
  • the limit value is adjustable as a switching parameter of the drive circuit in the manner described. One possible limit is the fractional stress that results from dividing the maximum voltage produced during a switching operation by induction.
  • At least one of the drive circuits can be set as a switching parameter, a voltage end value, which should have a voltage drop across the semiconductor switch triggered by the drive circuit at the end of a switching operation.
  • the drive circuit is in this case designed to generate at least one balancing pulse at the control input of the semiconductor switch for setting the voltage end value at the end of the switching process.
  • the symmetrizing pulse ensures that the controlled semiconductor switch briefly changes its switching state (from blocking to conducting or vice versa) and thereby the voltage drops across the individual semiconductor switches partial voltages are adjusted in their voltage values.
  • the voltage end value is adjustable as a switching parameter, it can always be achieved even with variable total operating voltage that the partial voltages are at least approximately equal, so that the semiconductor switches are evenly loaded.
  • a switching delay is adjustable.
  • This drive circuit is designed to start a switching process delayed by the set switching delay after receiving the switching signal.
  • a further advantage results if at least one of the drive circuits has a voltage measuring device for measuring a voltage drop across at least one of the semiconductor switches and a measuring output on which a measured value can be read out. Then, by means of the circuit arrangement, a current total operating voltage can be determined.
  • this may be designed to exchange a signal via an optical fiber connection with an external device.
  • one of the drive circuits is operated as a master drive and the at least one other as a slave drive.
  • slave drive is meant that this drive circuit exchanges data with a signaling device of the circuit arrangement which generates the switching signals for the drive circuits, via the master drive. Since only the master drive directly exchanges data with the signaling device, only a very few communication lines are needed to exchange data between the signaling device and the drive circuits.
  • FIG. 2 a drive circuit 42 is shown, which in a (in FIG. 2 not shown) controllable inverter of a frequency converter is installed.
  • the inverter corresponds in its function to the in FIG. 1 shown inverter.
  • the drive circuit 42 controls a semiconductor power switch 44.
  • This has a transistor 46 (here an IGBT) and a diode 48 connected to this anti-parallel.
  • a MOSFET can also be provided.
  • the drive circuit 42 For controlling the semiconductor power switch 44, the drive circuit 42 generates a control voltage at a control input 50 of the semiconductor power switch 44.
  • the control input 50 corresponds here to the gate of the IGBT.
  • a current Ic is switched controlled.
  • the control voltage at the control input 50 is generated in response to a switching signal S1, which receives the drive circuit 42 via a light receiver or input optocoupler 52 through which the drive circuit 42 is connected to a signal line 54 of an inverter controller (not shown).
  • the signal line 54 comprises an optical waveguide.
  • the inverter controller comprises a signaling device of the inverter.
  • the switching signal S1 is evaluated by a programmable controller 56.
  • the controller 56 may for example, be provided by an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit).
  • the inverter control determines whether the semiconductor power switch 44 should be in a conducting or a blocking state.
  • the controller 56 generates a corresponding digital signal to which a digital-to-analog converter 58 generates an analog signal.
  • the analog signal is amplified by an amplifier circuit 60 and transmitted as a control voltage via a gate resistor 62 to the control input 50.
  • the drive circuit 42 may be operated without a gate resistor.
  • a digital filter or a digital control may be provided to generate from the switching signal S1 of the inverter control a suitable for driving the semiconductor power switch 44 digital signal.
  • protective functions e.g. to provide for the semiconductor power switch 44.
  • the controller 56 forms a digital interface between the inverter controller and the semiconductor power switch 44.
  • the drive circuit 42 has a voltage measuring device 64, with which a diode voltage Ud is detected.
  • the diode voltage Ud here also corresponds to the collector-emitter voltage Uce of the transistor 46.
  • an analog-digital converter 66 the detected voltage value is converted into a digital measured value, which is evaluated by the control device 56.
  • the diode voltage Ud represents a voltage drop across the semiconductor circuit breaker 44 driven by the drive circuit 42.
  • the signal line 70 comprises an optical waveguide.
  • a fault-tolerant transmission protocol is used, so that even in a falsification of the data, for example by electromagnetic interference, the originally transmitted information (up to a certain Degree of corruption) can be reconstructed again from the corrupted data.
  • a transmission protocol are a Barker code and a cyclic code.
  • a change in the switching state of the semiconductor power switch 44, ie from conducting to blocking or vice versa, by the inverter control is specified by the switching signal S1 of the control line 54, then a corresponding switching operation by changing the control voltage at the control input 50 causes by the drive circuit 42.
  • the switching behavior of the control circuit 42 is determined by switching parameters of the control device 56 whose values can be changed during the operation of the drive circuit 42. The values for the switching parameters can be transmitted to the control circuit 42 together with the switching signal S1 via the control line 54 from the inverter control to the control device 56.
  • FIG. 3 a curve of the current intensity of the current Ic and the collector-emitter voltage Uce during a shutdown over the time t is plotted.
  • To interrupt the current Ic its current is gradually reduced, so that the time course of the current during the switching process a finite slope (derivative of Ic to the time during shutdown).
  • the course of the voltage Uce has an overshoot 72 during the switch-off process, which is caused by a voltage which is caused by a (in FIG. 2 not shown) inductance when switching off the current Ic is generated.
  • a maximum voltage value K1 * Uzk of the collector-emitter voltage Uce represents a limit value which may not be exceeded.
  • the maximum voltage value K1 * Uzk is formed as a partial voltage value from a current value of a DC voltage Uzk.
  • the DC voltage Uzk is an operating voltage of the inverter. It is provided in a DC link of the frequency converter to which the inverter is connected.
  • the DC voltage Uzk is also referred to below as the intermediate circuit voltage Uzk.
  • the voltage value for the intermediate circuit voltage Uzk has been determined by the inverter controller as a total operating variable.
  • the maximum voltage value K1 * Uzk is adjustable as a switching parameter at the control device 56.
  • the voltage measuring device 64, the analog-digital converter 66 and the control device 56 in this context form a voltage monitoring device in the form of a regulator for the diode voltage Ud or Uce.
  • the desired voltage maximum value K1 * Uzk has been transmitted to the drive circuit 42 via the control line 54 together with the switching signal S1.
  • a current voltage value U1max during the switching operation is detected by means of the voltage measuring device 64. If the current voltage value U1max becomes greater than the maximum voltage value K1 * Uzk, the switching operation is slowed down by the controller 56, so that the magnitude of the slope of the current waveform of Ic decreases.
  • the voltage end value K2 * Uzk can be predeterminable, which is the voltage Uce at the end of the Shutdown should have.
  • the control device 56 may be made for the control device 56 to switch the semiconductor power switch 44 one or more times briefly by generating a symmetrizing pulse from the blocking to the conducting state, so that a current flow is possible for a short time and thereby a current flow Voltage shift in the inverter is possible.
  • a current voltage value U1 is detected by the voltage measuring device 64.
  • a switching delay value dt1 may be set at the control device 56 as a switching parameter.
  • the switching delay value dt1 indicates the period of time after which the controller 56 starts the switching operation after being requested by the inverter control by the switching signal S1. The switching process is then initiated by the control input 50, the gate-emitter voltage Uge corresponding to the in FIG. 3 changed course is changed.
  • a half-bridge is shown with two half-bridge branches 74, 76 of the inverter in which the drive circuit 42 and the semiconductor power switch 44 are installed.
  • the half-bridge branches 74, 76 each represent an embodiment of the circuit arrangement according to the invention, wherein the (not shown) inverter control is to be regarded as part of the circuit arrangement.
  • the semiconductor power switch 44 is connected to a series circuit 80 together with another semiconductor power switch 78. As in FIG. 4 is indicated by ellipsis "", in addition to the two semiconductor power switches 44 and 78, further semiconductor power switches may be included in the series circuit 80.
  • the total number of semiconductor power switches connected in series in the series circuit 80 is denoted by n below.
  • an alternating current I1 is generated in the inverter.
  • the alternating current I1 corresponds to the alternating current with the same reference numeral in the inverter of FIG. 1
  • the series circuit 80 corresponds in function to the individual semiconductor power switch 26 of FIG FIG. 1 shown inverter. In the inverter whose half-bridge in FIG. 4 however, it is possible, through series connection 80, for the inverter to be operated with an intermediate circuit voltage Uzk which is greater than a maximum reverse voltage which may at most fall above a single one of the semiconductor power switches 44, 78.
  • one of the half-bridge branches 74, 76 is alternately switched to a conducting state and the other half-bridge branch 76, 74 is switched to a blocking state. Over one of the two semiconductor branches 74, 76 thus almost always drops the entire DC link voltage Uzk.
  • the semiconductor power switch 78 is connected via a control input to its own drive circuit 82, which corresponds in its operation to the drive circuit 42.
  • the drive circuit 82 receives a switching signal Sn from the inverter controller via a control line 84.
  • the half-bridge branch 76 corresponds in its construction to the half-bridge branch 74. Therefore, the elements of the half-bridge branch 76 are not explained in detail.
  • FIG. 5 to FIG. 7 It is shown how the drive circuits 42 and 82 and possibly also further drive circuits can be interconnected on the one hand with the inverter control of the inverter and on the other hand with each other.
  • the series circuit 80 is formed of a total number n of semiconductor power switches, of which in the FIG. 5 to FIG. 7 For clarity, only the first semiconductor power switch 44 with its associated drive circuit 42 and the last semiconductor power switch 78 with its associated drive circuit 82 are shown.
  • the inverter controller 86 of the inverter receives a measured value of the intermediate circuit voltage Uzk from a voltage measuring device (not shown) of the inverter.
  • factors K1 (1) to K1 (n) for calculating maximum voltage values K1 (1) * Uzk to K1 (n) * Uzk for the collector-emitter voltages of the transistors the individual semiconductor circuit breaker determined.
  • the values form limits, as related to FIG. 3 already explained.
  • the maximum voltage value K1 (1) * Uzk corresponds to that in connection with FIG. 3 explained maximum voltage value K1 * Uzk.
  • factors K2 (1) to K2 (n) are also calculated for calculating voltage end values K2 (1) * Uzk to K2 (n) * Uzk, as already described in connection with FIG. 3 were explained.
  • the voltage end value K2 (1) * Uzk corresponds to that in connection with FIG. 3 voltage end value K2 * Uzk.
  • K1 (1) to K1 (n) and K2 (1) to K2 (n) are determined in such a way that the operation of the inverter always results in a uniform loading of the total n semiconductor power switches of the series circuit 80.
  • a signal generator 88 of the inverter controller 86 generates a switching signal S1 to Sn for each of the driving circuits 1 to n of the n semiconductor power switches of the series circuit 80.
  • the drive circuit 42 has the order number 1, the drive circuit 82 the order number n.
  • each of the switching signals S1 to Sn together with the associated parameter values for the switching parameters ie the voltage maximum values K1 (1) * Uzk to K1 (n) * Uzk and the voltage end values K2 (1) * Uzk to K2 (n) * Uzk are each transferred to the drive circuits for which they are intended.
  • FIG. 6 shown variant is based on the measurement of the current voltage values U1 and U1max, as performed by the drive circuit 42, a measurement of corresponding current voltage values Un and Un, max, as performed by the drive circuit 82, and corresponding measurements of other current voltage values by the remaining drive circuits of the half-bridge branch 74 (see FIG. 4 ).
  • the drive circuit 42 transmits the measured values via the signal line 70, the drive circuit 82 via a corresponding signal line 90, the remaining drive circuits via further, corresponding signal lines to an inverter controller 86 'of in FIG. 6 shown variant.
  • a signal generator 88' calculates from the values U1 to Un the actual intermediate circuit voltage Uzk and (in combination with the savings values U1max to Un, max) the resulting voltage maximum values K1 (1) * Uzk to K1 (n) * Uzk and the voltage end values K2 (1) * Uzk to K2 (n) * Uzk.
  • FIG. 7 a variant is shown in which the parameter values and the current voltage values between the individual Control circuits are exchanged.
  • the total of n drive circuits 42, 82 are interconnected in a master-slave configuration.
  • the drive circuit 82 is configured here as a master drive, ie it is the only drive circuit of the half-bridge arm 74, which is connected to the inverter control via its signal lines 84, 90.
  • the drive circuit 82 receives the switching signals S1 to Sn for all drive circuits 42, 82 of the half-bridge arm 74 and transmits the received switching signals (except for itself) to the other drive circuits 42 configured as slave drives, etc.
  • the communication links between The individual drive circuits via the signal lines 54, 70 and the remaining signal lines, not shown, can be designed as a ring bus connection.
  • the respective current voltage values U1, U1max etc. as well as further feedback signals are transmitted to the master drive (drive circuit 82) by the remaining drive circuits 42.
  • voltage maximum values K1 (1) * Uzk to K1 (n) * Uzk and / or voltage end values K2 (1) * Uzk to K2 (n) * Uzk and possibly also delay times dt1 to dtn from the master control , ie, the drive circuit 82, are calculated.
  • the required value for the intermediate circuit voltage Uzk can be determined in each case by adding up the individual voltage values U1 to Un in the master control. This variant corresponds to the one in FIG. 7 illustrated configuration. Then only the switching signals S1 to Sn must be transmitted via the signal line 84.
  • said parameter values can be determined and communicated together with the switching signals S1 to Sn to the master control.

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  • Inverter Devices (AREA)
  • Power Conversion In General (AREA)
  • Semiconductor Integrated Circuits (AREA)

Claims (9)

  1. Montage (74, 76), comprenant un circuit (80) série composé d'au moins deux commutateurs (44, 78) à semiconducteurs, dont chacun est relié, par son entrée (50) de commande, à un circuit (42, 82) de commande respectif, conçu pour commuter le commutateur (44, 78) à semiconducteurs en fonction d'un signal (S1, Sn) de commutation pouvant être donné à l'avance, dans lequel, pendant une opération de commutation, un comportement de commutation d'au moins l'un des circuits (42, 82) de commande est fixé par au moins un paramètre de commutation numérique, dont la valeur (K1*Uzk, K2*Uzk, K1(1)*Uzk, K2(1)*Uzk, K1(n)*Uzk, K2(n)*Uzk, dt1, dtn) peut être modifiée, de manière à pouvoir régler le comportement de commutation en fonctionnement,
    caractérisé en ce que
    le montage est conçu pour, afin d'interrompre un courant, mettre tous les commutateurs (44, 78) à semiconducteurs du circuit série dans un état bloqué et
    a) au moins l'un des circuits (42, 82) de commande a un dispositif (64) de contrôle de la tension, qui est conçu pour contrôler une tension (Ud, Uce, U1max, Un,max) chutant aux bornes du commutateur (44, 78) à semiconducteurs commandé par le circuit (42, 82) de commande et, si la tension (Ud, Uce, U1max, Un,max) est plus haute qu'une valeur (K1*Uzk, K1(1)*Uzk, K1(n)*Uzk) limite, abaisser la tension (Ud, Uce, U1max, Un,max) en agissant sur l'opération de commutation, la valeur (K1*Uzk, K1(1)*Uzk, K1(n)*Uzk) limite pouvant être réglée, comme paramètre de commutation du circuit (42, 82) de commande, pour une action de réglage de celui-ci, le circuit (42, 82) de commande étant conçu pour, par l'action de réglage, limiter à une valeur la plus haute la tension aux bornes du commutateur (44, 78) à semiconducteurs,
    et/ou
    b) pour au moins l'un des circuits (42, 82) de commande, on peut régler, comme paramètre de commutation, une valeur (K2*Uzk, K2(1)*Uzk, K2(n)*Uzk) finale de tension que doit avoir, à la fin d'une opération de commutation, une tension (Ud, Uce, U1, Un) chutant aux bornes d'un commutateur (44, 78) à semiconducteurs commandé par le circuit (42, 82) de commande, le circuit (42, 82) de commande étant conçu pour produire, pour le réglage de la valeur (K2*Uzk, K2(1)*Uzk, K2(n)*Uzk) finale de tension à la fin de l'opération de commutation, au moins une impulsion de symétrisation à l'entrée (50) de commande du commutateur (44, 78) à semiconducteurs.
  2. Montage (74, 76) suivant la revendication 1, dans lequel, pour au moins l'un des circuits (42, 82) de commande, un retard (dt1, dtn) de commutation peut être réglé comme paramètre de commutation et dans lequel ce circuit (42, 82) de commande est conçu pour faire commencer, après la réception du signal (S1, Sn) de commutation, une opération de commutation retardée du retard (dt1, dtn) de commutation réglé.
  3. Montage (74, 76) suivant l'une des revendications 1 ou 2, dans lequel au moins l'un des circuits (42, 82) de commande a un dispositif (64) de mesure de tension pour mesurer une tension (Ud, Uce) chutant aux bornes d'au moins l'un des commutateurs (44, 78) à semiconducteurs, ainsi qu'une sortie (68) de mesure, à laquelle une valeur (U1, U1max, Un, Un,max) de mesure peut être lue.
  4. Montage (74, 76) suivant l'une des revendications précédentes, comprenant un dispositif (88, 88') de réglage, qui est conçu pour déterminer une tension (Uzk) globale chutant aux bornes de tous les commutateurs (44, 78) à semiconducteurs et pour déterminer, à partir de la tension (Uzk) globale déterminée, pour chaque commutateur (44, 78) à semiconducteurs, une valeur de tension partielle et pour transmettre les valeurs de tension partielle déterminées comme valeurs (K1*Uzk, K2*Uzk, K1(1)*Uzk, K2(1)*Uzk, K1(n)*Uzk, K2(n)*Uzk ) de paramètre aux circuits (42, 82) de commande associés respectifs.
  5. Montage (74, 76) suivant l'une des revendications précédentes, comprenant un dispositif (88, 88') de réglage, qui est conçu pour déterminer, pour au moins l'un des circuits (42, 82) de commande, une valeur, qui provoque un décalage dans le temps entre les opérations de commutation des circuits (42, 82) de commande, et pour déterminer, à partir de la valeur déterminée, un retard dans le temps et pour transmettre le retard dans le temps déterminé comme valeur (dt1, dtn) de paramètre à l'un des circuits (42, 82) de commande.
  6. Montage (74, 76) suivant l'une des revendications précédentes, dans lequel au moins l'un des circuits (42, 82) de commande est conçu pour échanger avec un appareil (86, 86') extérieur un signal par une liaison (54, 70, 84, 90) par fibre optique.
  7. Montage (74, 76) suivant l'une des revendications précédentes, dans lequel au moins l'un des circuits (42, 82) de commande est conçu pour échanger avec un appareil (86, 86') extérieur un signal au moyen d'un protocole de transmission tolérant aux erreurs.
  8. Montage (74, 76) suivant l'une des revendications précédentes, dans lequel l'un des circuits (42, 82) de commande fonctionne comme commande (82) maître et au moins un autre comme commande (42) esclave, la commande (42) esclave échangeant, en passant par la commande (82) maître, des données avec un dispositif (88, 88') donnant un signal du montage (74, 76), qui produit des signaux (S1, Sn) de commutation pour les circuits de commande.
  9. Montage (74, 76) suivant l'une des revendications précédentes, dans lequel les circuits (42, 82) de commande échangent des données entre eux par un bus en anneau.
EP20120738085 2011-07-21 2012-07-13 Dispositif de commutation comprenant un commutateur statique et un circuit de commande associé Active EP2721735B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE201110079545 DE102011079545A1 (de) 2011-07-21 2011-07-21 Schaltungsanordnung mit einem Halbleiterschalter und einer zugehörigen Ansteuerschaltung
PCT/EP2012/063824 WO2013010949A1 (fr) 2011-07-21 2012-07-13 Dispositif de commutation comprenant un commutateur statique et un circuit de commande associé

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EP2721735A1 EP2721735A1 (fr) 2014-04-23
EP2721735B1 true EP2721735B1 (fr) 2015-05-20

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EP2762347A1 (fr) 2013-01-31 2014-08-06 Siemens Aktiengesellschaft Convertisseur haute fréquence modulaire et procédé de fonctionnement de celui-ci
JP6329944B2 (ja) 2013-05-10 2018-05-23 株式会社日立製作所 絶縁ゲート型半導体素子の制御装置およびそれを用いた電力変換装置
DE102013216672A1 (de) * 2013-08-22 2015-02-26 Siemens Aktiengesellschaft Elektronischer Schalter mit einem IGBT

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DE4335857A1 (de) * 1993-10-21 1995-04-27 Abb Management Ag Stromrichterschaltungsanordnung und Verfahren zur Ansteuerung derselben
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US5712587A (en) * 1996-04-08 1998-01-27 Electric Power Research Institute, Inc. Apparatus and method for simultaneously deactivating series-connected switching devices
DE10156963A1 (de) * 2001-11-20 2003-06-05 Fritz Frey Schaltungsanordnung zum zuverlässigen Schalten von Stromkreisen
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GB0617990D0 (en) 2006-09-13 2006-10-18 Palmer Patrick R Control of power semiconductor devices
EP2234125B1 (fr) * 2009-03-27 2014-01-08 Honda Motor Co., Ltd. Dispositif de commande à solénoïde et dispositif de support d'isolation de vibration active équipé avec celui-ci
DE102010030078A1 (de) * 2010-06-15 2011-12-15 Siemens Aktiengesellschaft Verfahren zum Sperren eines Stromrichters mit verteilten Energiespeichern
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RU2586870C2 (ru) 2016-06-10
EP2721735A1 (fr) 2014-04-23
CN103891143A (zh) 2014-06-25
DE102011079545A1 (de) 2013-01-24
RU2014106411A (ru) 2015-08-27
CN103891143B (zh) 2016-10-26
WO2013010949A1 (fr) 2013-01-24
US20140145520A1 (en) 2014-05-29

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