Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
  • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
  • H03M7/3059—Digital compression and data reduction techniques where the original information is represented by a subset or similar information, e.g. lossy compression
  • H03M7/3062—Compressive sampling or sensing

Definitions

• CS Compressive sampling
• a host of functions including antenna array processing, multipath estimation, and interference rejection, are severely limited by the need to operate on large numbers of samples at high speed.
• ADC analog/digital conversion
• ADC analog/digital conversion
• Embodiments of the present invention provide for dramatically improved interference resistance in advanced communications applications, where the frequency range can exceed 1 GHz.
• Such embodiments may be implemented using wideband technology to provide a wideband compressive sampling architecture that is capable of superior interference rejection through RF front end cancellation.
• Embodiments of the invention include a circuit for sampling a signal.
• the circuit may include an attenuator, a mixer, an integrator, and a sample-and-hold circuit.
• the attenuator may be configured to receive a chipping sequence and an attenuation value, the attenuator attenuating the chipping sequence based on the attenuation value to output a corresponding mixing sequence.
• the mixer receives a data signal, modulates the data signal according to the mixing sequence, and generates a modulated data signal.
• the integrator receives the modulated data signal and generates a filtered modulated data signal.
• the sample-and-hold circuit sample the filtered modulated data signal to provided a sampled data signal.
• the attenuator value may be generated to attenuate the chipping sequence such that the mixing sequence enables the mixer to cancel interference in the data signal.
• the attenuator value may generated based on information relating to one or more of a signal of interest contained within the data signal, anticipated noise within the data signal, and anticipated interference within the data signal.
• the chipping sequence is a random sequence or a predefined pattern.
• a radio-frequency (RF) front-end circuit comprising a pre-sampling front-end circuit and a compressive sampling circuit as described above.
• the pre-sampling front-end circuit may be configured to receive an analog RF signal from an antenna and output a data signal.
• the front-end may also include a digital processor configured to process the sampled data signal.
• the digital processor may be further configured to perform one or more of signal energy detection, filtering the signal of interest, classification, and demodulation.
• the digital processor may operate under parameters that include the sampled data signal being absent of interference as a result of interference cancellation by the compressive sampling circuit.
• FIG. 1 illustrates compressive sensing measurement
• FIG. 2 illustrates RMPI sampling.
• FIG. 3 is an operational block diagram of an example embodiment of a compressive sampling apparatus featuring interference-resistant compressive sampling.
• FIG. 4 illustrates example OIC formulation matrices.
• FIG. 5 illustrates an example interference resistant wideband compressive sampler.
• FIG. 6 illustrates an embodiment in which an interference resistant wideband compressive sampler interfaces a back-end field-programmable gate array (FPGA) and digital signal processor (DSP).
• FPGA field-programmable gate array
• DSP digital signal processor
• this corresponds to the physical process of sampling (measurement basis) a Fourier (representation basis) transformed signal.
• compressive sampling is performed by taking M measurements of a length-N signal x (represented as ⁇ , where s is the sparsity vector and contains K non-zero entries) to form a measurement vector y.
• the signal x can then be reconstructed from y using an appropriate algorithm.
• interference is canceled much earlier in the processing chain than these prior attempts - by placing the interference cancellation in the RF front end of the CS receiver.
• A/I conversion architecture There are several approaches that can be taken in the design of the receiver's Analog to Information (A/I) conversion architecture. Candes and Wakin [1] present two such architectures. Their Non-Uniform Sampler digitizes the signal at randomly sampled time points. This can be used for compressive representation of signals with sparse frequency spectra (spikes and sines are incoherent). A second architecture is Random Modulation Preintegration (RMPI).
• RMPI Random Modulation Preintegration
• Fig. 2 is a block diagram illustrating RMPI sampling.
• the signal is multiplied by a random sequence of ⁇ l s, integrated over a time window, then sampled at the end of the time interval.
• a random antipodal sequence is a universal measurement process, and therefore it is incoherent with any time-frequency basis (such as the Gabor dictionary).
• the output measurements can then be used to reconstruct the original signal using an appropriate algorithm.
• RMPI is used for A/I conversion in [2].
• Fig. 3 is an operational block diagram of an example embodiment of a compressive sampling apparatus 300.
• the apparatus 300 includes an RF analog front end 302 and digital signal processor 304.
• the RF analog front end 302 includes a pre-sampling circuit 306 and an interference-resistant compressive sampling circuit 308.
• the sampled signal may then be forwarded to digital signal processor 304, which may perform signal reconstruction 310, signal energy detection 312, filtering of the signal of interest 314, classification 316, and demodulation 318.
• Embodiments of the wideband compressive sampler provide a measurement set that can deliver superior interference performance to previous CS techniques. By cancelling interference in the RF front end circuitry, it is unnecessary to rely on back end DSPs to perform the function, as is done in [2,3,4]. By this point, strong narrowband interference may have degraded the measurements of the collected samples to such a degree that it may not be possible to recover the original signal in practice. Embodiments of the present invention avoid this problem by introducing a new take on standard RMPI A/I conversion.
• a challenge lies in designing sequences that are resistant to interference using a priori knowledge of its geometry and/or statistics.
• using known basis support to create a projection matrix that nulls interference, as in [2,3] is subject to SNR difficulties when the target signal and interference signals are not sufficiently orthogonal, and we will initially focus on an MMSE-based approach as described in [4].
• the procedure is comparable to [2], in that the authors also use a linear operator to map samples of x to a set of measurements y.
• embodiments of the present invention alter it using a priori covariance knowledge to create the operator PMMSE-
• the measurement basis can be a set of random antipodal sequences, now made interference resistant by applying the interference cancellation operator.
• Fig. 4 illustrates example formulation matrices to create the PMMSE operator.
• Modulation of the incoming data signal is performed with these modified sequences.
• the operator PMMSE will be termed ⁇ to designate it as an interference cancelling measurement basis. Interference cancellation is therefore done in the RF front end as opposed to the back end, as in [2].
• a second challenge is the design of a Nyquist rate modulator using relatively complex sequences. While ⁇ l s are relatively simple to implement in hardware, generating high-precision values at high rates may to require a sophisticated attenuator and high speed serial interface. See [4] for a detailed description of formulation matrix construction.
• Fig. 5 illustrates a wideband compressive sampler 500 in an example embodiment, which implements a mixer 502, integrator 504, and low-rate sample- and-hold circuit 506 consistent with RMPI.
• a binary, antipodal chipping sequence 508 is attenuated by an attenuator 510 such that the chipping sequence becomes a row sub-matrix of the measurement operator ⁇ > Attenuation values 512 corresponding to the ⁇ : rows are generated in a FPGA and passed to the attenuator through a high rate interface.
• the binary, antipodal chipping sequence is attenuated by an amount commensurate with these values.
• the chipping sequence is pseudo-random due to the incorporation of deterministic covariance information.
• the chipping sequence may be a predefined pattern or other non-random sequence.
• the length-N signal x is modulated with the length-Z chipping sequence then integrated over a window LT, where T is the Nyquist sample time.
• the signal is then sampled-and-held and passed to a quantizer, such as a sigma-delta ( ⁇ ) converter.
• the reconstructed signal x is an interference and noise free digital version of the RF signal x(t).
• the number of required measurements is M> cKiog(N/K) for high probability reconstruction of a ⁇ -sparse signal [4].
• greedy algorithms such as orthogonal matching pursuit will be employed.
• the mixer, integrator and low-rate sample-and-hold circuits can be made in accordance with teachings of International Patent
• Performance of the compressive sampler shown in Fig. 5 may be measured to determine the efficacy of the interference cancellation.
• a key performance metric which can be measured following compressive measurement and before quantization, is SNR vs. Kj/Ks for a given SIR, where SNR is the signal to noise ratio, Ki/ s is the sparsity ratio of the interference to the signal of interest, and SIR is the signal to interference ratio.
• a goal value may be >72 dB for all Kj/Ks over the expected SIR range. Due to the need to satisfy noise figure and dynamic range requirements, the number of measurements may be greater than the minimum required for reconstruction, and the restricted isometry property [5] must be satisfied to sufficient degree to ensure desired performance levels.
• a noise figure of 12 dB would be in line with other compressive sensing acquisition receivers, while a 72 dB dynamic range will present enough SNR to achieve 12-bit resolution from the analog to digital converter.
• An appropriate algorithm may be selected to reconstruct the signal.
• One class comprises algorithms that minimize the LI -norm.
• One example is the Lasso algorithm.
• the other class comprises greedy algorithms. These form a fast, approximate representation by taking successively highest correlation values (such as through an inner product) of the measured signal with a dictionary set.
• An example is matching pursuit, or orthogonal matching pursuit.
• Fig. 6 shows an embodiment in which an interference resistant wideband compressive sampler interfaces a back-end FPGA and DSP, where the signal reconstruction algorithms and other digital processing as shown in Fig. 3 are performed.
• the interference resistant wideband compressive sampler's sample-and-hold circuit interfaces an ADC (such as a delta-sigma converter), which interfaces the FPGA/DSP back-end.
• ADC such as a delta-sigma converter
• Signal reconstruction may be performed using a Programmable System on Chip (PSoC) such as Cypress Semiconductor's CY8C55 as shown in Fig. 6.
• Successive digital processing tasks such as energy detection, filtering, classification, and demodulation, as referenced earlier, may be performed using FPGAs and/or DSPs.
• the digital processor may omit interference cancellation as described above with reference to Fig. 3.
• the digital processor may operate under parameters that include the sampled data signal input being absent of interference as a result of interference cancellation by the compressive sampling circuit.
• the digital processor may implement a redundant or supplemental interference cancellation to further enhance performance.

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• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Noise Elimination (AREA)
• Compression, Expansion, Code Conversion, And Decoders (AREA)

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• 2012
  • 2012-06-08 US US13/491,892 patent/US8750438B2/en not_active Expired - Fee Related
  • 2012-06-08 EP EP12730298.2A patent/EP2719085A1/en not_active Withdrawn
  • 2012-06-08 WO PCT/US2012/041587 patent/WO2012170840A1/en active Application Filing
  • 2012-06-08 JP JP2014514888A patent/JP5908070B2/ja not_active Expired - Fee Related
  • 2012-06-08 KR KR1020147000391A patent/KR20140065386A/ko not_active Application Discontinuation
  • 2012-06-08 CN CN201280027560.5A patent/CN103765780A/zh active Pending

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