EP2713386B1

EP2713386B1 - Process for manufacturing semiconductor devices, such as super-barrier sbr rectifiers

Info

Publication number: EP2713386B1
Application number: EP13186557.8A
Authority: EP
Inventors: Francesco Lizio
Original assignee: STMicroelectronics SRL
Current assignee: STMicroelectronics SRL
Priority date: 2012-09-27
Filing date: 2013-09-27
Publication date: 2016-06-29
Anticipated expiration: 2033-09-27
Also published as: CN103700587A; US9018048B2; US20140087539A1; CN109037057A; CN103700587B; CN109037057B; EP2713386A1

Description

The present invention relates to a process for manufacturing semiconductor devices, such as super-barrier rectifiers.
Power semiconductor rectifiers are known for example from the document US2003/0222290 .
As is known, the recent family of SBRs, namely, adjustable field-effect rectifiers (AFERs, see for example US 2009/0078962 ) envisages the use of regions typical of MOSFET transistors and the addition of a so-called "pocket" or "probe" region so as to reduce the negative resistance and at the same time have a high recovery speed, even at high frequency, and in this way reduce the problems of electromagnetic interference.
With this device, it is important for the distance between the channel and the "pocket" or "probe" to be as small as possible, but for the two regions not to overlap. Consequently, the channel implant has lateral dimensions and corresponding tolerances that are very critical.
Since in this technology the channel is lithographically defined, the performances of the device are limited by the very accuracy of the lithographic process.
By virtue of the probe implantation being made subsequently and in regions complementary to the channel regions, alignment errors occurring in the various masking levels add together, jeopardizing the final result or, at the very least, reducing the performances of the finished device.
On the other hand, the current trend to miniaturization requires, at least in certain applications, an increase in the circuit density so that it becomes important to reduce both the spacing and the superposition between the adjacent regions.
For a better understanding of the problem referred to above, reference may be made to Figures 1-10, which show an AFER diode developed by the present applicant.
Figure 1 shows a cell 2 belonging to an AFER diode 1, generally comprising a plurality of cells 2, adjacent to each other and formed by strip-like shaped regions extending perpendicularly to the drawing plane. The AFER diode 1 is formed in a substrate 3 of semiconductor material of an N- type, which forms a first drain region. A second drain region of an N+ type (not shown) may extend underneath the substrate 3, and a drain metallization (not shown either) may extend underneath the second drain region.
Each cell 2 comprises a well region 4, of a P type; source regions 16, of an N+ type; and a probe region 5, of an N type, facing a surface 6 of the substrate 3.
A gate oxide layer 11 extends over the surface 6, and a gate region 12 extends over the gate oxide layer 11. The gate oxide layer 11 and the gate region 12 have, in each cell 2, an opening 13, and a portion 14a of a conductive (metal) region 14 arranged on top of the gate region 12 extends in the opening 13. The portion 14a of the metal region 14 extends also partially within the substrate 3 and is here adjacent to the source regions 16 and to the well region 4.
In detail, the source regions 16 extend on the two sides of, and directly adjacent to, the portion 14a of the metal region 14. The well region 4 comprises a deep portion 9, which is more doped, extending underneath the portion 14a of the metal region 14, and two surface portions (forming channel regions 10), which face the surface 6 and are each arranged on a side of a respective source region 16. The channel regions 10 are each adjacent to a respective probe region 5 (one belonging to the cell 2 itself, the other to the adjacent cell 2). The probe region 5 is deeper than the channel regions 10, but is arranged closer to the surface than the deep portion 9 of the well region 4.
In practice, the portion 14a of the metal region 14 directly contacts and electrically connects together the gate region 12, the source regions 16, and the deep portion 9 of the well region 4. A silicide layer 15, for example of titanium, may extend underneath the metal region 14, over the gate region 12 and on the sides of the opening 13.
The AFER diode 1 is obtained as shown in Figures 2-9.
Initially (Figure 2), the active area is prepared: the gate oxide layer 11 and the gate region 12, here of polysilicon, are formed on the substrate 3.
Then (Figure 3), a poly mask 20, of resist, is formed on the gate region 12 and has a window 21 where the opening 13 is to be formed. Using the poly mask 20, the exposed portion of the gate region 12 is removed to obtain the window 13, and, in the substrate 3, an implantation of dopant species of a P type, for example a boron implantation, is carried out so as to form a pre-well region 17.
Next (Figure 4), using the same poly mask 20, a tilted implantation is carried out with dopant species of an N++ type, for example As, so as to form an enriched layer 22, which, thanks to the tilted implantation, extends, with its peripheral portions, underneath the gate region 12.
Then (Figure 5), the gate oxide layer 11 and the substrate 3 are etched and removed in the area underneath the window 21 (and thus the opening 13) to form a microtrench 18. In this way, also part of the enriched layer 22 is removed, but underneath the gate region 11, the peripheral portions thereof remain, to form the source regions 16.
Next (Figure 6, an implantation of dopant species of a P type (e.g., BF₂) is carried out inside the pre-well region 17, to form a thin layer 23 of a P type, more doped than the pre-well region 17 and not shown for simplicity in the subsequent figures.
After removal of the poly mask 20 (Figure 7), a channel mask 24 of resist is formed. The channel mask 24 has a window 25 that is ideally centred with respect to the window 21 of the poly mask 20 (and thus to the opening 13), but is wider, so as to expose, in addition to the microtrench 18 and the opening 13, also the top surface of the two portions of the gate region 12, laterally to the opening 13. Then, dopant species of a P type are implanted to provide the channel regions 10 in the substrate 3, laterally to the opening 13, and an enriched area 26 within the pre-well region 17. However, since the channel implant has a lower dose than the well implant (typically the difference is of two orders of magnitude, 10¹² for the channel implant and 10¹⁴ for the well implant), the channel implant does not modify the concentration of the pre-well region 17. Consequently, the enriched area 26 is no longer shown in the subsequent figures. Ideally, the width of the channel regions 10 should be the same; however, on account of the inevitable misalignments between the poly mask 20 and the channel mask 24, in practice they have a different length.
After removing the channel mask 24, a probe mask 27 is formed (Figure 8). Probe mask 27 is ideally complementary to the channel mask 24 and covers the gate region 11 on top of the pre-well region 17 and the channel regions 10. Dopant species of an N type are then implanted to form the probe regions 5 laterally to each channel region 10. Ideally, the probe regions 5 is immediately adjacent to the channel regions 10, even though they may extend to a greater depth, but the misalignment between the channel mask 24 and the probe mask 27 may cause a spacing between one channel region 10 and the adjacent probe region 5, on one side, and an overlapping between the two regions 10, 5, on the opposite side.
After removing the probe mask 27, the silicide layer 15 (Figure 9) and then the metal region 14 (Figure 10) are formed.
After the thermal steps for activating the dopant species, the structure of Figure 1 is obtained, wherein the deep portion 9 of the well region 4 has a non-uniform doping, and the well region 4 embeds the channel regions 10.
In AFER diodes of this type, the lateral dimensions are very small and critical so that alignment errors referred to above may considerably affect the operation of the diode and require compromises for relaxing design rules and tolerances.
For example, in devices produced by the present applicant, the probe region 5 and the opening 13 may have a width of approximately 350 nm, and the distance between the opening 13 and the adjacent side edge of the probe region 5 may be approximately 250 nm, so as to ensure a channel length of approximately 100 nm, with a lateral dimension of the source region 16 of approximately 150 nm. The length of channel (width of the channel region 10, between the source region 16 and the probe region 5) may be 100 nm.
As indicated above, with the described manufacturing technique, criticality derives from the fact that the channel implant (using the channel mask 24) and the probe implant (using the probe mask 27) are aligned, with two different photo-techniques, to the contact previously opened in the gate region 12 (opening 13 obtained using poly mask 20), on the basis of the precision degree required of the channel and probe photo-techniques.
To achieve this precision, various solutions have been suggested, such as: use of exposure systems for VLSI technologies, with maximum misalignments within 20 nm; execution of dimensional checks in all the steps; use of feedback systems for automatic compensation of the process drift; and use of golden tools.
However, these actions have an impact on the production flow in terms of costs and cycle times.
The aim of the present invention is to provide a process intended to overcome the drawbacks of the prior art.
According to the present invention, a process for manufacturing semiconductor devices is provided, as defined in claim 1.
In practice, a fully self-aligned structure is provided, which thus does not require particularly accurate photo-techniques.
In fact, the three photo-techniques (corresponding to the poly mask 20, the channel mask 24, and the probe mask 27), are replaced by a single photo-technique, namely, the probe one. The subsequent processes enable opening of complementary and self-aligned regions for the channel implant and opening of the self-aligned contact on polysilicon.
For a better understanding of the present invention preferred embodiments thereof are now described, purely by way of non-limiting example, with reference to the attached drawings, wherein:

Figure 1 shows, in cross-section, an AFER diode made by the present applicant;
Figures 2-10 show cross-sections of the AFER diode of Figure 1, in successive manufacturing steps;
Figures 11-21 show cross-sections of an embodiment of the present AFER diode, in successive manufacturing steps;
Figures 22-28 show cross-sections of a different embodiment of the present AFER diode, in successive manufacturing steps; and
Figures 29 and 30 show cross-sections of another different embodiment of the present AFER diode, in an intermediate manufacturing step.

The present process for manufacturing an AFER diode is based upon: forming a first mask on a gate layer; implanting a probe region in the substrate using the first mask; forming a second mask laterally and complementary to the first mask, at least in a projection in a plane parallel to the surface of the body; implanting a channel region, in a complementary position to the probe region, using the second mask; forming spacers on the sides of the second mask; and removing portions of the semiconductor layer to obtain a gate region.
In particular, the first mask has a first window that is filled with filling material to form a complementary mask; after providing the complementary mask, the first mask is removed and the second mask is formed so as to comprise the complementary mask or be arranged thereon, congruent therewith.
Figures 11-21 show an embodiment of the present process.
First, initial steps are carried out for forming edge regions (not shown), in a per se known manner. Then (Figure 11), the active area is prepared: on a substrate 30, also here of an N type, a gate oxide layer 31, a gate layer 32, and an insulating layer 33, e.g. an oxide layer, such as a TEOS (tetraethyl orthosilicate) layer, are formed.
Then (Figure 12), a resist probe mask 34 is formed, which has windows 35 where the probe regions are to be formed. Then, a probe implantation is carried out, here of dopant species of an N type, for example arsenic. The implantation is performed according to parameters, in particular energy, studied so as to enable the dopant ion species to traverse the insulating layer 33, the gate layer 32, and the gate oxide layer 31, and causes probe regions 37 to be formed (Figure 13).
Next (Figure 13), the windows 35 of the probe mask 34 are filled with a filling material (filler regions 39) of material compatible with, and having a high selectivity with respect to, the photoresist of the probe mask 34. For example, the filler regions 39 may be spin-on glass, polyimide, organic material, screen-printing paste, and the like. A complementary mask 58 is thus obtained, on the insulating layer 33, formed by filler strips 39 and complementary to the probe mask 34.
Next (Figure 14), the probe mask 34 is removed.
Then, using the complementary mask 58, the insulating layer 33 is etched, for example by a dry etch, leaving insulating portions 33a. The filler regions 39 and the insulating portions 33a form a channel mask 38. Next, a channel P type implantation is performed, for example a boron implantation (Figure 15). In this way, underneath the areas where the probe mask 34 was previously present, channel regions 40 are formed, which are arranged on the sides of the probe regions 37.
Next, the filler regions 39 are removed (complementary mask 58), to obtain the structure of Figure 16, where the probe regions 37 and the channel regions 40 are arranged in an alternating way in the substrate 30, and the insulating regions 33a extend on the surface 41 of the substrate 30, exactly overlying the probe regions 37 and staggered with respect to the channel regions 40.
As an alternative to the above, it is possible first to remove the complementary mask 58 and then to carry out the channel implantation.
Next (Figure 17), a spacing layer is deposited, for example an oxide layer such as TEOS, which coats the insulating regions 33a at the top and laterally; followed by an anisotropic etch so as to form spacers 44 on the lateral surfaces of the insulating regions 33a, in a known manner. The insulating regions 33a and the spacers 44 thus form a contact mask 47 having windows 43 where openings are to be formed for the contacts. The contact mask 47 is thus self-aligned to the probe and channel implants and is formed by strips extending perpendicular to the drawing plane and centred with respect to the probe regions 37.
Using the contact mask 47 (Figure 18), the gate layer 32 is first etched (to form gate regions 32a) and then a well implantation of a P type is performed. Well regions 48 are thus formed in the substrate 30, partially overlying the channel regions 40.
Then (Figure 19), using the same contact mask 47, a tilted implant with dopant species of an N+ type, for example As, is carried out so as to form enriched regions 49 that extend each, with their own peripheral portions, underneath gate regions 32a.
Next (Figure 20), the gate oxide layer 31 and the substrate 30 are etched and removed underneath the windows of the contact mask 47 to form microtrenches 51, arranged aligned to, and as a continuation of, the contact openings 46. In this way, also part of the enriched regions 49 is removed to form, underneath the gate regions 32a, source regions 50 of an N+ type.
After removal of the contact mask 47, for example by wet etches (Figure 21), a silicide layer 53 is deposited, similar to the silicide layer 15 of Figure 1, as well as a contact region 54, for example of metal and similar to the metal region 14 of Figure 1. Alternatively, the contact mask 47 may be kept, even though its removal enables a larger surface of the gate regions 32a to be obtained to may be contacted by the contact region 54.
After thermal activation steps of the dopant species, a structure similar to that of Figure 1 is obtained.
In this way, the photo-technique used for forming the probe mask 34 also determines the shape and arrangement of the subsequent channel mask 38 and contact mask 47, which are thus self-aligned to the probe mask 34, thereby eliminating any criticality existing with the prior art and reducing the costs, thanks to the reduction of the photo-techniques for forming the photoresist masks in the prior-art process.
Figures 22-27 show a different embodiment of the present process, wherein same parts of the process of Figures 11-21 have been designated by the same reference numbers.
Initially, the same steps described with reference to Figure 11 are carried out, including: forming edge regions (not shown); and forming the gate oxide layer 31, the gate layer 32, and the insulating layer 33. Then, similarly to what shown in Figure 12, the photo-technique is used to form the probe mask 34, but in this case, prior to performing the probe implantation, the insulating layer 33 is etched, e.g. by dry etch, leaving the insulating portions 33a. The probe implant (Figure 22) is then carried out, here only through the gate layer 32 (and the thin gate oxide layer 31) so that the implantation energy is less than the energy necessary in the step of Figure 12, and leads to formation of the probe regions 37 (Figure 23).
Next (Figure 23), the probe mask 34 is removed, and a filling layer is deposited and fills the openings or windows 35 between the insulating portions 33a. The material of the filling layer has high selectivity in regard to the material of the insulating portions 33a. For example, a nitride layer is deposited, the thickness whereof is such as to completely fill the cavities, and thus depends, i.a., upon the width of the openings 35. After a planarization step, for example via etch-back or CMP (Chemical-Mechanical Polishing), which leads to the elimination of the excess part of the nitride layer above the insulating portions 33a, nitride regions 60 are obtained.
Next (Figure 24), the insulating portions 33a are removed via wet etching. Since the selectivity of the etch may be very high, virtually infinite, the nitride regions 60 are not affected by this etch and define a channel mask 61 complementary to the probe mask 34. Then, using the channel mask 61, the channel implant of a P type is made, for example a boron implant, to form the channel regions 40, also here arranged alongside and alternate with the probe regions 37 (Figure 25).
The spacing layer is then deposited, here designated by 63 (Figure 25). The spacing layer 63 is anisotropically etched and leads to formation of spacers 64 on the lateral surfaces of the nitride regions 60 (Figure 26). The nitride regions 60 and the spacers 64 thus form a contact mask 67, used for carrying out the well implant, of a P type. Well regions 48 are thus formed in the substrate 30, also here partly overlying the channel regions 40.
Then (Figure 27), using the same contact mask 67, an N+ type tilted implantation is carried out, for forming the enriched regions 49.
Next (Figure 28), the gate layer 32, the gate region 32, the gate oxide layer 31, and the substrate 30 are etched and removed where exposed by the contact mask 47, to form N+ type gate regions 32a and source regions 50.
After removing the contact mask 67, the silicide layer 53 and the contact region 54 are deposited to obtain the structure of Figure 28.
Also in this case, after the thermal steps for activating the dopant species, a structure is obtained similar to that of Figure 1.
In practice, in this case, the probe mask 61 forms the mask complementary to the probe mask 34 and is arranged laterally and complementarily to the probe mask 34, in a projection on a plane parallel to the surface of the body.
According to a different embodiment, the complementary mask may be obtained using a negative photoresist.
Also in this case, after the initial steps of Figures 11-12, including forming the gate oxide layer 31, the gate layer 32, the insulating layer 33, the probe mask 34, and the probe regions 37, the windows 35 of the probe mask 34 are filled with the filling material, here designated by 70 (Figure 29), by deposition and etch-back until the resist of the probe mask 34 is exposed. In this case, the filling material 70 is resist of a complementary type to the probe mask 34. Typically, if the probe mask 34 is of positive resist, the filling material 70 is of negative resist, sensitive to the same wavelength as the positive resist.
Thus, the structure is completely (blank) photoexposed, without the use of any coating or mask, thus causing development both of the positive-resist regions 34 (previously covered, during formation of the probe mask 34 and thus not previously developed, and now rendered soluble by being developed) and of the negative-resist regions 70 (which undergo cross-linking and thus become insoluble during development), as indicated schematically in the figure by the arrow 71.
Due to the different properties of the positive and negative resist, the subsequent development leaves the regions formed by the filling material 70 unaltered and causes removal of the probe mask 34, to obtain the structure of Figure 30, which is structurally the same as Figure 14, wherein the filler regions 39 are replaced by the negative-resist regions 70 and the complementary mask 58 is replaced by the complementary mask 72.
The process then proceeds in the way described with reference to Figures 15-21, including: etching the insulating layer 33, channel implanting, and forming the channel regions 37; removing the channel mask (including the portions 70); forming the spacers 44; etching the gate layer 32, with formation of the gate regions 32a; well implanting, with formation of the well regions 48; source tilted implanting, with formation of the enriched regions 49; etching the substrate 30, with formation of the microtrenches 51 and the source regions 50; and forming the contact region 54.
It should be noted that in all the embodiments, the exact shape and size of the various regions are represented only schematically and may vary with respect to what shown. For example, even though the channel regions 40 and the probe regions 37 are shown with the same depth, in general their depth is different, similarly to what shown in Figure 1, where the probe region 5 is deeper than the source region 16.
Moreover, in a per se known manner, the depth of the source regions 50, after implantation, may vary with respect to what is illustrated, but, with the subsequent thermal budgets for dopant activation, the deep part of the P-well region 48 diffuses isotropically, joining without interruptions with the channel region. The manufacturing process described above thus solves the problem of the required precision and of the associated costs for alignment of the probe, channel, and source regions, since the corresponding masks are obtained complementarily to and/or deriving from the first mask (here, the channel mask).
The process is particularly advantageous, not only because it does not involve the use of the costly solutions that are currently necessary, but also on account of its simplicity and reduction in the number of photo-technique steps. In particular, the described process becomes particularly important to enable scaling of the technology to obtain cells of smaller dimensions.
Finally, it is clear that modifications and variations may be made to the process described and illustrated herein, without thereby departing from the scope of the present invention, as defined in the attached claims.
For example, the same approach may be used for manufacturing semiconductor devices based upon the use of gallium nitride, in particular forming the gate region. In fact, the process enables evaporation of the metal on the gate region without performing etching thereof, thus preventing damage to the GaN surface because of the plasma.

Claims

A process for manufacturing a semiconductor device, comprising the steps of:
providing a body (30) of semiconductor material having a surface;

forming a semiconductor layer (32) on top of the body;

forming a first mask (34; 34, 33a) on top of the semiconductor layer;

introducing first dopant species into the body using the first mask to form a first conductive region (37) in the body;

forming a second mask (38; 61) laterally and complementarily to the first mask, at least in a projection in a plane parallel to the surface of the body;

introducing second dopant species into the body (30) using the second mask to form a second conductive region (40) in the body, in an adjacent and complementary position to the first conductive region (37);
the process characterized by
forming spacers on the sides of the second mask region (38; 61), to form a third mask (47; 67) aligned to the second mask; and
by using the third mask, removing portions of the semiconductor layer (32) to obtain a gate region (32a).
The process according to claim 1, wherein:
the first mask (34; 33a, 34) comprises a window (35);

after introducing first dopant species, at least partially filling the window (35) with filling material (39; 60; 70) to form a complementary mask (58; 61) arranged offset and complementarily with respect to at least one portion (34; 33a) of the first mask; the second mask (38; 61) including at least partially the complementary mask (58; 61) or being congruent with respect to the complementary mask; and

after filling the window (35) at least partially, the first mask (33a, 34; 34) is removed.
The process according to claim 2, wherein the first mask is a probe mask (34); the first conductive region is a probe region (37); the second mask is a channel mask (38; 61); and the second conductive region is a channel region (40).
The process according to claim 2 or 3, wherein the semiconductor device comprises an AFER diode (1), the process comprising, after removing portions of the semiconductor layer (32), and using the third mask (47; 67):
introducing third dopant species into the body to form a well region (48);

introducing fourth dopant species into the channel region (40) in a tilted way to form a source region (50);

removing a portion of the body (30) to form a microtrench (51); and

depositing a conductive contacting layer (53, 54) filling the microtrench and extending at least on one side of the gate region (32a) and in electrical contact with the gate region (32a), the source region (50), and the well region (48).
The process according to claim 4, wherein the body (30), the first conductive region (37), and the source region (50) have a first conductivity type, and the well region (48) and the second conductive region (40) have a second conductivity type.
The process according to claim 4 or 5, wherein the semiconductor layer (32) is of polysilicon, and the conductive contacting layer (53) is of metal.
The process according to any one of claims 2-6, wherein, prior to providing a first mask (34), on the semiconductor layer (32), a masking layer (33) is formed; and forming a second mask (38) comprises removing portions of the masking layer using the complementary mask (58; 72).
The process according to claim 7, wherein introducing first dopant species and filling the first window (35) are performed prior to removing portions of the masking layer (33); the complementary mask (58; 72) extends over the masking layer (33), laterally with respect to the first mask (34); and introducing first dopant species comprises implanting the first dopant species through the masking layer.
The process according to claim 8, wherein, prior to forming spacers (44), the complementary mask (39) is removed.
The process according to claim 8 or 9, wherein removing the complementary mask (58; 72) is carried out before or after introducing second dopant species.
The process according to any one of claims 8-10, wherein the first mask (34) is of first-type photoresist, and the filling material (70) is a second-type photoresist.
The process according to claim 11, wherein the first-type photoresist is positive, and the filling material (70) is negative photoresist and, prior to removing the first mask (34), the structure is photoexposed blank.
The process according to any one of claims 2-6, wherein providing a first mask (33a, 34) comprises forming, on the semiconductor layer (32), a masking layer (33) and first mask regions (34), and removing portions of the masking layer not covered by the first mask regions (34); and forming a second mask (61) comprises removing the first mask regions (34), and, after at least partially filling the window (35) with filling material, removing remaining portions (33a) of the masking layer.
The process according to any one of claims 8-10 or 13, wherein the masking layer (33) is of insulating material.