CN101556921B - Semiconductor device and making method thereof - Google Patents
Semiconductor device and making method thereof Download PDFInfo
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- CN101556921B CN101556921B CN2008100924324A CN200810092432A CN101556921B CN 101556921 B CN101556921 B CN 101556921B CN 2008100924324 A CN2008100924324 A CN 2008100924324A CN 200810092432 A CN200810092432 A CN 200810092432A CN 101556921 B CN101556921 B CN 101556921B
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Abstract
The present invention provides a semiconductor device and a making method thereof. The semiconductor device comprises a semiconductor substrate, a plurality of nodal areas, a grid electrode, a source electrode and a drain electrode, wherein the semiconductor substrate comprises a first type pitfall and a second type pitfall; the nodal areas are positioned between the first type pitfall and the second type pitfall, and every nodal area is positioned between the first type pitfall and the second type pitfall and is abutted against the first type pitfall and the second type pitfall; the grid electrode is arranged on the semiconductor substrate and is positioned on at least two of a plurality of nodal areas; and the source electrode and the drain electrode are arranged in the semiconductor substrates at both sides of the grid electrode. Compared with a traditional semiconductor element, the semiconductor element made by the embodiment can approximately enhance the operation voltage range of the grid electrode by more than 30 percent. Moreover, because the making method of the semiconductor element of the embodiment does not need additional technology steps, a making process which is essentially the same as the prior art can be used, and the making cost can not be increased.
Description
Technical field
The invention relates to a kind of manufacture method of semiconductor device, and particularly can improve the manufacture method of the semiconductor device of operating voltage relevant for a kind of usefulness.
Background technology
High voltage most is widely used in many electronic installations, as the Voltage Supply Device of central processing unit, power-supply management system, AC/DC changeover switch etc.Because the high pressure metal oxide semitransistor normally operates under the high operation voltage, therefore may cause a high electric field and cause producing much more extremely hot electrons near the composition surface of raceway groove and drain electrode.These hot electrons can be promoted near the electronics the drain electrode in the conducting band and form electron-hole pair, and near the shared eletron draining is impacted.Most because of the electronics of hot electron after being ionized can move to drain electrode and increase drain current Id, and another few ionization electron partly can inject and be absorbed in grid oxic horizon, causes the change of grid limit voltage.On the contrary, the hole that produces because of hot electron can flow to substrate and produce a drain current Isub.When operating voltage rose, the quantity of electron-hole pair also can and then increase and cause so-called " charge carrier multiplication " (carrier multiplication) phenomenon.
Fig. 1 shows that a tradition has the profile of the high voltage most in side diffused drain district.As shown in Figure 1, high voltage most 130 is formed on the semiconductor wafer 110.Semiconductor wafer 110 has a P type silicon substrate 111 and and is formed at P type silicon substrate 111 lip-deep P type extensions (epitaxial) layer 112.High voltage most 130 has a P type trap 121, and is formed at N type source area 122, in the P type trap 121 and is formed at a N type drain region 124 and a grid 114 in the P type epitaxial loayer 112.
When above-mentioned drain current Isub flowed through P type silicon substrate 111, P type silicon substrate 111 resistance R sub own can produce an induced voltage Vb.When if induced voltage Vb is enough big, just 122 of P type silicon substrate 111 and source electrodes forward bias voltage drop can take place and form so-called parasitic double carriers junction transistors 140 simultaneously.When parasitic transistor 140 is switched on, can heighten by drain electrode 124 electric currents that flow to source electrode 122, and produce electricity collapse phenomenon, cause high voltage most 130 faults.
In some high voltage most, for a higher breakdown voltage is provided, a kind of structure that is called double-diffused drain electrode (Double Diffuse Drain) has all been used in its source/drain electrode.Fig. 2 has shown No. 5770880 disclosed high voltage most with double-diffused drain electrode in the U.S..One substrate 210 has N mold base 212.Grid 220 on grid oxic horizon 222 is formed at one source pole 230 and drains between 240.It is identical and interchangeable that source electrode and drain electrode come down to, therefore following will only describing drain electrode.Each drain electrode has a dual diffusion region, comprises one first heavy dense doping contact zone 214 and one light doped region 216.These diffusing, doping districts carry out P type ion (as the boron ion) and implant, carry out annealing steps and make ions diffusion enter substrate 210 and form P type doped region 214 and 216 via form the surfaces of substrate 210 being exposed opening 219 backs on oxide layer 218.Contact zone 214 normally is limited to the surface and does not go deep in the N mold base 212.Second 216 heavy of the light doped regions are to go deep in the matrix 212 and have partly being positioned at grid 220 belows.212 of doped region 216 and N mold bases form a composition surface, and this composition surface promptly provides the breakdown voltage value of element.Diffusing, doping district 216 has a low doping concentration gradient, can be reduced near the electric field level that causes reverse biased matrix-drain junction.So can make element before breakdown voltage reaches, can under a high voltage, operate.Yet making said elements needs complicated technology and may need extra mask, so manufacturing cost is also higher.
Therefore, the utmost point needs a kind of new semiconductor device and manufacture method thereof, can improve the breakdown voltage of element and not need additionally to increase manufacturing cost.
Summary of the invention
The invention provides a kind of semiconductor device and manufacture method thereof, this semiconductor device comprises: semi-conductive substrate comprises one first type trap and one second type trap; A plurality of interfaces, between this first type trap and one second type trap, wherein each interface and is close to this first type and the second type trap between this first type trap and this second type trap, and wherein said a plurality of interfaces are doped with P type ion and N type ion; One grid is arranged on this Semiconductor substrate, and this grid is positioned at least on the two of described a plurality of interface; And an one source pole and a drain electrode, be arranged in this Semiconductor substrate of these grid both sides.
The present invention provides a kind of manufacture method of semiconductor device again, comprising: semi-conductive substrate is provided; Form one first type trap in this Semiconductor substrate; And forming one second type trap and a plurality of interface in this Semiconductor substrate, each of wherein said a plurality of interfaces and is close to this first type trap and this second type trap between this first type trap and this second type trap;
The formation method in the wherein said first type trap, the described second type trap and described a plurality of interfaces comprises:
Form one first photoresist layer on described Semiconductor substrate;
One first mask is provided;
Utilize described first mask to carry out an exposure technology, to shift in described first photoresist layer of pattern to the described Semiconductor substrate on described first mask;
As mask, carry out one first type implanting ions technology with described first photoresist layer, to form the described first type trap in described Semiconductor substrate;
Remove described first photoresist layer;
Form one second photoresist layer on described Semiconductor substrate;
One second mask is provided;
Utilize described second mask to carry out an exposure technology, to shift in described second photoresist layer of pattern to the described Semiconductor substrate on described second mask; And
Carry out one second type implanting ions technology with described second photoresist layer as mask, forming the described second type trap and described a plurality of interface in described Semiconductor substrate,
A plurality of again interfaces are doped with P type ion and N type ion simultaneously, and described a plurality of interface is to utilize the described first type implanting ions technology, form the described first type trap and utilize the described second type implanting ions technology, and the step that forms the described second type trap forms.
The present invention also provides a kind of semiconductor device, and described semiconductor device comprises:
Semi-conductive substrate comprises one first type trap and one second type trap;
A plurality of interfaces, between described first type trap and one second type trap, wherein each interface is between described first type trap and the described second type trap, and is close to described first type and the second type trap, and wherein said a plurality of interfaces and described Semiconductor substrate have the identical conduction kenel;
One grid is arranged on the described Semiconductor substrate, and described grid is positioned at least on the two of described a plurality of interfaces; And
An one source pole and a drain electrode are arranged in the described Semiconductor substrate of described grid both sides.
The present invention also provides a kind of manufacture method of semiconductor device, and the manufacture method of described semiconductor device comprises:
Semi-conductive substrate is provided;
Form one first type trap in described Semiconductor substrate; And
Form one second type trap and a plurality of interface in described Semiconductor substrate, each of wherein said a plurality of interfaces and is close to described first type trap and the described second type trap between described first type trap and the described second type trap,
The formation method in the wherein said first type trap, the described second type trap and described a plurality of interfaces comprises:
Form one first photoresist layer on described Semiconductor substrate;
One first mask is provided;
Utilize described first mask to carry out an exposure technology, to shift in described first photoresist layer of pattern to the described Semiconductor substrate on described first mask;
As mask, carry out one first type implanting ions technology with described first photoresist layer, to form the described first type trap in described Semiconductor substrate;
Remove described first photoresist layer;
Form one second photoresist layer on described Semiconductor substrate;
One second mask is provided;
Utilize described second mask to carry out an exposure technology, to shift in described second photoresist layer of pattern to the described Semiconductor substrate on described second mask; And
Carry out one second type implanting ions technology with described second photoresist layer as mask, forming the described second type trap and described a plurality of interface in described Semiconductor substrate,
Described a plurality of interface and described Semiconductor substrate have the identical conduction kenel, and described a plurality of interface is to utilize the described first type implanting ions technology, form the described first type trap and utilize the described second type implanting ions technology, the step that forms the described second type trap forms.
Compared to traditional semiconductor element, utilize the semiconductor element of the foregoing description made, can promote the grid operating voltage range more than 30% approximately.Moreover, because the manufacture method of the semiconductor element of the foregoing description does not need additionally to increase processing step, therefore can use the manufacturing process identical in fact, and can not increase manufacturing cost with known technology.
Description of drawings
Fig. 1 illustrates the profile of a known semiconductor element.
Fig. 2 illustrates the profile of a known semiconductor element.
Fig. 3 to Fig. 9 is profile and the manufacturing step thereof that illustrates according to the semiconductor element of an embodiment manufacturing.
Figure 10 A shows the drain voltage-drain current measuring value of a traditional semiconductor element.
Figure 10 B shows the drain voltage-drain current measuring value of the semiconductor element of one embodiment of the invention.
Drawing reference numeral:
15a～photoresist layer; 15b～patterning photoresist layer; 16～predetermined the position that forms the first type implanting ions district; 18～photoresist layer; 19～patterning photoresist layer; 20～the first type implanting ions technologies; 21～the second type implanting ions districts; The position of 22～formation interface 106a; 23～be predefined in the P type substrate 100 position that forms the interface; 30～the second type implanting ions technologies; 60～shading region; 61～transparent area; 70～shading region; 71～transparent area; 74～fleet plough groove isolation structure; 80～shading region; 100～P type substrate; 102～the first type traps; 104～the second type traps; 106a～interface; 106b～interface; 110～semiconductor wafer; 111～P type silicon substrate; 112～P type epitaxial loayer; 116～MOS device; 120～gate electrode; 121～P type trap; 122～N type source area; 123～source area; 124～drain region; 125～gate dielectric; 130～high voltage most; 140～parasitic double carriers junction transistors; 210～substrate; 212～N mold base; 214～the first heavy dense doping contact zones; 216～light doped region; 218～oxide layer; 219～opening; 220～grid; 222～grid oxic horizon; 230～source electrode; 240～drain electrode; 200～element region; 300～PN junction; 500～mask; 600～mask; 700～mask.
Embodiment
Below will describe in detail as reference of the present invention, and example is accompanied by and illustrates with embodiment.In diagram or description, similar or identical part is to use identical figure number.In diagram, the shape of embodiment or thickness can enlarge, to simplify or convenient the sign.The part of element will be to describe explanation in the diagram.Be understandable that the element that does not illustrate or describe, the form known to can those skilled in the art.In addition, when narration one deck was positioned at a substrate or another layer and goes up, this layer can be located immediately on substrate or another layer, or intermediary layer can also be arranged therebetween.
Fig. 3 to Fig. 9 is the manufacturing process profile of the semiconductor device of preferred embodiment of the present invention.
Please refer to Fig. 3, at first, provide the Semiconductor substrate of P type substrate 100 for example.P type substrate 100 is preferably silicon substrate.In another embodiment, P type substrate 100 comprises germanium silicide (SiGe), silicon-on-insulator (silicon on insulator, SOI) substrate or other semiconductive material substrate.Then, carry out lithography process, be coated with a photoresist layer 15a on P type substrate 100.One mask 500 is provided subsequently, and it comprises a shading region 60 and a transparent area 61.Then, make light 5 by above-mentioned mask 500 carrying out a step of exposure, and shift among the photoresist layer 15a of pattern to the P type substrate 100 on the mask 500.
As shown in Figure 4, implement a developing process subsequently, remove the part that photoresist layer 15a is not covered by above-mentioned shading region 60, and form patterning photoresist layer 15b, and define the predetermined position 16 that forms the first type implanting ions district by patterning photoresist layer 15b.
Then, please refer to Fig. 5, it illustrates with patterning photoresist layer 15b as mask, P type substrate 100 is carried out one first type implanting ions technology 20, to form one first type trap 102 in P type substrate 100.Wherein, the above-mentioned first type ion can be N type or P type ion.
In the present embodiment, the manufacture method of mask 500 comprises: one first integrated circuit layout (lay-out) database is provided earlier, comprises the first type trap, 102 data.Utilize this first integration circuit layout data storehouse subsequently again, form mask 500.
As shown in Figure 6A, after removing patterning photoresist layer 15b, code-pattern forms a photoresist layer 18 on P type substrate 100.Then, provide a mask 600, comprise a shading region 70 and a transparent area 71.Then, make light 6 by above-mentioned mask 600 carrying out an exposure technology, and shift in the photoresist layer 18 of pattern to the P type substrate 100 on the mask 600.
Please refer to Fig. 7, implement a developing process subsequently, remove the part that photoresist layer 18 is not covered by above-mentioned shading region 70, and form patterning photoresist layer 19, and define the predetermined position that forms the second type implanting ions district 21 and interface 22 by patterning photoresist layer 19.Then, be mask with patterning photoresist layer 19, P type substrate 100 is carried out one second type implanting ions technology 30, to form the second type trap 104 and a plurality of interface 106a in P type substrate 100.Wherein, the above-mentioned second type ion can be N type ion or P type ion, and with the first type ion be the ion of opposite conductivity type attitude.It should be noted that mask 600 and above-mentioned mask 500 have complementary pattern.Therefore, can be by the transparent area on this two mask of adjustment or the scope of shading region, with a plurality of interface 106a of formation between the above-mentioned first type trap 102 and the second type trap 104, and each interface 106a is close to the first type trap 102 and the second type trap 104.The manufacture method of above-mentioned mask 600 comprises: one second integration circuit layout data storehouse is provided earlier, comprises the first type trap, 102 data, the second type trap, 104 data and interface 106a data.Then, read this layout database, and carry out a cloth woods logical operation, to obtain an operation result.Utilize this logic operation result to form mask 600 at last again.Wherein, above-mentioned interface 106a between 0.2 μ m and 5 μ m, is preferably 0.5 μ m to 1.5 μ m approximately.
Please referring again to Fig. 3 to Fig. 7, be the shading scope that utilize to shorten the shading region 70 (as shown in Figure 6A) of the shading region 60 (as shown in Figure 3) of mask 500 or mask 600 in the present embodiment, between this two shading region, to form an extra transparent area (figure shows).But the scope of the horizontal expansion first type trap 102 like this and the second type trap 104, make win type trap 102 and generation doping overlapping zone, the second type trap, 104 edges, therefore, after finishing above-mentioned first type implanting ions technology 20 and the second type implanting ions technology, 30 technologies respectively, can on P type substrate 100, form a plurality of interface 106a that are doped with above-mentioned first type and the second type ion simultaneously.In one embodiment, the doping of the first type implanting ions technology 20 is greater than the doping of the second type implanting ions technology 30, thereby can form the first type ion district of a light doping (LightlyDoped) in the 106a of interface.In another embodiment, by the second type ion high that mix, in each interface 106a, to form the second type ion district of a light doping than the first type ion concentration.
Hookup 5 also please refer to Fig. 6 B, and it illustrates and forms an interface another embodiment in P type substrate 100.Compared to the embodiment of Fig. 7 different be, the shading scope of the shading region 80 of the mask 700 of present embodiment is big than the shading region 70 of mask 600, so can laterally reduce the scope of the first type trap 102 and the second type trap 104, make after finishing above-mentioned first type implanting ions technology 20 and one second type implanting ions, 40 technologies respectively, can on P type substrate 100, form the interface 106b of a plurality of do not mix above-mentioned first type and the second type ions.In other words, these a little interface 106b be in fact with the zone of P type substrate 100 identical conduction kenels.
Hookup 7 also please refer to Fig. 8, and it illustrates and for example forms fleet plough groove isolation structure in P type substrate 100 (shallow trench isolation, STI) a plurality of isolation structures of 74 are to define element region 200.Generally speaking, the manufacture method of fleet plough groove isolation structure comprises the steps: at first etching P type substrate 100, to form a depression, then with for example high-density electric slurry (high-density plasma, HDP) dielectric material of oxide is inserted in this depression, (chemical mechanical polish, flatening process CMP) removes excessive dielectric material, to form fleet plough groove isolation structure via for example cmp again.Yet, this isolation structure also can be utilize known regional oxidizing process (Local Oxidation of Silicon, LOCOS) formed field oxide (Field Oxide, FOX).
Please refer to Fig. 9, it illustrates and forms a metal-oxide semiconductor (MOS) (MOS) device 116 in said elements district 200.MOS device 116 also comprises gate dielectric 125.In a preferred embodiment, gate dielectric 125 comprises oxide layer, and this gate dielectric 125 can be by in the environment that contains oxide, water, nitric oxide (NO) or its combination, oxidation technology with for example dry type or wet type thermal oxidation (thermaloxidation) forms, or utilize with tetraethyl silica alkane (Tetraethoxysilane, TEOS) and oxygen form as chemical vapor deposition (CVD) technology of predecessor (precursor).The formation step of above-mentioned MOS device 116 comprises: at first, form a gate electrode 120 on P type semiconductor substrate 100, and gate electrode 120 is formed at the two top at least of above-mentioned interface 106a.Form an one source pole 123 and a drain electrode 124 subsequently again in the P type semiconductor substrate 100 of gate electrode 120 both sides.Wherein, source area 123 and drain region 124 can use known ionic-implantation to form, and source area 123 and drain region 124 have the conductivity identical with the first type trap 102.
The gate electrode 120 preferable for example electric conducting materials of tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), platinum (Pt), aluminium (Al), hafnium (Hf), ruthenium (Ru) or its silicide or nitride that comprise.In a preferred embodiment, gate electrode 120 is made up of polysilicon, and can mix or unadulterated polysilicon forms by chemical vapor deposition (CVD) method deposition.
Above-mentioned gate electrode 120 can use for example little shadow technology to carry out patterning (patterned) with gate dielectric 125.Generally speaking, lithography process comprises: be coated with a photoresist, this photoresist carried out masking film (masked), exposure (exposed) and development (developed) subsequently, to form a photo-resistive mask (photoresist mask) again.Then, after this photo-resistive mask of patterning, etching technics can be carried out, removing undesired part in above-mentioned gate electrode material and the grid dielectric material, thereby the gate electrode 120 and gate dielectric 125 that shows as Fig. 8 can be formed.
Similarly, in another embodiment, the MOS device 116 that utilizes said method also can form to include gate electrode 120, gate dielectric 125, source area 123 and drain region 124 is on the P of the embodiment of Fig. 6 B type substrate 100, and wherein gate electrode 120 is positioned at the two top at least (figure shows) of interface 106b.
It should be noted that, because above-mentioned interface 106a or interface 106b are between the first type trap 102 and the second type trap 104, therefore can form a PN junction (P-N Junction) 300 respectively between the second type trap 104 below source area 123 and the gate electrode 120 and between the second type trap 104 below drain region 124 and the gate electrode 120.Utilize this PN junction 300 can between the second type trap 104 below source area 123 and/or drain region 124 and the gate electrode 120, produce a depletion region, breakdown voltage in the time of can improving MOS device 116 operations by this depletion region, and then the operating voltage of lift elements (operation voltage) scope.
Please refer to Figure 10 A and Figure 10 B, it is presented at respectively under the different grid operating voltages, the drain voltage of the semiconductor element of the drain voltage of traditional semiconductor element-drain current measuring value and one embodiment of the invention-drain current measuring value.Shown in Figure 10 A, the grid operating voltage (Vg) of traditional semiconductor element is approximately between 0V～45V.Yet shown in Figure 10 B, the grid operating voltage of the semiconductor element of one embodiment of the invention can be increased to 0V～60V.In other words,, utilize the semiconductor element of the foregoing description made, can promote the grid operating voltage range more than 30% approximately compared to traditional semiconductor element.Moreover, because the manufacture method of the semiconductor element of the foregoing description does not need additionally to increase processing step, therefore can use the manufacturing process identical in fact, and can not increase manufacturing cost with prior art.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; change and retouching when doing, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (10)
1. the manufacture method of a semiconductor device is characterized in that, the manufacture method of described semiconductor device comprises:
Semi-conductive substrate is provided;
Form one first type trap in described Semiconductor substrate; And
Form one second type trap and a plurality of interface in described Semiconductor substrate, each of wherein said a plurality of interfaces and is close to described first type trap and the described second type trap between described first type trap and the described second type trap;
The formation method in the wherein said first type trap, the described second type trap and described a plurality of interfaces comprises:
Form one first photoresist layer on described Semiconductor substrate;
One first mask is provided;
Utilize described first mask to carry out an exposure technology, to shift in described first photoresist layer of pattern to the described Semiconductor substrate on described first mask;
As mask, carry out one first type implanting ions technology with described first photoresist layer, to form the described first type trap in described Semiconductor substrate;
Remove described first photoresist layer;
Form one second photoresist layer on described Semiconductor substrate;
One second mask is provided;
Utilize described second mask to carry out an exposure technology, to shift in described second photoresist layer of pattern to the described Semiconductor substrate on described second mask; And
Carry out one second type implanting ions technology with described second photoresist layer as mask, forming the described second type trap and described a plurality of interface in described Semiconductor substrate,
A plurality of again interfaces are doped with P type ion and N type ion simultaneously, and described a plurality of interface is to utilize the described first type implanting ions technology, form the described first type trap and utilize the described second type implanting ions technology, and the step that forms the described second type trap forms.
2. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the manufacture method of described semiconductor device also comprises:
Form a grid on described Semiconductor substrate; And
Forming one source pole and drains in the described Semiconductor substrate of described grid both sides.
3. the manufacture method of semiconductor device as claimed in claim 2 is characterized in that, described grid is positioned at the two top at least in described a plurality of interfaces.
4. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the manufacture method of described first mask comprises:
One first integration circuit layout data storehouse is provided, comprises the described first type trap data; And
Utilize the described first integration circuit layout data storehouse, form described first mask.
5. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the manufacture method of described second mask comprises:
One second integration circuit layout data storehouse is provided, comprises the described first type trap data, the described second type trap data and described a plurality of interfaces data;
Read the described second integration circuit layout data storehouse, and carry out a cloth woods logical operation, to obtain an operation result; And
Utilize described logic operation result to form described second mask.
6. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the described first type trap is P type trap or N type trap, and the described second type trap has opposite conductivity with the described first type trap.
7. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the length in described a plurality of interfaces is between 0.2 μ m and 5 μ m.
8. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the doping of described P type ion is greater than or less than the doping of described N type ion.
9. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, described a plurality of interface and described Semiconductor substrate have the identical conduction kenel, and described a plurality of interface is to utilize the described first type implanting ions technology, form the described first type trap and utilize the described second type implanting ions technology, the step that forms the described second type trap forms.
10. a semiconductor device is characterized in that, described semiconductor device comprises:
Semi-conductive substrate comprises one first type trap and one second type trap;
A plurality of interfaces, between described first type trap and one second type trap, wherein each interface and is close to described first type and the second type trap between described first type trap and the described second type trap, and wherein said a plurality of interfaces are doped with P type ion and N type ion;
One grid is arranged on the described Semiconductor substrate, and described grid is positioned at least on the two of described a plurality of interfaces; And
An one source pole and a drain electrode are arranged in the described Semiconductor substrate of described grid both sides.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6306700B1 (en) * | 2000-08-07 | 2001-10-23 | United Microelectronics Corp. | Method for forming high voltage devices compatible with low voltages devices on semiconductor substrate |
| CN1967870A (en) * | 2005-11-16 | 2007-05-23 | 台湾积体电路制造股份有限公司 | Semiconductor structure and its forming method, transverse diffusion p-type mos device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6306700B1 (en) * | 2000-08-07 | 2001-10-23 | United Microelectronics Corp. | Method for forming high voltage devices compatible with low voltages devices on semiconductor substrate |
| CN1967870A (en) * | 2005-11-16 | 2007-05-23 | 台湾积体电路制造股份有限公司 | Semiconductor structure and its forming method, transverse diffusion p-type mos device |
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