EP2710475A1 - Mémoire rémanente et méthode avec des petits groupes logiques répartis entre des partitions de mémoire slc et mlc actives - Google Patents

Mémoire rémanente et méthode avec des petits groupes logiques répartis entre des partitions de mémoire slc et mlc actives

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Publication number
EP2710475A1
EP2710475A1 EP12722632.2A EP12722632A EP2710475A1 EP 2710475 A1 EP2710475 A1 EP 2710475A1 EP 12722632 A EP12722632 A EP 12722632A EP 2710475 A1 EP2710475 A1 EP 2710475A1
Authority
EP
European Patent Office
Prior art keywords
logical
data
memory
block
slc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP12722632.2A
Other languages
German (de)
English (en)
Inventor
Sergey Anatolievich Gorobets
William S. Wu
Stephen T. SPROUSE
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SanDisk Technologies LLC
Original Assignee
SanDisk Technologies LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/468,720 external-priority patent/US20120297121A1/en
Application filed by SanDisk Technologies LLC filed Critical SanDisk Technologies LLC
Publication of EP2710475A1 publication Critical patent/EP2710475A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0611—Improving I/O performance in relation to response time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/068—Hybrid storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7202—Allocation control and policies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7203—Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7205—Cleaning, compaction, garbage collection, erase control
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5641—Multilevel memory having cells with different number of storage levels

Definitions

  • This application relates to the operation of re -programmable non- volatile memory systems such as semiconductor flash memory, and, more specifically, to efficient storing of data in hierarchical layers of memory partitions.
  • Solid-state memory capable of nonvolatile storage of charge, particularly in the form of EEPROM and flash EEPROM packaged as a small form factor card, has become the storage of choice in a variety of mobile and handheld devices, notably information appliances and consumer electronics products.
  • RAM random access memory
  • flash memory is non-volatile, and retaining its stored data even after power is turned off.
  • ROM read only memory
  • flash memory is rewritable similar to a disk storage device.
  • flash memory is increasingly being used in mass storage applications. More recently, flash memory in the form of solid-state disks (“SSD”) is beginning to replace hard disks in portable computers as well as in fixed location installations.
  • Flash EEPROM is similar to EEPROM (electrically erasable and programmable read-only memory) in that it is a non-volatile memory that can be erased and have new data written or "programmed" into their memory cells. Both utilize a floating (unconnected) conductive gate, in a field effect transistor structure, positioned over a channel region in a semiconductor substrate, between source and drain regions. A control gate is then provided over the floating gate. The threshold voltage characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, for a given level of charge on the floating gate, there is a corresponding voltage (threshold) that must be applied to the control gate before the transistor is turned “on” to permit conduction between its source and drain regions.
  • flash memory such as Flash EEPROM allows entire blocks of memory cells to be erased at the same time.
  • the floating gate can hold a range of charges and therefore can be programmed to any threshold voltage level within a threshold voltage window.
  • the size of the threshold voltage window is delimited by the minimum and maximum threshold levels of the device, which in turn correspond to the range of the charges that can be programmed onto the floating gate.
  • the threshold window generally depends on the memory device's characteristics, operating conditions and history. Each distinct, resolvable threshold voltage level range within the window may, in principle, be used to designate a definite memory state of the cell.
  • a single-level-cell (SLC) memory has each cell storing a single bit of data by operating in a binary mode, where a single reference level differentiates between two ranges of threshold levels of each storage element.
  • the threshold levels of transistors correspond to ranges of charge levels stored on their storage elements.
  • the trend is to further increase the density of data storage of such memory arrays by storing more than one bit of data in each storage element transistor.
  • a multi-level-cell (MLC) memory has each cell storing more a single bit of data by operating in a multilevel mode, where two or more reference levels differentiates between more than two ranges of threshold levels of each storage element.
  • MLC multi-level-cell
  • Each storage element memory transistor has a certain total range (window) of threshold voltages in which it may practically be operated, and that range is divided into the number of states defined for it plus margins between the states to allow for them to be clearly differentiated from one another. Obviously, the more bits a memory cell is configured to store, the smaller is the margin of error it has to operate in.
  • the transistor serving as a memory cell is typically programmed to a "programmed" state by one of two mechanisms.
  • hot electron injection a high voltage applied to the drain accelerates electrons across the substrate channel region.
  • control gate pulls the hot electrons through a thin gate dielectric onto the floating gate.
  • tunnel injection a high voltage is applied to the control gate relative to the substrate. In this way, electrons are pulled from the substrate to the intervening floating gate.
  • program has been used historically to describe writing to a memory by injecting electrons to an initially erased charge storage unit of the memory cell so as to alter the memory state, it has now been used interchangeable with more common terms such as “write” or "record.”
  • the memory device may be erased by a number of mechanisms.
  • a memory cell is electrically erasable, by applying a high voltage to the substrate relative to the control gate so as to induce electrons in the floating gate to tunnel through a thin oxide to the substrate channel region (i.e., Fowler-Nordheim tunneling.)
  • the EEPROM is erasable byte by byte.
  • the memory is electrically erasable either all at once or one or more minimum erasable blocks at a time, where a minimum erasable block may consist of one or more sectors and each sector may store 512 bytes or more of data.
  • the memory device typically comprises one or more memory chips that may be mounted on a card.
  • Each memory chip comprises an array of memory cells supported by peripheral circuits such as decoders and erase, write and read circuits.
  • peripheral circuits such as decoders and erase, write and read circuits.
  • the more sophisticated memory devices also come with a controller that performs intelligent and higher level memory operations and interfacing. More recently, the memory devices in the form of SSD are being offered commercially in the form factor of a standard hard drive.
  • non-volatile solid-state memory devices There are many commercially successful non-volatile solid-state memory devices being used today. These memory devices may be flash EEPROM or may employ other types of nonvolatile memory cells. Examples of flash memory and systems and methods of manufacturing them are given in United States patents nos. 5,070,032, 5,095,344, 5,315,541, 5,343,063, and 5,661,053, 5,313,421 and 6,222,762. In particular, flash memory devices with NAND string structures are described in United States patent nos. 5,570,315, 5,903,495, 6,046,935.
  • Nonvolatile memory devices are also manufactured from memory cells with a dielectric layer for storing charge. Instead of the conductive floating gate elements described earlier, a dielectric layer is used. Such memory devices utilizing dielectric storage element have been described by Eitan et al., "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, no. 11, November 2000, pp. 543-545.
  • An ONO dielectric layer extends across the channel between source and drain diffusions. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit is localized in the dielectric layer adjacent to the source.
  • United States patents nos. 5,768,192 and 6,011,725 disclose a nonvolatile memory cell having a trapping dielectric sandwiched between two silicon dioxide layers. Multi-state data storage is implemented by separately reading the binary states of the spatially separated charge storage regions within the dielectric.
  • Flash memory behaves quite differently from traditional disk storage or RAM.
  • a block generally contains a number of pages. As data is stored in a block page by page, eventually some of that data becomes obsolete. This means the block will contain many garbage data taking up space. However, the block can only be erased as a unit and so before the garbage data can be erased with the block, the valid data in the block must first be salvaged and copied into another block. This operation is commonly referred to as garbage collection and is an overhead of the block structure of the flash memory. The larger the block, the more time is required for the garbage collection. Similarly, the more frequently the data in the block is being updated, the more frequently will the block need to be garbage collect. Garbage collection is preferably performed in the foreground like during a write operation. This obviously will degrade the write speed.
  • the addressing granularity is mainly at the block level as a page with a given logical address can be located by which block is storing the logical group it belongs to. Since the logical group is stored in the block in a self-indexed manner with its logical addresses in sequential order, the page can be quickly located.
  • the block management system implementing logical groups typically deals with updates and non-sequential writes by tracking them at the page level. It budgets a predetermined amount of resource for the page level tracking which manifests has limiting the number of logical groups having non-sequential or obsolete data. Generally, when subject to updates, some of the orderly blocks will contain obsolete data and keeping track of them will also consume part of the resource. When over the budget, a selected block with non-sequential or obsolete data is restored back to an orderly block in sequential order. This is accomplished by rewriting into a new block in sequential order with the latest updates. However the relocation will exact a performance hit.
  • the block management system implementing logical groups will begin to be less optimized if the host writes mostly short and non-sequential data.
  • This type of write pattern is prevalent in applications from a personal computer or smart mobile device.
  • SSD Solid-state disk
  • flash memory instead of long sequential writes, the flash memory must now deal mostly with short random writes. Initially, the performance will not suffer since as long as free space can be found, the data can be written there. However, with constant use and frequent updates, the predetermined resource for page tracking will eventually be exhausted. At that point, performance can take a big hit as the next write may have to be accompanied by a relocation of a block.
  • the problem with the large block size can not be easily solved by simply reducing the block size as the block size tend to increase geometrically with each new generation of memory technology. With higher integration of circuits more memory cells are being fitted in the same die.
  • the block size measure in columns and rows increases geometrically. This is especially the case for memory of the NAND type.
  • the memory is an array of NAND strings where each string is a daisy chain of memory cells and a minimum erase block must be formed by a row of such NAND string. If the NAND string has 32 cells, a block will contain 32 rows of cells. The number of memory cells in a NAND string also increases with each generation, so the block size increases column-wise and row-wise.
  • the block size which is dictated by the physical memory structure, is in present generation as large as 4MB.
  • the operating system of personal computers typically allocates logical sectors in size of 512kB and often writes a page as a cluster of logical sectors in 4kB unit.
  • the ideal situation for a block is either nothing is written or the block is filled up sequentially with the entire logical group of valid data. In either case there is no fragmentation and there is no need for garbage collection or relocation.
  • the block becomes non-ideal very quickly and eventually will need relocation. This amounts to inefficient writes since the same page may have to be written and then re- copied one or more times (also referred to as "write amplification".)
  • An alternative, conventional addressing approach suitable for short random writes is to not use logical groups, but to track every page independently as it is being written to a block. Instead of maintaining the stored data as orderly logical group in a block, each page is tracked as to which block it is stored in and at what offset in the block.
  • this page addressing scheme there is no burden of storing or maintaining data in groups in order of sequential logical addresses.
  • the page addressing scheme will have an address table much larger than that for the logical group address scheme. For example, if there are 1000 pages in a block, then the address table for the page addressing scheme will be approximately 2 to 3 orders of magnitude larger.
  • a nonvolatile memory is provided with a block management system in which an ordered logical address range from a host is partitioned into logical groups where a block stores multiple logical groups of data.
  • Each logical group is of a size having a range from at least the same order of magnitude to an order of magnitude higher as the size of a host write but at least of a size of a page or metapage which is a unit of read or write of maximum parallelism supported by the memory.
  • the logical group By having the size of the logical group decoupled from that of the erase block, and being of a size more compatible with the size and nature of host writes, the logical group provides the benefit of simplifying addressing and conserving limited system resource while not triggering excessive rewrites which impact performance.
  • each block will hold not one but multiple logical blocks of data.
  • the host writes are buffered and staged logical-group by logical-group, which are then written into a block.
  • the memory is partitioned in SLC and MLC portions and comprises, first, second and third operational and functional layers.
  • the first and second layers operate in the SLC portion.
  • the third layer operates in the MLC portion.
  • the first layer is for initially storing write data from a host and staging the data logical-group by logical-group before relocating each logical group into either the second or third layer.
  • the second layer provides active storage in a pool of SLC blocks for storing host data at the logical-group level. When the pool is full, more room is made by evicting the logical groups with the least potential rewrites to the third layer which stores at a higher density.
  • the second layer provides a fast SLC storage area where fragmented and medium size host writes land. Unlike prior systems, where there is no second layer and the first layer essentially acts as a FIFO to transmit data to the third layer in MLC storage before the data can be accessed, this second layer maintains a working set of user data in the fast SLC storage area.
  • FIG. 1 illustrates a host in communication with a memory device in which the features of the present invention are embodied.
  • FIG. 2 illustrates a page of memory cells, organized for example in the NAND configuration, being sensed or programmed in parallel.
  • FIG. 3 illustrates schematically an example of a memory array organized in erasable blocks.
  • FIG. 4 illustrates schematically a memory chip having multiple arrays and operations for maximum parallelism.
  • FIG. 5 illustrates schematically, a memory structure having higher degree of parallelism.
  • FIG. 6 illustrates a binary memory having a population of cells with each cell being in one of two possible states.
  • FIG. 7 illustrates a multi-state memory having a population of cells with each cell being in one of eight possible states.
  • FIG. 8 illustrates an example of a physical memory architecture suitable for practicing the invention.
  • FIG. 9 illustrates schematically the data path between the SLC portion and the MLC portion in a 2-layer data storage system.
  • FIG. 10 illustrates in more detail the SLC layer shown in FIG. 9.
  • FIG. 11 illustrates a page in the memory organization of the block management system according to the present invention.
  • FIG. 12 illustrates a logical group in the block management system.
  • FIG. 13A illustrates an erase block accommodating data from multiple logical groups.
  • FIG. 13B is a flow diagram illustrating the scheme of storing host writes to the non- volatile memory in terms of small logical groups.
  • FIG. 14 illustrates a system architecture for managing the blocks and pages across the different memory partitions according to the present invention.
  • FIG. 15 illustrates in more details the second layer shown in FIG. 14.
  • FIG. 16 illustrates the 'temperature' sorting of the logical groups for the 'hot' logical group case.
  • FIG. 17 illustrates the 'temperature' sorting of the logical groups for the 'cold' logical group case.
  • FIG. 18 illustrates how different types of writes are sorted into block streams according to their perceived temperature interactively.
  • FIG. 19 is a flow diagram illustrating the scheme of temperature sorting for memory storage and operations.
  • FIG. 20 is a flow diagram illustrating the scheme of temperature sorting at the logical group level.
  • FIG. 21 is a flow diagram illustrating the scheme of temperature sorting at the block level.
  • FIG. 1 illustrates a host in communication with a memory device in which the features of the present invention are embodied.
  • the host 80 typically sends data to be stored at the memory device 90 or retrieves data by reading the memory device 90.
  • the memory device 90 includes one or more memory chip 100 managed by a memory controller 102.
  • the memory chip 100 includes a memory array 200 of memory cells with each cell capable of being configured as a multi-level cell ("MLC") for storing multiple bits of data, as well as capable of being configured as a single-level cell (“SLC”) for storing 1 bit of data.
  • MLC multi-level cell
  • SLC single-level cell
  • the memory chip also includes peripheral circuits 204 such as row and column decoders, sense modules, data latches and I/O circuits.
  • An on-chip control circuitry 110 controls low-level memory operations of each chip.
  • the control circuitry 110 is an on-chip controller that cooperates with the peripheral circuits to perform memory operations on the memory array 200.
  • the control circuitry 110 typically includes a state machine 112 to provide chip level control of memory operations via a data bus 231 and control and address bus 111.
  • the host 80 communicates and interacts with the memory chip 100 via the memory controller 102.
  • the controller 102 co-operates with the memory chip and controls and manages higher level memory operations.
  • a firmware 60 provides codes to implement the functions of the controller 102.
  • An error correction code (“ECC”) processor 62 processes ECC during operations of the memory device.
  • ECC error correction code
  • the host 10 sends data to be written to the memory array 100 in logical sectors allocated from a file system of the host's operating system.
  • a memory block management system implemented in the controller stages the sectors and maps and stores them to the physical structure of the memory array.
  • a preferred block management system is disclosed in United States Patent Application Publication Number: US-2010-0172180-Al, the entire disclosure of which is incorporated herein by reference.
  • FIG. 2 illustrates a page of memory cells, organized for example in the NAND configuration, being sensed or programmed in parallel.
  • FIG. 2 essentially shows a bank of NAND strings 50 in the memory array 200 of FIG. 1.
  • a "page" such as the page 60, is a group of memory cells enabled to be sensed or programmed in parallel. This is accomplished in the peripheral circuits by a corresponding page of sense amplifiers 210.
  • the sensed results are latches in a corresponding set of data latches 220.
  • Each sense amplifier can be coupled to a NAND string, such as NAND string 50 via a bit line 36.
  • the page 60 is along a row and is sensed by a sensing voltage applied to the control gates of the cells of the page connected in common to the word line WL3.
  • each cell such as cell 10 is accessible by a sense amplifier via a bit line 36.
  • Data in the data latches 220 are toggled in from or out to the memory controller 102 via a data I/O bus 231.
  • the page referred to above is a physical page memory cells or sense amplifiers.
  • each physical page has multiple data pages.
  • the NAND string 50 is a series of memory transistors 10 daisy-chained by their sources and drains to form a source terminal and a drain terminal respective at its two ends.
  • a pair of select transistors SI, S2 controls the memory transistors chain's connection to the external via the NAND string's source terminal and drain terminal respectively.
  • the source select transistor SI when the source select transistor SI is turned on, the source terminal is coupled to a source line 34.
  • the drain select transistor S2 is turned on, the drain terminal of the NAND string is coupled to a bit line 36 of the memory array.
  • Each memory transistor 10 in the chain acts as a memory cell. It has a charge storage element 20 to store a given amount of charge so as to represent an intended memory state.
  • a control gate of each memory transistor allows control over read and write operations.
  • the control gates of corresponding memory transistors of a row of NAND string are all connected to the same word line (such as WL0, WL1, ...)
  • a control gate of each of the select transistors SI, S2 (accessed via select lines SGS and SGD respectively) provides control access to the NAND string via its source terminal and drain terminal respectively.
  • flash memory One important difference between flash memory and other type of memory is that a cell must be programmed from the erased state. That is the floating gate must first be emptied of charge. Programming then adds a desired amount of charge back to the floating gate. It does not support removing a portion of the charge from the floating to go from a more programmed state to a lesser one. This means that update data cannot overwrite existing one and must be written to a previous unwritten location.
  • the array of memory cells is divided into a large number of blocks of memory cells.
  • the block is the unit of erase. That is, each block contains the minimum number of memory cells that are erased together.
  • FIG. 3 illustrates schematically an example of a memory array organized in erasable blocks.
  • Programming of charge storage memory devices can only result in adding more charge to its charge storage elements. Therefore, prior to a program operation, existing charge in charge storage element of a memory cell must be removed (or erased).
  • a non- volatile memory such as EEPROM is referred to as a "Flash" EEPROM when an entire array of cells 200, or significant groups of cells of the array, is electrically erased together (i.e., in a flash). Once erased, the group of cells can then be reprogrammed.
  • the group of cells erasable together may consist of one or more addressable erase unit 300.
  • the erase unit or block 300 typically stores one or more pages of data, the page being a minimum unit of programming and reading, although more than one page may be programmed or read in a single operation.
  • Each page typically stores one or more sectors of data, the size of the sector being defined by the host system.
  • An example is a sector of 512 bytes of user data, following a standard established with magnetic disk drives, plus some number of bytes of overhead information about the user data and/or the block in with it is stored.
  • individual memory cells in the memory array 200 are accessible by word lines 42 such as WLO-WLy and bit lines 36 such as BL0 - BLx.
  • the memory is organized into erase blocks, such as erase blocks 0, 1, ... m. If the NAND string 50 (see FIG. 2) contains 16 memory cells, then the first bank of NAND strings in the array will be accessible by select lines 44 and word lines 42 such as WL0 to WL15.
  • the erase block 0 is organized to have all the memory cells of the first bank of NAND strings erased together. In memory architecture, more than one bank of NAND strings may be erased together.
  • FIG. 4 illustrates schematically a memory chip having multiple arrays and operations for maximum parallelism.
  • the memory chip is fabricated with two dies, DIE 1 and DIE 2.
  • Each die contains two memory planes.
  • DIE 1 contains memory plane 1 and memory plane 2
  • DIE 2 contains memory plane 3 and memory plane 4.
  • Each memory plane contains multiple blocks and each block contains multiple pages.
  • memory plane 1 includes Block 1 which in turn includes a page PI .
  • the blocks such as Block 1 - Block 4 are each minimum erase units (MEUs) fixed by the physical architecture of the memory array in a memory plane, such as the block 300 shown in FIG. 3.
  • the pages such as P1-P4 are each minimum Read/Write units fixed by the number read/write circuits that operate in parallel.
  • FIG. 5 illustrates schematically, a memory structure having higher degree of parallelism.
  • pages P1-P4 are linked together as a "metapage", which at the system level, is operated on as a minimum unit of read or write.
  • Blockl - Block 4 are linked together as a "metablock”, which at the system level, is operated on as a minimum erase unit.
  • the physical address space of the flash memory is treated as a set of metablocks, with a metablock being the minimum unit of erasure.
  • metalblock e.g., 300-4 and “block” 300 are used synonymously to define the minimum unit of erasure at the system level for media management, and the term “minimum erase unit” or MEU is used to denote the minimum unit of erasure of flash memory.
  • MEU minimum erase unit
  • metalpage e.g., 60- 4 and “page” 60 are used synonymously with the understanding that a page can be configured into a metapage at the system level with a higher degree of parallelism.
  • FIG. 4 illustrates that higher degree of parallelism can be achieve by aggregating memory structures from multiple planes in a memory chip, it should be understood that in another embodiment, the planes may be distributed among more than one memory chip.
  • an example of nonvolatile memory is formed from an array of field-effect transistors, each having a charge storage layer between its channel region and its control gate.
  • the charge storage layer or unit can store a range of charges, giving rise to a range of threshold voltages for each field-effect transistor.
  • the range of possible threshold voltages spans a threshold window.
  • each resolvable zone is used to represent a different memory states for a memory cell.
  • the multiple memory states can be coded by one or more binary bits.
  • FIG. 6 illustrates a binary memory having a population of cells with each cell being in one of two possible states.
  • Each memory cell has its threshold window partitioned by a single demarcation level into two distinct zones.
  • a read demarcation level rVi between a lower zone and an upper zone, is used to determine to which zone the threshold level of the cell lies.
  • the cell is in an "erased” state if its threshold is located in the lower zone and is in a "programmed” state if its threshold is located in the upper zone.
  • FIG. 6(1) illustrates the memory initially has all its cells in the "erased” state.
  • FIG. 6(2) illustrates some of cells being programmed to the "programmed” state.
  • a 1-bit or binary code is used to code the memory states. For example, the bit value “1” represents the “erased” state and "0" represents the "programmed” state.
  • programming is performed by application of one or more programming voltage pulse. After each pulse, the cell is sensed to verify if the threshold has moved beyond a verify demarcation level vVi.
  • a memory with such memory cell partitioning is referred to as “binary” memory or Single-level Cell (“SLC”) memory. It will be seen that a binary or SLC memory operates with a wide margin of error as the entire threshold window is only occupied by two zones.
  • FIG. 7 illustrates a multi-state memory having a population of cells with each cell being in one of eight possible states.
  • Each memory cell has its threshold window partitioned by at least seven demarcation levels into eight distinct zones.
  • read demarcation levels rVi to rV 7 are used to determine to which zone the threshold level of the cell lies.
  • the cell is in an "erased” state if its threshold is located in the lowest zone and is in one of multiple "programmed” states if its threshold is located in the upper zones.
  • FIG. 7(1) illustrates the memory initially has all its cells in the "erased” state.
  • FIG. 7(2) illustrates some of cells being programmed to the "programmed” state.
  • a 3-bit code having lower, middle and upper bits can be used to represent each of the eight memory states.
  • the "0", “1", “2”, “3”, “4", “5", “6” and “7” states are respectively represented by “111”, “Oi l”, “001”, “101 ', “100", “000”, “010” and ⁇ 10".
  • programming is performed by application of one or more programming voltage pulses. After each pulse, the cell is sensed to verify if the threshold has moved beyond a reference which is one of verify demarcation levels vVi.to vV 7 .
  • a memory with such memory cell partitioning is referred to as "multi-state” memory or Multi-level Cell (“MLC”) memory.
  • MLC Multi-level Cell
  • a memory storing 4-bit code will have lower, first middle, second middle and upper bits, representing each of the sixteen states.
  • the threshold window will be demarcated by at least 15 demarcation levels into sixteen distinct zones.
  • FIG. 8 illustrates an example of a physical memory architecture suitable for practicing the invention.
  • the array of memory cells 200 (see FIG. 1) is partitioned into a first portion 410 and a second portion 420.
  • the second portion 420 has the memory cells configured as high density storage with each cell storing multiple bits of data.
  • the first portion 410 has the memory cells configured as lower density storage with each cell storing less number of bits than that of the second portion.
  • memory cells in the first portion 410 are configured as SLC memory to store 1 bit of data each.
  • Memory cells in the second portion 420 are configured as MLC memory to store 2 bits of data each.
  • the first portion storing 1 bit of data per cell will also be referred as Dl and the second portion storing 2 bit of data per cell as D2.
  • the first portion will operate with more speed, a much wider margin of error and more endurance compared to that of the second portion.
  • a memory partitioned into two portions such as into Dl (1-bit) and D3 (3 -bit) portions is disclosed in United States Application US 12/642,584 filed on December 18, 2009, the entire disclosure of which is incorporated herein by reference.
  • FIG. 9 illustrates schematically the data path between the SLC portion and the MLC portion in a 2-layer data storage system.
  • the first layer is the main input buffer for incoming data and operates on the SLC portion 410 of a NAND memory which is faster/higher-endurance/higher-cost memory compared to the MLC portion 420.
  • the second layer is the main data archive storage and operates on the MLC portion which is slower/lower-endurance/lower-cost memory.
  • FIG. 9 The main operations in such system are labeled in FIG. 9 are as follows:
  • FIG. 10 illustrates in more detail the SLC layer shown in FIG. 9.
  • the typical structure of SLC layer uses multiple blocks, usually one Write/Update block data and one Relocation/Compaction block for data copied during block reclaim (or, they can be combined).
  • the following main rules usually apply:
  • Blocks are linked in the chain according to the order in which they were programmed.
  • the least recently programmed block is selected as the SLC move/folding block, from which data may be moved/folded to the MLC write block.
  • the block with the lowest volume of valid data is selected as the SLC reclaim block, from which valid data is relocated to the SLC relocation block connecting to the head of the chain.
  • An SLC move block or SLC relocation block is added to the SLC empty block list on completion of a data move/folding or block reclaim operation.
  • the two-layer structure can be in fact more than two layer, if there are more types of memory, say RAM, or 3rd type of NVM.
  • each 'memory' layer there might be multiple sub-systems, with different data handling, which also referred to as 'layer'.
  • the prior art systems based on NAND memory usually have the following storage hierarchy.
  • the SLC partition has SLC blocks to implement a Binary Cache and Binary Update blocks.
  • the Binary Cache is used for some or all data. Data is stored in the Binary Cache with fine granularity of 1 or 8 (4KB) sectors. Typically, the Binary Cache is used to cache small and random fragments of a page. It is then evicted to the Binary Update block.
  • the Binary Update blocks map most of the data in units of Logical Group. Each Logical Group has a size that corresponds to the SLC block. So, one Binary block can store up to one Logical Group in which the pages are in sequential order of logical address. This layer does not exist in cluster-based systems, as in those systems all Binary blocks are used as Binary Cache.
  • the MLC partition has MLC blocks for storing the data in higher density than the SLC blocks.
  • data is stored MLC-block by MLC-block.
  • 3 SLC blocks is folded (relocated) to 1 MLC block.
  • very small unit such as 4KB, creates a problem of the data being fragmented, scattered between the blocks so much that maximum parallelism during read and data copy (due to update) is not achievable. Also, amount of copy increases as small update can trigger copy of an entire block(s).
  • the invention has an architecture which addresses the above problems, in particular the undesirable FIFO buffer behavior of SLC blocks which increases write amplification; the fragmentation of data, which reduces parallelism; the high intensity of processing, which requires large RAM and high power; the duplicate capacity budget for data in SLC blocks, which is inefficient and wasteful.
  • a nonvolatile memory is provided with a block management system in which an ordered logical address range from a host is partitioned into logical groups where a block stores multiple logical groups of data.
  • Each logical group is of a size having a range from at least the same order of magnitude to an order of magnitude higher as the size of a host write but at least of a size of a page or metapage which is a unit of read or write of maximum parallelism supported by the memory.
  • the logical group By having the size of the logical group decoupled from that of the erase block, and being of a size more compatible with the size and nature of host writes, the logical group provides the benefit of simplifying addressing and conserving limited system resource while not triggering excessive rewrites which impact performance.
  • FIG. 11 illustrates a page in the memory organization of the block management system according to the present invention.
  • a host writes units of data which are identified by their logical address, LBA (logical block address).
  • the memory operates on a logical page 62 of data in parallel.
  • the page 62 can hold data for a number of LB As.
  • each page holds data from M units of LB As and a page, Page(LPo), may be filled with data from LBAo to LBA M - I .
  • a page is at least a group of cells/data that can be serviced by a corresponding group of read/write circuits in a memory plane.
  • the page is a metapage as described in connection with FIG. 5 to achieve maximum parallelism.
  • the metapage is of size 32kB to 64kB. With a host write cluster of 4kB, a metapage can hold 8 to 16 clusters.
  • FIG. 12 illustrates a logical group in the block management system.
  • a group of pages is tracked as one unit.
  • the logical addressed space of the host system is partitioned into logical groups 350, each group being a subset of the logical address space defined by a range of LBAs or logical page numbers.
  • logical group LGO is constituted from N logical pages with logical page nos. LP 0 to LP N -i and the next logical group LG1 is constituted from N logical pages with logical page nos. LP N to LP 2N -i , etc.
  • a logical group 350 is stored in the memory with its logical page numbers in sequential order so that the pages in it are self-indexed. In this way, addressing for the pages 62 in the logical group is by simply keeping track at the logical group level instead of the page level. However, with updates of pages in a logical group, garbage collection needs to be performed to reclaim space occupied by invalid pages. In prior art systems, the logical group has a size that aligns with the size of an erase block. In this way, garbage collection on an erase block is simply to salvage the valid data of the logical group and rewrite the entire logical group to a new block.
  • FIG. 13A illustrates an erase block accommodating data from multiple logical groups.
  • the size of the logical group 3350 is decoupled from that of the erase block and is not the same size as the erase block.
  • the logical group 350 is down-sized to be more compatible with the size and nature of host writes.
  • a block 310 (which preferable is a metablock) in the SLC portion 410 is able to accommodate data for P number of logical groups.
  • the SLC block stores the following logical groups: LGO, LG1, LG2, LG1 etc where LG1 ' is an updated version of LG1.
  • each logical group is down-sized to a range from at least the same order of magnitude to an order of magnitude higher as the size of a unit of host write but at least of a size of a metapage which is a unit of read or write of maximum parallelism supported by the memory.
  • This will be optimized for data patterns that are frequently updated or non-sequential and not to trigger excessive rewrites.
  • a logical group may have 4 metapages. If the metapage holds 8 to 16 host clusters, then a logical group may hold 32 to 64 clusters.
  • the logical group size may be judicially increased as a tradeoff for the purposed of relieving demand on addressing resource so that the controller chip need not operate with external RAM.
  • FIG. 13B is a flow diagram illustrating the scheme of storing host writes to the non- volatile memory in terms of small logical groups.
  • STEP 500 Organizing the non- volatile memory into blocks of memory cells that are erasable as a unit, each block for storing a plurality of pages, each page for accessing a predetermined number logical unit of data in parallel, each logical unit having a logical address assigned by the host.
  • STEP 510 Defining a plurality of logical groups by partitioning a logical address space of the host into non-overlapping sub-ranges of ordered logical addresses, each logical group having a predetermined size within delimited by a minimum size of at least one page and a maximum size of fitting at least two logical groups in a block.
  • STEP 520 Buffering individual host writes.
  • STEP 530 Staging the individual host writes logical group by logical group.
  • STEP 540 Storing any staged logical groups into the non- volatile memory.
  • the memory is partitioned in SLC and MLC portions and comprises, first, second and third operational and functional layers.
  • the first and second layers operate in the SLC portion.
  • the third layer operates in the MLC portion.
  • the first layer is for initially storing write data from a host and staging the data logical-group by logical-group before relocating each logical group into either the second or third layer.
  • the second layer provides active storage in a pool of SLC blocks for storing host data at the logical-group level. When the pool is full, more room is made by evicting the logical groups with the least potential rewrites to the third layer which stores at a higher density.
  • FIG. 14 illustrates a system architecture for managing the blocks and pages across the different memory partitions according to the present invention.
  • the blocks and pages in the memory arrays are managed by a block management system, which resides as firmware 60 in the memory controller 102 (see FIG. 1).
  • the memory is partitioned into a SLC portion 410 and a MLC portion 420.
  • the block management system implements a first, fragment caching layer 412, a second, logical group sorting layer 414 and a third, cold logical group archiving layer 422. These are operational and functional layers.
  • the first two layers 412 and 414 operate in the SLC portion 410 and the third layer 421 operates in the MLC portion 420.
  • the first, fragment caching layer 412 operates on binary blocks 310 of the SLC portion 410 and is for initially storing data from a host and staging the metapages logical-group by logical-group before relocating each logical group into the MLC portion 420.
  • the staging is to gather the data into entire logical groups. The gathering could be from fragments of a host write or by padding in combination with existing data already stored in the non- volatile memory.
  • the SLC portion 410 includes two structures: a resident binary zone 402 and a binary cache 404.
  • the Binary Cache 404 is storage for mainly short fragments with fine addressing unit (sector), where the data can be moved/evicted to SLC blocks 310 or MLC blocks 320.
  • the resident binary zone 402 is reserved for known frequently updated areas with short updates, typically NTFS or other File System tables data only.
  • the second, logical group sorting layer 414 stores data logical-group by logical-group in a pool of SLC update/storage blocks 310.
  • the writes to this pool come from host writes or from rewrites due to garbage collection. If the host data is mainly of short fragment, it is first cached in the first layer 412 before being evicted from the first layer to the second layer 414. If the host data is less fragmented (medium size), where complete logical group can be had, it is written directly to the second layer 414.
  • the second layer 414 provides a fast SLC storage area where fragmented and medium size host writes land. Unlike prior systems, where there is no second layer and the first layer 412 essentially acts as a FIFO to transit data to the third layer 422 in the MLC portion 420 before the data can be accessed, this second layer 414 maintains a working set of user data in the fast SLC portion 410.
  • a non- volatile memory organized into flash erasable blocks sorts units of data according to a temperature assigned to each unit of data, where a higher temperature indicates a higher probability that the unit of data will suffer subsequent rewrites due to garbage collection operations.
  • the units of data either come from a host write or from a relocation operation.
  • the data are sorted either for storing into different storage portions, such as SLC and MLC, or into different operating streams, depending on their temperatures.
  • the temperature sorting technique is operable in SLC as well as MLC portions. This allows data of similar temperature to be dealt with in a manner appropriate for its temperature in order to minimize rewrites. Examples of a unit of data include a logical group and a block.
  • the memory is partitioned in SLC and MLC portions and comprises, first, second and third operational and functional layers.
  • the first and second layers operate in the SLC portion.
  • the third layer operates in the MLC portion.
  • the first layer is for initially storing write data from a host and staging the data logical-group by logical-group before relocating each logical group into either the second or third layer.
  • the second layer provides active storage in a pool of SLC blocks for storing host data at the logical-group level. When the pool is full, more room is made by evicting the logical groups with the least potential rewrites to the third layer which stores at a higher density.
  • Each logical group in the second layer is ranked by its potential for future rewrites due to garbage collection.
  • a temperature from a finite range is assigned to each logical group with the coldest logical group first to be evicted to the third layer.
  • Ranking criteria include the rate of update the logical group is experiencing and the length of time the logical group is between updates.
  • Logical groups relocated from the second memory layer to the third memory layer will be accessed at the third memory layer.
  • Logical group remaining at the second memory layer will be accessed directly at the second memory layer.
  • FIG. 15 illustrates in more details the second layer shown in FIG. 14.
  • a pool of binary blocks 310 is provided for storing the logical groups. As each block 310 is filled and some of the logical groups in it are updated, the block will need to be garbage-collected. Valid logical groups in the block are relocated to a new block. The logical groups in the pool are sorted according to its 'temperature'.
  • the logical group to be moved to the third layer 422 is selected according to its 'temperature'.
  • the second layer 414 also provides facilities for ranking and sorting the logical groups by how likely they need rewrites.
  • a logical group is considered 'hot' when it contains data that is frequently updated and is from short and random host writes because the logical group will need more rewrites due to more garbage collections.
  • a logical group is considered 'cold' when it contains data that is seldom updated and is long sequential host writes because the logical group will remain relatively static requiring little or no rewrites.
  • One 'temperature' ranking criterion is the rate of update the logical group is experiencing.
  • the sorting and distinguishing of the actively updated and less actively updated logical groups are significant when the first 412 and second 414 layers operate in a SLC memory portion 410 and the third layer 422 operates in the MLC portion 420.
  • the active logical groups in the SLC memory as a working set and only move the inactive ones to the MLC memory, rewrites of the logical group whenever there are updates to it are minimized in the MLC memory. This in turn minimizes the total number of rewrites a logical group will suffer.
  • the third layer 422 stores at a higher density (MLC) the coldest logical groups evicted from the second layer. This process is also referred to as 'folding' SLC data to MLC data.
  • MLC higher density
  • sorting scheme has been described with respect to sorting at the logical group level, it is to be understood that the invention is equally applicable to sorting at the level of other data units, such as sorting at the fragment level or sorting at the block level.
  • US Patent 7633799 discloses usage of different data access pattern criteria such as LRU, hit rate by write and read commands. But, the prior art does not teach specific practical methods of making it work in a data storage system, such as making the choice efficient and at the same time avoid excessive processing, RAM and control update requirements.
  • the approach in the present invention is to aim for minimizing Write Amplification.
  • Write amplification is caused by a future write elsewhere in the system.
  • Write amplification is caused by co-location of active (hot) and inactive (cold) data being mixed in a physical block. Whenever, there is a mixing of hot and cold data in a block, the data in the block will eventually need to be relocated or rewritten to another block. As blocks get larger, it becomes more challenging to keep active and inactive regions co-located.
  • the invention provides a collection of practical methods to sort data in a way to detect the best data to evict/archive to the next layer of storage.
  • the methods mainly use known principles, specifically they are based on analyzing access pattern and history. The focus is on making the data sorting practical.
  • the main methods include:
  • the Temperature value can be stored with the data itself or in a separate table, or alongside with addressing entries.
  • the temperature values themselves can be based on: a) Least Recently Written (by the host) criteria for the data fragments/units; b) Recent Hit (access, e.g., read) rate; c) Data fragment length (the shorter the data is, the more likely it is to be hit soon); d) Number of block compactions copies for the data as an indicator of data age; e) Combination of a) and b) and c), which produces the best results.
  • the temperature sorting is at the logical group level.
  • the coldest logical group will be the first to be evicted from the second layer to the third layer.
  • the criteria for a logical group to be evicted include the following.
  • Time stamps The temperature is determined as a time stamp value of the logical group. A time stamp indicates when the logical group was last written. The longer it was last written, the colder is the temperature. Practically using a limited TS range, very old logical groups beyond a maximum TS value will all be considered to have the same coldest temperature.
  • the advantage of TS is that it has the fastest response to access pattern change. The disadvantage is that it provides no previous history.
  • time stamp is to provide an 11-bit time stamp for each logical group in the binary block pool of the second layer.
  • the temperature is determined as a write count of the logical group.
  • a write count indicates how many times the logical group was written or the frequency of updates. For example, at a new update of the logical group, the write count is incremented.
  • the advantage of write count is that it keeps history information. The disadvantage is that it may make old hot logical groups 'sticky'.
  • FIG. 16 illustrates the 'temperature' sorting of the logical groups for the 'hot' logical group case.
  • LG temperature is a combined function of update frequency and age.
  • the Active Binary Working Set (ABWS) is the pool of SLC blocks in the second layer. It represents the short list of Hot Logical Groups and blocks, where the LGT (Logical Group Temperature) values are being tracked.
  • ABWS Active Binary Working Set
  • Sorting is done on the basis of LGT (Logical Group Temperature) values for the Logical Groups.
  • LGT values are stored for limited number of Logical Groups currently addressed by master index, making Active Binary set.
  • the master index is a table that lists all the logical groups in the SLC pool of the second layer. Each LGT is 3 bit in size and has a range from 0 (coldest) to 7 (hottest).
  • GAT Binary Blocks in Inactive Binary Set and MLC blocks
  • GAT is a lookup table that keeps track of the mapping between logical groups and blocks.
  • FIG. 17 illustrates the 'temperature' sorting of the logical groups for the
  • a logical group residing in the third, MLC layer is updated and returned to the binary pool in second, SLC layer.
  • the given logical group is folded back to the third, MLC layer.
  • the sorting can be performed at the block level. This is an alternative approach if there are too many logical groups in the pool to individually track their temperature. Instead, the temperature is tracked at the block level where all logical groups in a block are treated as if they have the same temperature.
  • the sorting options is this case include the following:
  • Each Binary block has TS same for all logical groups written for the block.
  • Hot-Cold data Binary block sorting (implicit implementation of the Block level TS) - no need to model
  • Each Binary block is listed in the UB info in time allocation order for new data update blocks. Equivalent to TS being the same for all logical groups written for the block.
  • the new block's position in the list is chosen approximately according to the source block locations. In other words, the new block has approximately the same temperature as the source block.
  • units of data are sorted according to their temperatures into different block streams such that the blocks in each operating stream only involves data of similar temperature.
  • the goal is to separate hot data from cold data as soon as possible and at every opportunity.
  • the hot data and cold data have different obsolescence and garbage collection/relocation schedules. For example, hot data will become obsolete faster and require more frequent garbage collection/rewrites. When the cold data are not mixed in with the hot data, it will not incur unnecessary rewrites. Most likely, the hot data will obsolete itself without triggering relocation of cold data from one block to another block, and the cold data in cold blocks will stay there without compactions/relocations due to the hot data.
  • FIG. 18 illustrates how different types of writes are sorted into block streams according to their perceived temperature interactively. The sorting applies to the source at the second layer with incoming data and also applies to data moved by compaction to separate hot/cold blocks.
  • the stream is deemed a series of long sequential writes and is directed to be folded to the MLC portion either directly or via the binary block pool.
  • the stream is in a by-pass mode as soon as it is identified. The head of the sequential stream marooned in a cold or even hot block will eventually be relocated.
  • the different data streams described above can be created by a user and therefore come from a user logical partition. Some of the write streams in the partition may also be created from relocation operations.
  • Partitions In general, different logical partitions such as user partition, OS (operating system) partition and 'sticky' binary partition may be maintained, each with its own mix of different type of data streams, some with predetermined temperature.
  • OS partition operating system
  • the system data are known to be fragmented and fast changing, so there is not even the need to determine the temperature. It is simply assigned a hot temperature and stored in the hot blocks.
  • 'sticky' partition where the data there are meant to stay in the binary SLC portion. Thus its data stream is always 'hot' and is stored in the hot blocks.
  • Blocks and logical groups are subject to sorting by LGT without partition boundaries. That means that it is not necessary to budget a number of Closed blocks per partition, and the blocks are distributed on demand. For example, if the OS partition is active and the user partition is not, then up to all Closed update blocks can be allocated to the OS partition as all user partition's logical groups will be sorted to cold state and folded to the MLC portion.
  • Writes from a steam may be stored into multiple blocks. Every time a first logical group is partially written in a first block and is followed by a write of a different, second logical group, the second logical group is written to a second block in the hope that subsequent writes will furnish the incomplete data to complete the first logical group. This will reduce fragmentation. Up to a predetermined number of update blocks can be opened contemporaneously for this purpose. Beyond that, the incomplete logical group is made complete by padding the incomplete data.
  • FIG. 19 is a flow diagram illustrating the scheme of temperature sorting for memory storage and operations.
  • STEP 600 Organizing the non- volatile memory into blocks of memory cells that are erasable together.
  • STEP 610 Ranking each unit of data by assigning a temperature, where a higher temperature indicates a higher probability that the unit of data will suffer subsequent rewrites due to garbage collection operations.
  • STEP 620 Performing an operation on the unit of data in a manner dependent on the temperature of the unit of data.
  • STEP 630 Done.
  • FIG. 20 is a flow diagram illustrating the scheme of temperature sorting at the logical group level.
  • STEP 700 Organizing the non- volatile memory into blocks of memory cells that are erasable together.
  • STEP 710 Partitioning the non-volatile memory into a SLC portion and an MLC portion, where memory cells in the SLC portion each stores one bit of data and memory cells in the MLC portion each stores more than one bit of data.
  • STEP 720 Providing a plurality of logical groups by partitioning a logical address space of the host into non-overlapping sub-ranges of ordered logical addresses, the logical groups having a size that multiple logical groups fit in a block.
  • STEP 730 Storing data logical group by logical group in each block of the SLC portion.
  • STEP 740 Ranking each logical group stored in the SLC portion by a temperature, where a higher temperature indicates a higher probability the logical group will suffer subsequent rewrites due to garbage collection operations.
  • STEP 750 In response to a demand to free up room in the SLC portion, preferentially relocating a logical group with the coldest temperature from the SLC portion to the MLC portion.
  • FIG. 21 is a flow diagram illustrating the scheme of temperature sorting at the block level.
  • STEP 800 Organizing the non- volatile memory into blocks of memory cells that are erasable together.
  • STEP 810 Partitioning the non- volatile memory into a SLC portion and an MLC portion, where memory cells in the SLC portion each stores one bit of data and memory cells in the MLC portion each stores more than one bit of data.
  • STEP 820 Ranking each block in the SLC portion by a temperature, where a higher temperature indicates a higher probability the block will suffer subsequent rewrites due to garbage collection operations.
  • STEP 830 In response to a demand to free up room in the SLC portion, preferentially relocating data in a block with the coldest temperature from the SLC portion to the MLC portion.
  • STEP 840 Done.

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Abstract

Une mémoire rémanente organisée en blocs effaçables flash reçoit des données d'écritures d'hôte d'abord par l'organisation en groupes logiques avant l'écriture dans les blocs. Chaque groupe logique contient des données provenant d'un ensemble prédéfini d'adresses logiques ordonnées et possède une taille fixe inférieure à celle d'un bloc. La totalité des groupes logiques est obtenue par partitionnement d'un espace d'adresses logiques de l'hôte en sous-gammes non chevauchantes d'adresses logiques ordonnées, chaque groupe logique possédant une taille prédéterminée dans une gamme délimitée par une taille minimum d'au moins une page et une taille maximum d'insertion d'au moins deux groupes logiques dans un bloc et jusqu'à un ordre de magnitude supérieur à une taille classique d'une écriture d'hôte. Ainsi, la collecte de données inexactes en excès due à l'exploitation d'un grand groupe logique est évitée alors que l'espace d'adresses est réduit pour minimiser la taille d'une RAM d'antémémorisation.
EP12722632.2A 2011-05-17 2012-05-11 Mémoire rémanente et méthode avec des petits groupes logiques répartis entre des partitions de mémoire slc et mlc actives Withdrawn EP2710475A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201161487234P 2011-05-17 2011-05-17
US13/468,720 US20120297121A1 (en) 2011-05-17 2012-05-10 Non-Volatile Memory and Method with Small Logical Groups Distributed Among Active SLC and MLC Memory Partitions
PCT/US2012/037511 WO2012158514A1 (fr) 2011-05-17 2012-05-11 Mémoire rémanente et méthode avec des petits groupes logiques répartis entre des partitions de mémoire slc et mlc actives

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