Classifications

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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
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  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
  • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
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  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
  • H10W20/211—Through-semiconductor vias, e.g. TSVs
  • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
  • H10W20/2125—Top-view shapes
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  • H10W90/00—Package configurations
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
  • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
  • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
  • H05K3/341—Surface mounted components
  • H05K3/3431—Leadless components
  • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/01—Manufacture or treatment
  • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
  • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
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  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/099—Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
  • H10W72/01231—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition
  • H10W72/01233—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating
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  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/072—Connecting or disconnecting of bump connectors
  • H10W72/07231—Techniques
  • H10W72/07236—Soldering or alloying
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  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/073—Connecting or disconnecting of die-attach connectors
• • H—ELECTRICITY
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/221—Structures or relative sizes
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  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/231—Shapes
  • H10W72/232—Plan-view shape, i.e. in top view
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  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/241—Dispositions, e.g. layouts
  • H10W72/247—Dispositions of multiple bumps
  • H10W72/248—Top-view layouts, e.g. mirror arrays
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/251—Materials
  • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
• • H—ELECTRICITY
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/281—Auxiliary members
  • H10W72/283—Reinforcing structures, e.g. bump collars
• • H—ELECTRICITY
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/29—Bond pads specially adapted therefor
• • H—ELECTRICITY
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/941—Dispositions of bond pads
  • H10W72/944—Dispositions of multiple bond pads
• • H—ELECTRICITY
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/20—Configurations of stacked chips
  • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
• • H—ELECTRICITY
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
  • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
• • H—ELECTRICITY
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
  • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
• • H—ELECTRICITY
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W99/00—Subject matter not provided for in other groups of this subclass

Definitions

• the present invention relates to an integrated circuit according to the preamble of claim 1 and to a method for producing an electrical feedthrough according to the preamble of claim 8.
• Such an integrated circuit and such Ver ⁇ drive for producing an electrical feedthrough are known for example from DE 10 2006 035 864 AI.
• a micro-electronic integrated circuit formed by stacking a plurality of, in each case a microelectronic functionalized region having substrates is formed, wherein (at least) one of these Substra ⁇ te with (at least) is provided an electrical through-contact to signal or power connection paths of to allow a substrate to another substrate of Substratsta ⁇ pels or out of the integrated circuit out.
• electrical plated- through tierept here are provided, which are each formed as a first surface of a substrate to an opposite second substrate surface by the respective substrate through ver ⁇ current and consistently filled with an electrically conductive material through holes.
• DE 10 2006 035 864 AI of such holes is regarding a "aspect ratio" in a substrate, thus noted the relationship between hole depth and hole width (Loch twistmes ⁇ ser), that this is in a range of 2 to 10, but typically greater than 3 is.
• the through hole has at least one step, at which a transition from a smaller hole cross-section on the part of the first surface to a larger hole cross-section takes place on the part of the second surface.
• the basic idea of the invention is to form a through-hole with a hole cross-section which, viewed over the hole length, varies in such a way that in favor of a technolo- cally less problematic filling process although a larger hole cross-section is provided, the maximum time of one gradation in the range, however, merges Wenig ⁇ favor of a reduction in the space requirement in the functionalized substrate region in egg nen smaller hole cross-section.
• the invention thus makes it possible to provide an electrical feedthrough with a small space requirement (in the relevant area) and nevertheless of outstanding quality and reliability with respect to both the production process and the subsequent function.
• the key for the later function continuous replenishment of the through ⁇ hole with the electrically conductive material "from ei ⁇ nem cast", ie continuous over the entire hole length be- see the two substrate surfaces in question with great process reliability.
• the through-hole may have one or more such cross-sectional varying gradations, wherein at each step, a very abrupt change in cross-section may be preferentially effected (eg over a transitional area considered in the longitudinal direction of the hole of less than 10% of the total hole length).
• the terms "small hole cross section” and “larger hole ⁇ cross section” here refer to the difference of the hole cross-sections on both sides of the respective gradation.
• first "passivated fourth ⁇ " ie is provided with an electrical insulation during or after the production of the through hole before the electrically conductive material is introduced.
• the passivation may be formed by a silicon oxide film.
• the through hole preferably has a circular hole cross section.
• the following are with regard to a given such circular hole cross section preferred dimensioning ⁇ ments or sizing rules. It is understood that this also appropriate dimensioning and dimensioning rules concerning the corresponding hole cross sections (surfaces) are disclosed, which are read along with the after ⁇ following information, respectively (and also be applied to non-circular hole cross sections Kgs ⁇ NEN).
• a diameter of the smaller hole cross-section is smaller than 20 ⁇ m, in particular smaller than 10 ⁇ m.
• Diameter preferably at least 1 ⁇ or at least 2 ⁇ , for example, about 5 ⁇ .
• the height of the functionalized region can be in the range of 1 ⁇ to 20 ⁇ ⁇ example. If the functionalized area on its lateral extent be ⁇ seek has an uneven height, so the term "amount of the functionalized portion" refers to that amount which is in the immediate order ⁇ nosti the respective mouth of the through hole.
• the diameter of the smaller hole cross-section and the larger hole cross-section of at least a factor 2, preferably by at least a factor of 5 min ⁇ differ.
• a diameter of the larger hole cross-section is greater than 30 .mu.m, in particular greater than 60 .mu.m. On the other hand, this diameter is preferably less than 200 ⁇ , for example, about 100 ⁇ .
• the through hole can also have more than ei ⁇ ne gradation at which the hole cross section or hole diameter changes. If more than one gradation is provided, then the statements given above concerning the "smaller hole cross-section" refer to the hole cross-section reaching directly to the first substrate surface, that is to say the "very smallest hole cross-section” in this multistage design. In contrast, in this case, the "larger hole cross-section” designates the hole cross-section which directly reaches the second surface, that is, to a certain extent, the "largest hole cross-section” in the multi-stage design.
• the distance of the gradation from the first surface is smaller than the distance of the gradation from the second surface, preferably by at least a factor 2.
• the spacing of the gradation from the first surface is 150% to 300% of the height of the functionalized area. If the altitude is varying, this figure refers back to the height in the area of the relevant mouth of the through-hole.
• the thickness of the substrate in which the through hole is formed may be, for example, in the range of 50 ⁇ to 500 ⁇ .
• the space requirement in particular the space requirement in the functionalized area
• the reliability of the electrical feedthrough can be optimized to a large extent.
• the substrate for this purpose is only accessible from the second surface. is working, so z.
• This processing of the substrate by the two ⁇ th surface thereof can be carried out in several (quer4.000sverkleinernden) stages.
• hole sections produced on the one hand by the second surface and on the other hand by the first surface are added to the desired through hole.
• the continuous filling of the through hole with the electrically conductive material is preferably carried out by means of egg ⁇ nes liquid-filling method, for. B. with a molten solder material.
• known per se Lot ⁇ materials eg. As "Solder Alloys”
• passivation of the substrate surfaces exposed after the formation of the through-hole takes place before the electrically conductive material is introduced.
• a liquid filling method according to a "one shot one material” method e.g. B. by submerging the substrate in a bath of the liquefied electrically conductive material, the cavity formed by the through hole with high process reliability can be almost completely filled with the conductive material.
• the filled in the through-hole conductive material on at least ei ⁇ ner of the two substrate surfaces forms a contact, for example, so-called "solder balls-contacting" from.
• the continuous replenishment of the through hole as well as the formation of a contact to the first and / or second substrate surface can advantageously take place in a single Pro ⁇ zessön.
• a contact surface wettable by the conductive material is provided on the first surface and annularly surrounds the mouth of the through hole on the first substrate surface.
• the portion of the conductive material which wets such a contact surface can also be a contact to a surface of an immediately adjacent further substrate of the relevant integrated circuit, for example to another substrate which is stacked to form the integrated circuit with the first-mentioned substrate.
• an embodiment is particularly advantageous, in which the mouth of the through-hole surrounding the second surface has a ring projecting from the second surface and filled with the conductive material to an extent is such that the conductive material protrudes from the distal end of the ring.
• the ring can z. B. are made of a polymer material.
• the height of the inside diameter and the wall thickness of the ring can be determined according to at ⁇ case of use and reliability requirements. Suitable dimensions for many applications are, for example, a height of 30 ⁇ m to 100 ⁇ m, while For example, about 40 ⁇ , an inner diameter in the range of 30 ⁇ to 200 ⁇ , for example, about 50 ⁇ , and a Wan ⁇ strength in the range of 20 ⁇ to 200 ⁇ , for example, about 50 ⁇ .
• a wall thickness of at least 10% of the inner diameter and / or at most 100% of the inner diameter is advantageous.
• a ring made of plastic material can, for example, be carried out so that the substrate surface in question is first provided with a plastic film or coating over its full area and then using photolithographic methods (eg using photoresist) over a large area denudation (z. B. etching) of the plastic material, whereby le ⁇ diglich the material in question is allowed to stand at the respectively desired locations of the rings.
• plastic material eg polymer
• the ring (z. B. Polymer) may advantageously result in a Stability capitalization of the ring from the end projecting material part (z. B. "Solder Ball”) in the plane and thus to the raised stabili ⁇ hung reliability.
• the ring can reduce a shearing action between soldered substrate and substrate (eg, other substrate or "circuit carrier" in a substrate stack), which can arise under thermal stress due to different linear expansions of the joining partners.
• End face and optionally additionally on its outer peripheral surface have a wettable with the respective filler wettable coating ⁇ .
• Such coatings can, for. B. using photolithographic methods or the like can be realized.
• ring is to be understood here very broadly, for example as an annularly closed elevation on the relevant substrate surface in the region of the mouth of a relevant through-hole.
• the ring may also have a non-circular outer periphery in particular.
• the integrated circuit comprises a plurality of stacked and arranged electrically to each other kon ⁇ lactated substrates, wherein at least one of said substrates with at least one electrical through connection is provided as described above.
• a circuit can be composed of three stacked substrates übereinan ⁇ .
• a bottom substrate may, for. B. act as a circuit carrier, in which at the top conductor tracks and wettable (eg., Metallic) contact surfaces are provided, via which the electrical connection with the substrate arranged above it (middle substrate in the stack) is produced.
• the middle substrate can be z. B. have multiple electrical contacts of the type already described above, z. B.
• the vias may be connected to the top of this substrate and to a functionalized region (microelectronic
• Circuit arrangement lead and / or turn on this substrate top side electrical contacts for electrical connection of the third, the substrate stack uppermost substrate.
• the uppermost substrate may thus in turn have electrical feedthroughs, which connect the underside thereof with the upper side, wherein z. B. at the top (alternatively or in addition, bottom) of the top substrate again a functionalized area can be provided.
• the electrical feedthroughs of the central substrate and the upper substrate may, for. B. at least partially coaxial to each other, so that form in this case electrical vias from the bottom of the middle substrate to the top of the obe ⁇ ren substrate.
• An inventive method for producing an electrical plated-through hole in a substrate for an integrated circuit comprising the steps of: - forming a second from a first substrate surface to be ei ⁇ ner opposing substrate surface through the substrate extending through hole (preferably with subsequent passivation of the hole inner surface), wherein the through hole is formed with at least one gradation, where a transition from a smaller hole cross-section of the part of the first substrate surface to a RESIZE ⁇ ßeren hole cross-sectional part of the second substrate surface,
• the formation of the through hole can be carried out by an etching process, wherein the substrate of etched at ⁇ the substrate surfaces her will so that the hole step is formed (with differing ⁇ chen hole cross-sections) at the point at which gene the two (coaxial) Operaharm- particular "clash".
• a complete, continuous Auf ⁇ fill can be done without material transitions with a (single) electrically conductive material between the two substrate surfaces. This is preferred with a liquid filling method of the kind already explained above.
• Fig. 1 shows the production of an electrical through-contact to a substrate of an integrated circuit according to a first Principalsbei ⁇ play
• 2 shows such a method according to another exemplary embodiment
• FIG. 3 is an illustration for illustrating a modified embodiment of an electrical connection element of the electrical feedthrough, with respect to the example of FIG. 1;
• FIG. 5 shows the arrangement of the substrate stack of FIG. 4 on a further, acting as a circuit carrier
• FIGS. 1 a to 1 c illustrate the manufacture of an integrated circuit 1 comprising a stacked arrangement of a first substrate 10 and a second substrate 20.
• the substrates 10, 20 form a first (upper) substrate (10) and a second (lower) substrate ⁇ strat (20) of the substrate stack.
• the substrate 10 has a (top) first surface 11 and an opposite (lower) second surface 12.
• the substrate 20 has a (top) first surface 21 and an opposite (lower) second surface 22.
• a material for the substrates 10, 20 can z. B. silicon may be provided.
• the lower substrate 20 le ⁇ diglich a circuit substrate or a circuit board is thus used mainly for electrical "wiring" of the arranged thereon substrate 10 and the creation of ways for external contacting of the integrated circuit 1.
• the substrate 20 z. B. also be made of a ceramic material or epoxy resin or other electrically insulating materials, but at least at its top electrically conductive area such as metallic conductor tracks or contact surfaces are provided.
• These functionalized regions 13 and 23, also referred to as functional regions include, but are be ⁇ known per se essential electrical or electronic com- ponents of the integrated circuit 1, whereas deeper in the interior of the substrate regions ( "bulk") primarily or as electrical insulation Support for the functional areas 13, 23 serve.
• the functional area 13 of the first substrate 10 may, in particular differently doped regions, passivation (z. B. from oxides or nitrides include (z. B. S1O 2) or Metalli ⁇ stechniken to each of desired electronic components (eg., Transistors to provide etc.) and their electrical connections diodes, resistors (z. B. in CMOS technology or other suitable technology. fabricated) As part of the functional area 13 in the fi gures ⁇ a contact surface 14 (z. B. metallized area ).
• the functional region 23 of the second substrate 20 essentially comprises conductor tracks which lead to different contact surfaces or such contact surfaces. connect with each other. Plotted in Fig. Lc is such a contact surface 24 (metal layer). 25 denotes a so-called solder stop layer.
• the individual functional areas of the integrated circuit 1 formed from a plurality of substrates are connected to one another via one or more electrical feedthroughs.
• a via 40 is shown as an example, which provides an electrical connection between the contact surface 14 of the first substrate 10 and the con ⁇ tact surface 24 of the second substrate 20.
• a special feature of the via 40 is that the through hole 42 has a step 46, at which a transition from a smaller hole diameter dl from the first surface 11 to a larger hole cross section d2 takes place from the second surface 12.
• a step 46 at which a transition from a smaller hole diameter dl from the first surface 11 to a larger hole cross section d2 takes place from the second surface 12.
• the procedure was as follows: First, the first sub ⁇ strat as shown in Figure la, 10. (Here, the semiconductor substrate such as silicon.) Machining ⁇ tet order on the upper surface (first surface 11) of the functional area 13 and through the substrate 10 extending therethrough to form the through hole 42. This may advantageous in known processes of the semiconductor industry Retired ⁇ attacked (such. As CMOS technology).
• the through hole 42 may, for. B.
• the gradation 46 viewed in the vertical direction, is relatively scarce (eg less than 10 ⁇ m, in particular less than 5 ⁇ m) below the functional area 13.
• an annular elevation here a ring 50 arranged of polymer material whose inner cross section corresponds approximately to the hole cross section at this point.
• the through hole 42 fully ⁇ constantly and homogeneously filled with the electrically conductive material (Lot 44), wherein at the substrate top, the metallic contact surface 14 has been wetted and at the substrate ⁇ bottom
• the electrically conductive material Lit 44
• the ring 50 serves to a certain extent as a limiting ring for the lateral delimitation of the solder 44 protruding at the lower mouth of the through-hole 42 and together with this solder 44 forms an advantageous electrical "connection element" for contacting the through-connection 40 with another substrate or circuit carrier.
• the ring 50 (or another purpose serving annular closed survey) was z. B. formed by a photolithographic process on the second surface 12 of the substrate 10.
• the second substrate 20 is then attached to the first substrate 10 in such a way that electrical contacting of the plated through-hole 40 takes place at the metallic contact surface 24 of the functional region 23 of the second substrate 20.
• This preferably under a suitably elevated temperature, so that the proportion of the solder 44 protruding from the ring 50 in this case wets the contact surface 24 well.
• the substrate 10 may in practice be provided with a plurality of plated-through holes of the type shown, which are e.g. B.
• the second substrate functioning as a circuit carrier could be 20, for example, a plurality of (side by side) arranged thereon first substrates (such as the illustrated substrate 10) wear.
• the through-connection 40 it is advantageously possible to construct geometrically space-saving multifunctional systems in which a plurality of substrates can be combined not only laterally but alternatively or additionally also vertically stacked to form an integrated circuit.
• a particularly small hole cross section or hole ⁇ diameter is provided saves valuable surface Be ⁇ area of the functionalized region, said ground up of the larger Hole cross section in the interior of the Substra ⁇ tes nevertheless a continuous filling of the through hole with high quality (especially without inclusions) well ge ⁇ ling.
• the through-connection 40 is to divide the through-connection 40 into three regions which have special features specially adapted to the respective functionality:
• the through-hole 42 has a relatively small diameter, so that a high efficiency of the area utilization in the area of the first surface 11 results.
• a relatively large hole cross-section is provided which, unlike the illustrated embodiment, could also increase in multiple stages to the second surface 12. This results in a smoother filling as well as advantageously a high electrical conductivity.
• a stepped through-hole 40 is provided in the illustrated example, which is integrated together with the electrical connection element ("solder bump") to form a continuous and homogeneous electrical conductor without "interfaces".
• the mechanical support of the Lotanteiles used for contacting by the Begrenzungsring 50 extends the functionality of the via 40 considerably.
• the invention thus allows advantageous stacking of multiple substrates with a "3D contacting".
• FIGS. 2a to 2c show, in Figs. La to lc representation corresponding to a modifiedskysbei ⁇ game.
• a polymer ring 50a arranged on the underside of a first substrate 10a is provided with a wettable coating 52a which, in the example shown, also extends over the entire lateral surface starting from the distal end face of the ring 50a of the ring 50a.
• solder material protrudes on the underside of a first substrate or the limiting ring formed there.
• this solder supernatant has a crowned shape, for which the aforementioned coating of a wettable material (metal coating 52a) is advantageous in the case of a non-wettable ring material (eg polymer).
• the subfigures 3a to 3c represent various stages of the filling process.
• Fig. 3a shows the still unfilled state.
• a special feature of the ring 50b is that this starting from a substantially cylindrical central Kavi- ty star-shaped outwardly projecting bulges 54b, which function as solder reservoir having the subsequently inserted ⁇ brought Lot 44b.
• a certain amount of the solder 44 b can be introduced into these bulges 54 b, in particular if, for example, B. due to the lack of wettability of the ring material no protrusion of the solder 44 b is formed at the distal end of the ring 50 b. This situation is shown in Fig. 3b.
• FIGS. 4a to 4c show a further embodiment of the production of an integrated circuit 1c (FIG. 4c).
• FIG. 4a are first separately provided two sub strate ⁇ 10c and 30c and provided at least in part with through holes 42c of the already described above.
• the substrate 10c shown in FIG. 4a corresponds in its execution to the example shown in FIG. 2a and already explained.
• two variants were drawn simultaneously in FIG. 4a, namely in the left part of the figure with the functional area 33c facing the first substrate 10c and in the right part of the figure with the functional area 33c facing away from this substrate 10c.
• First and second surfaces of the substrate 30c are designated 31c and 32c, respectively.
• the two substrates 10c and 30c are then positioned in a stacked relationship to one another.
• the substrate 30c is hereby stacked on the (upper) first surface 11c of the first substrate 10c.
• Fig. 4b illustrated substrate stack a liquid-filling process is then subjected, for example, as above be ⁇ already described (melted by immersing the substrate stack in a bath of solder) to the through-holes 42c, and the second to the (lower) surface 12c of the substrate
• FIG. 4c there are various possibilities with regard to the electrical connections which are created by the plated-through holes 40c.
• 4c leftmost drawing ⁇ is designated via 40c is for the in Fig.
• an electric contact with contact surfaces of both the substrate 10c and the substrate 30c is provided.
• the right adjacent in the figure via 40c only a contact with a contact surface in the function area 13c of the substrate 10c provide ge ⁇ at the upper end. From the right part of Fig. 4c are more

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• 2011
  • 2011-03-23 DE DE102011005978A patent/DE102011005978A1/de not_active Withdrawn
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  • 2012-03-07 US US14/006,913 patent/US20140084428A1/en not_active Abandoned
  • 2012-03-07 EP EP12709304.5A patent/EP2668664A1/de not_active Withdrawn

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