EP2658113A3 - Mehrschichtige Leiterplatte zur Motorsteuerung - Google Patents

Mehrschichtige Leiterplatte zur Motorsteuerung Download PDF

Info

Publication number
EP2658113A3
EP2658113A3 EP13164682.0A EP13164682A EP2658113A3 EP 2658113 A3 EP2658113 A3 EP 2658113A3 EP 13164682 A EP13164682 A EP 13164682A EP 2658113 A3 EP2658113 A3 EP 2658113A3
Authority
EP
European Patent Office
Prior art keywords
motor control
circuit board
multilayer circuit
conductor layers
control multilayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP13164682.0A
Other languages
English (en)
French (fr)
Other versions
EP2658113A2 (de
Inventor
Nobuhiro Uchida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JTEKT Corp
Original Assignee
JTEKT Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by JTEKT Corp filed Critical JTEKT Corp
Publication of EP2658113A2 publication Critical patent/EP2658113A2/de
Publication of EP2658113A3 publication Critical patent/EP2658113A3/de
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49568Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02PCONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P6/00Arrangements for controlling synchronous motors or other dynamo-electric motors using electronic commutation dependent on the rotor position; Electronic commutators therefor
    • H02P6/08Arrangements for controlling the speed or torque of a single motor
    • H02P6/085Arrangements for controlling the speed or torque of a single motor in a bridge configuration
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0618Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0201Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203Cooling of mounted components
    • H05K1/0209External configuration of printed circuit board adapted for heat dissipation, e.g. lay-out of conductors, coatings
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/4617Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar single-sided circuit boards

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Inverter Devices (AREA)
  • Structure Of Printed Boards (AREA)
EP13164682.0A 2012-04-23 2013-04-22 Mehrschichtige Leiterplatte zur Motorsteuerung Withdrawn EP2658113A3 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012097910A JP2013225622A (ja) 2012-04-23 2012-04-23 モーター制御用多層回路基板

Publications (2)

Publication Number Publication Date
EP2658113A2 EP2658113A2 (de) 2013-10-30
EP2658113A3 true EP2658113A3 (de) 2015-01-07

Family

ID=48182749

Family Applications (1)

Application Number Title Priority Date Filing Date
EP13164682.0A Withdrawn EP2658113A3 (de) 2012-04-23 2013-04-22 Mehrschichtige Leiterplatte zur Motorsteuerung

Country Status (4)

Country Link
US (1) US8994120B2 (de)
EP (1) EP2658113A3 (de)
JP (1) JP2013225622A (de)
CN (1) CN103379730A (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6271265B2 (ja) * 2014-01-24 2018-01-31 日本電産サンキョー株式会社 モータ駆動装置
CN104392980B (zh) * 2014-11-27 2019-02-15 深圳先进技术研究院 一种芯片封装结构
CN105576997B (zh) * 2016-02-04 2019-06-07 中国第一汽车股份有限公司 一种车用集成电机的逆变器总成
WO2023179845A1 (en) * 2022-03-22 2023-09-28 Huawei Digital Power Technologies Co., Ltd. Semiconductor power entity and method for producing such entity by hybrid bonding

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007036045A1 (de) * 2007-08-01 2009-02-05 Siemens Ag Elektronischer Baustein mit zumindest einem Bauelement, insbesondere einem Halbleiterbauelement, und Verfahren zu dessen Herstellung
US20090189291A1 (en) * 2008-01-24 2009-07-30 Infineon Technologies Ag Multi-chip module
DE102008040906A1 (de) * 2008-07-31 2010-02-04 Robert Bosch Gmbh Leiterplatine mit elektronischem Bauelement
US20110108971A1 (en) * 2009-11-10 2011-05-12 Infineon Technologies Ag Laminate electronic device
WO2011083578A1 (ja) * 2010-01-08 2011-07-14 トヨタ自動車株式会社 半導体モジュール
EP2391192A1 (de) * 2010-05-26 2011-11-30 Jtekt Corporation Mehrschichtiges Leitungssubstrat

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4039202B2 (ja) * 2002-10-16 2008-01-30 日産自動車株式会社 積層型半導体装置およびその組み立て方法
WO2005086978A2 (en) * 2004-03-11 2005-09-22 International Rectifier Corporation Embedded power management control circuit
JP4283753B2 (ja) * 2004-10-26 2009-06-24 パナソニックエレクトロニックデバイス山梨株式会社 電気部品内蔵多層プリント配線板及びその製造方法
JP2006165175A (ja) * 2004-12-06 2006-06-22 Alps Electric Co Ltd 回路部品モジュールおよび電子回路装置並びに回路部品モジュールの製造方法
CN100459083C (zh) * 2006-03-15 2009-02-04 日月光半导体制造股份有限公司 内埋元件的基板制造方法
JP2011083063A (ja) 2009-10-02 2011-04-21 Mitsuba Corp 駆動制御装置、およびモータユニット
JP5273095B2 (ja) * 2010-05-24 2013-08-28 株式会社デンソー 半導体装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007036045A1 (de) * 2007-08-01 2009-02-05 Siemens Ag Elektronischer Baustein mit zumindest einem Bauelement, insbesondere einem Halbleiterbauelement, und Verfahren zu dessen Herstellung
US20090189291A1 (en) * 2008-01-24 2009-07-30 Infineon Technologies Ag Multi-chip module
DE102008040906A1 (de) * 2008-07-31 2010-02-04 Robert Bosch Gmbh Leiterplatine mit elektronischem Bauelement
US20110108971A1 (en) * 2009-11-10 2011-05-12 Infineon Technologies Ag Laminate electronic device
WO2011083578A1 (ja) * 2010-01-08 2011-07-14 トヨタ自動車株式会社 半導体モジュール
US20120250253A1 (en) * 2010-01-08 2012-10-04 Toyota Jidosha Kabushiki Kaisha Semiconductor module
EP2391192A1 (de) * 2010-05-26 2011-11-30 Jtekt Corporation Mehrschichtiges Leitungssubstrat

Also Published As

Publication number Publication date
US20130277761A1 (en) 2013-10-24
CN103379730A (zh) 2013-10-30
US8994120B2 (en) 2015-03-31
EP2658113A2 (de) 2013-10-30
JP2013225622A (ja) 2013-10-31

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