EP2624448A1 - Amplificateur de faible bruit - Google Patents

Amplificateur de faible bruit Download PDF

Info

Publication number
EP2624448A1
EP2624448A1 EP20120153472 EP12153472A EP2624448A1 EP 2624448 A1 EP2624448 A1 EP 2624448A1 EP 20120153472 EP20120153472 EP 20120153472 EP 12153472 A EP12153472 A EP 12153472A EP 2624448 A1 EP2624448 A1 EP 2624448A1
Authority
EP
European Patent Office
Prior art keywords
terminal
circuit
lna
input
lna circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP20120153472
Other languages
German (de)
English (en)
Other versions
EP2624448B1 (fr
Inventor
Sven Mattisson
Stefan Andersson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to ES12153472.1T priority Critical patent/ES2551883T3/es
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Priority to EP15171109.0A priority patent/EP2947769B1/fr
Priority to EP12153472.1A priority patent/EP2624448B1/fr
Priority to DK12153472.1T priority patent/DK2624448T3/en
Priority to IN5942DEN2014 priority patent/IN2014DN05942A/en
Priority to AU2013214368A priority patent/AU2013214368B2/en
Priority to US14/375,127 priority patent/US9312818B2/en
Priority to PCT/EP2013/051492 priority patent/WO2013113636A2/fr
Priority to MYPI2014701907A priority patent/MY170838A/en
Publication of EP2624448A1 publication Critical patent/EP2624448A1/fr
Application granted granted Critical
Publication of EP2624448B1 publication Critical patent/EP2624448B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/34—Negative-feedback-circuit arrangements with or without positive feedback
    • H03F1/342—Negative-feedback-circuit arrangements with or without positive feedback in field-effect transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/181—Low-frequency amplifiers, e.g. audio preamplifiers
    • H03F3/183—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only
    • H03F3/185—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/129—Indexing scheme relating to amplifiers there being a feedback over the complete amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/384—Amplifier without output filter, i.e. directly connected to the load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/75—Indexing scheme relating to amplifiers the amplifier stage being a common source configuration MOSFET

Definitions

  • the present invention relates to the field of low-noise amplifiers for receivers, such as radio receivers.
  • LNA low-noise amplifier
  • resistive shunt or inductive series degeneration.
  • the input resistance (Rin) is set by the voltage gain of the circuit and the resistance Rf Assuming the load is dominated by RL, the transconductance is set by Q1, and the open-loop input impedance is high, then we get Rin ⁇ Rf/(1 + gm1 ⁇ RL), where gm1 is the transconductance of Q1.
  • a typical value for Rf is about 500 ⁇ .
  • the common base transistor Q2 isolates the load resistor from Q1 to increase the voltage gain
  • the emitter follower Q3 isolates Rf from RL to minimize loading
  • Such a combination of a common-emitter and a common-base stage is called a cascode, and is a common way to improve the gain and reverse isolation of a single common-emitter stage.
  • Cascodes can be formed of any combination of MOS, BJT and MESFET transistors, including mixed types.
  • a drawback with the resistive shunt degeneration LNA is the presence of the resistor Rf, which degrades the noise figure.
  • One possible way to improve the noise figure is to increase the gain. However, doing so would normally degrade the linearity.
  • inductive series degeneration illustrated in Fig. 2 is more common than resistive shunt degeneration.
  • the input resistance will be Rin ⁇ gm ⁇ Lf/Cgs, where gm and Cgs are the transconductance and the gate-to-source capacitance, respectively, of the transistor M1.
  • a typical value of Lf is 1 nH.
  • the inductive series degeneration is inherently more narrow band as the input impedance basically corresponds to an RLC series resonator, typically with at least a moderate Q (e.g. 1 ⁇ Q ⁇ 10, which can typically be obtained for an on-chip inductor).
  • a moderate Q e.g. 1 ⁇ Q ⁇ 10
  • LNA closed-loop transconductance is reduced, typically to half the value of M1 alone, and that it is requiring a matching inductor Lg, which typically is external as its value depends on the actual operating frequency.
  • Lf when integrated on chip, may also be an issue.
  • the structure is inherently narrow band as the input impedance approximately corresponds to a series resonator,
  • Adabi et al "CMOS Low Noise Amplifier with capacitive feedback matching", Proc. IEEE 2007 Custom Integrated Circuits Conference, pp. 643-646 (in the following referred to as "Adabi et al") shows in Fig. 1 therein an LNA with a capacitive feedback.
  • the inventors have realized that the use of a capacitive feedback LNA such as that illustrated in Fig. 1 of Adabi et al can alleviate at least some of the drawbacks of the resistive shunt degeneration LNA and the inductive series degeneration LNA described above.
  • the inventors have further realized that, even if such a capacitive feedback LNA provides a matched resistive input-impedance with relative wide bandwidth, the useable bandwidth of the LNA is nevertheless limited because the bandwidth of the gain is relatively low in comparison with the bandwidth of the resistive input impedance.
  • An object of the present invention is therefore to provide an improved low-noise amplifier with capacitive feedback for use in a receiver circuit.
  • a common source or common emitter low-noise amplifier (LNA) circuit for amplifying signals at an operating frequency f in a receiver circuit.
  • the LNA circuit comprises an input transistor arranged to, in operation, be biased to have a transconductance g m at the operating frequency f , and having a first terminal, which is a gate or base terminal, operatively connected to an input terminal of the LNA circuit.
  • the LNA circuit further comprises a shunt-feedback capacitor operatively connected between the first terminal of the input transistor and a second terminal, which is a drain or collector terminal, of the input transistor.
  • the LNA circuit comprises an output capacitor operatively connected between the second terminal of the input transistor and an output terminal of the LNA circuit.
  • the output capacitor has a capacitance value C L ⁇ g m / f.
  • the input transistor may be a MOS transistor, whereby the first terminal is a gate terminal, the second terminal is a drain terminal, and the LNA circuit is a common source LNA circuit.
  • the shunt-feedback capacitor may be or comprise a MOS gate capacitor implemented with a MOS transistor of the same type as the input transistor.
  • the feedback capacitor may be or comprise a gate-to-drain capacitance of the input transistor.
  • the input transistor may be a bipolar junction transistor, whereby the first terminal is a base terminal, the second terminal is a collector terminal, and the LNA circuit is a common emitter LNA circuit.
  • the LNA circuit may comprise a series inductor operatively connected between the first terminal of the input transistor and the input terminal of the LNA circuit 30.
  • a receiver circuit comprising the LNA circuit according to the first aspect.
  • the receiver circuit further comprises a termination circuit with a current input terminal connected to the output terminal of the LNA circuit.
  • of the input impedance Z in of the termination circuit at the frequency f may be less than 1/10 of the magnitude
  • 1/(2 ⁇ f ⁇ C L ) of the impedance Z CL ( f ) of the output capacitor of the LNA circuit.
  • the termination circuit may be or comprise a common-base amplifier, a common-gate amplifier, a trans-impedance amplifier, a feedback-connected operational amplifier with a virtual-ground node as current input terminal, a transformer, or a current-mode mixer.
  • the receiver circuit may be a radio receiver circuit.
  • a radio communication apparatus comprising the receiver circuit according to the second aspect.
  • the radio communication apparatus may e.g. be, but is not limited to, a mobile terminal, a wireless data modem, or a radio base station.
  • a wireline communication apparatus comprising the receiver circuit according to the second aspect.
  • the wireline communication apparatus may e.g. be, but is not limited to, a cable modem.
  • Fig. 3 illustrates schematically an environment in which embodiments of the present invention may be employed.
  • a mobile terminal 1 illustrated in Fig. 3 as a mobile, or cellular, telephone 1
  • a radio base station 2 e.g. in a cellular communication network.
  • the mobile telephone 1 and the radio base station 2 are nonlimiting examples of what is referred to below generically with the term radio communication apparatus.
  • Another nonlimiting example of such a radio communication apparatus is a wireless data modem, e.g. a wireless data modem to be used in a cellular communication network.
  • Embodiments of the present invention may also be employed in radio communication apparatuses for operation in other types of communication networks, such as but not limited to wireless local area networks (WLANs) and personal area networks (PANs).
  • WLANs wireless local area networks
  • PANs personal area networks
  • Embodiments of the present invention may further also be employed in other types of communication apparatuses, e.g. wireline communication apparatuses, such as but not limited to cable modems.
  • Communication apparatuses may comprise one or more receiver circuits, such as a one or more radio receiver circuits in the case of radio communication apparatuses.
  • a radio receiver circuit is briefly described below with reference to Fig. 4.
  • Fig. 4 is a simplified block diagram of a radio receiver circuit 10 according to an embodiment of the present invention.
  • the radio receiver circuit 10 is connected to an antenna 15 for receiving electromagnetic radio frequency (RF) signals.
  • RF radio frequency
  • the radio receiver circuit comprises analog processing circuitry 20 for operative connection to the antenna 15.
  • the analog processing circuitry 20 is adapted to perform (analog) signal processing on RF signals from the antenna 15.
  • the analog processing circuitry 20 may comprise one or more filters and/or other circuitry for processing of RF signals.
  • Such circuitry is, per se, well known in the art of radio receivers and is therefore not further described herein in greater detail.
  • the embodiment of the radio receiver circuit 10 illustrated in Fig. 4 comprises a low-noise amplifier (LNA) circuit 30, having an input terminal 32 and an output terminal 34. Embodiments of the LNA circuit 30 are described in further detail below.
  • the embodiment of the radio receiver circuit illustrated in Fig. 4 further comprises a termination circuit 40 having an input terminal 42 connected to the output terminal 34 of the LNA circuit 30.
  • the term "termination circuit" in this context refers to any circuit that is connected to the output terminal 34 of the LNA circuit 30, and thus acts as a termination for the LNA circuit 30.
  • embodiments of the LNA circuit 30 may be employed in other types of receiver circuits than radio receiver circuits, e.g. receiver circuits for wireline communication apparatuses.
  • a receiver circuit instead of the antenna, such a receiver circuit may be connected to a connector for connection with a wireline communication network.
  • the basic structure indicated in Fig. 4 with analog processing circuitry 20, an LNA circuit 30, and a termination circuit 40 may be used in such a (non-radio) receiver circuit as well.
  • ⁇ denotes angular frequency
  • s j ⁇ , where j is the imaginary unit.
  • a drawback with the resistive shunt feedback circuit is that it requires relatively high current levels through Q3 for proper operation and that Q3 adds parasitic (outside the feedback loop, Rf) loading of the output node which limits the high-frequency performance.
  • the feedback resistor also adds capacitive losses to the substrate (ground) which influences the high-frequency performance. IfQ3 is not used (i.e. Rf connects to RL directly) the gain will be slightly lower as some of the Q1 collector current will flow through Rf. Unless Rf>> Rin (e.g.. when the voltage gain is very high), Rf will degrade the noise figure (NF) significantly.
  • A denotes the voltage gain of the circuit
  • ⁇ is approximately 1/2 for a bipolar junction transistor (BJT) and approximately 2/3 for a MOS transistor
  • R in and g m 1 are the input resistance of the circuit and the transconductance of transistor Q1, respectively.
  • the noise-figure degradation ⁇ NF is about 0.65 dB.
  • the corresponding noise-figure degradation ⁇ NF for a MOS transistor implementation at the same current is about 0.9 dB, and obtaining a similar ⁇ NF as in the BJT case would require about twice the current in the MOS transistor implementation.
  • a high LNA voltage gain is required for low noise but will at the same time reduce linearity as clipping of the output node is at a fixed level, limited by the bias current or supply voltage, and the corresponding input compression point will, thus, be inversely proportional to the LNA gain.
  • clipping at the LNA output occurs at 1V amplitude
  • One volt amplitude corresponds almost to a rail-to-rail swing for a typical bipolar transistor, while it is almost twice the supply voltage of MOS devices. Thus, this is already higher than what is practical and cannot easily be increased; the gain has to be limited for reasonable linearity.
  • a drawback with the series degeneration of Fig. 2 is that the LNA closed-loop transconductance is reduced, typically to half the value of the transconductance of M 1 alone. Furthermore, a matching inductor Lg is required. This is typically an external (or "off-chip”) inductor as its value depends on the actual operating frequency. The size of L f , when integrated on chip, may also be an issue.
  • the parameter ⁇ ( s ) is the frequency dependent current gain of the transistor M 1
  • g m denotes the transconductance of the transistor M 1
  • C gs denotes the gate-to-source capacitance of the transistor M 1
  • Z match (s) and Z lc (s) denote the impedance of the part labeled match and the part labeled IC (Integrated Circuit), respectively, in Fig. 2 .
  • This series resonator needs to be tuned for each frequency band of interest, and although the integrated parts, M 1 and L f , may support a wider frequency range, the inductor Lg has to be optimized for each band configuration.
  • Lg is replaced by a more complex matching network to compensate for parasitics (not shown in Fig. 2 ), e.g. ESD (Electro-Static Discharge) protection, but this does not significantly increase the frequency range for a given set of component values.
  • ESD Electro-Static Discharge
  • the inductive series feedback relies on a frequency dependent current gain (A I ) of the input transistor to obtain a resistive impedance match. This is true for most MOSFETs as A I ⁇ g m /( sC gs ), and thus has a capacitive behavior, for all frequencies of interest.
  • a similar resistive impedance matching, without the need for a coil L f can be obtained with a capacitive shunt feedback LNA (such as that shown in Fig. 1 of Adabi et al).
  • a simplified schematic circuit diagram of such a capacitive shunt feedback LNA is illustrated in Fig. 5 for reference. This circuit converts the capacitive feedback impedance to a resistive input impedance by means of a frequency dependent (oc 1/ ⁇ ) voltage gain.
  • the input impedance of the circuit in Fig. 5 is approximately Z in s ⁇ 1 g m ⁇ 1 + C L C F 1 + s ⁇ C gs g m ⁇ 1 + C L C F
  • the input impedance has a low-pass characteristic with a resistive part approximately equal to (1 + C L / C F )/ g m and a bandwidth approximately equal to ⁇ T /(1 + C L / C F ), where ⁇ T denotes the angular transit frequency of the transistor which typically is much larger than the operating frequency.
  • the voltage gain A v of the circuit in Fig. 5 is frequency dependent with a low-pass character A v ⁇ s ⁇ C F - g m s ⁇ C F + s ⁇ C L ⁇ - g m s ⁇ C F + s ⁇ C L
  • Eq. 4 The approximations in Eq. 4 are valid for typical component values and typical frequencies of interest achievable and used in integrated circuit LNAs. So, in spite giving a wide-band resistive input impedance the gain is not, which limits the usable frequency range. In accordance with embodiments of the present invention, this limitation is alleviated by means the concept of using the current through C L as the output rather than the voltage across it.
  • the operating frequency f (or continuous band) is a fixed predetermined frequency (or continuous band).
  • the LNA circuit is tunable to several such operating frequencies f (or continuous bands).
  • the LNA circuit 30 comprises an input transistor 50 having a first terminal 52, a second terminal 54, and a third terminal 56.
  • the input transistor 50 may be a MOS transistor or a BJT.
  • the first terminal 52 is a gate terminal
  • the second terminal 54 is a drain terminal
  • the third terminal 56 is a source terminal.
  • the first terminal 52 is a base terminal
  • the second terminal 54 is a collector terminal
  • the third terminal 56 is an emitter terminal.
  • the input transistor 50 is arranged to, in operation, be biased to have a transconductance g m at the operating frequency f.
  • the LNA circuit comprises a shunt-feedback capacitor 60 operatively connected between the first terminal 52 of the input transistor 50 and the second terminal 54 of the input transistor 50.
  • the LNA circuit comprises an output capacitor 65 operatively connected between the second terminal 54 of the input transistor 50 and the output terminal 34 of the LNA circuit 30.
  • the capacitance of the shunt-feedback capacitor 60 is in the following denoted C F
  • the capacitance of the output capacitor 65 is in the following denoted C L .
  • the shunt-feedback capacitor 60 is shown in the figures as an individual component, separate from the input transistor 50, it should be noted that the parasitic gate-to-drain capacitance of the input transistor 50 may provide a non-negligible contribution to the capacitance C F .
  • the shunt-feedback capacitor 60 may in many cases be seen as comprising the gate-to-drain capacitance of the input transistor 50 as well as a dedicated capacitor in parallel therewith. In extreme cases, the shunt-feedback capacitor 60 may even be built up by (or, simply phrased, "be") the gate-to-drain capacitance of the input transistor 50 alone.
  • Fig. 6 illustrates an embodiment of the LNA circuit 30 wherein the input transistor 50 is a MOS transistor, and the LNA circuit 30 is a common source LNA circuit.
  • a biasing unit 70 adapted to bias the LNA circuit 30 at a suitable operating point is included.
  • the biasing unit 70 may be comprised in the LNA circuit 30, or may be external to the LNA circuit 30. Alternatively, part of the biasing circuit 70 may be comprised in the LNA circuit 30 while the remainder of the biasing circuit 70 may be external to the LNA circuit 30.
  • the biasing unit 70 may e.g. comprise a passive network and/or an active network arranged to provide a suitable DC biasing current for the input transistor 50.
  • the biasing unit 70 would be designed such as to provide an open circuit at the operating frequency f (or the continuous band of such operating frequencies).
  • the biasing unit 70 is included also in the embodiments illustrated in Figs. 7-9 .
  • the design of a suitable biasing unit 70 for a particular embodiment would be a straightforward task for a person skilled in amplifier design and is therefore not further described herein in any greater detail.
  • the transconducatance g m should typically be made larger, normally much larger, than 1/R s (the reciprocal of the source resistance, as seen by the LNA, which is also the matching resistance).
  • the shunt-feedback capacitance C F can be made relatively small (i.e. with small capacitance, which also translates to a small area) and typically smaller, normally much smaller, than the capacitance C L of the output capacitor 65.
  • the loop feedback factor, or return ratio can be made relatively small. This implies that the gain reduction due to C F is typically relatively small.
  • the aforementioned gate-to-drain capacitance (or "internal shunt feedback capacitance”) of the input transistor 50 may provide a significant contribution to C F . Consequently, a relatively small additional area may be needed for the shunt-feedback capacitor 60 in order to reach the value of C F that is needed to reach the desired input resistance.
  • the transistors and capacitors may be made in the same technology and g m , C F , and C L are correlated resulting in tight tolerances. If the shunt-feedback capacitor 60 (or the part of the shunt feed-back capacitor 60 that is not the gate-to-drain capacitance of the input transistor 50) is built from an MOS gate capacitor, the matching condition will only depend on a capacitance ratio (i.e. layout feature sizes) and the transconductance g m of the input transistor 50. In practice this reduces the design work to control g m of the input transistor 50 and to make sure that parasitics are included reasonably well in the modeling of C F and C L , and thus provides a relatively low design complexity, which is advantageous.
  • a capacitance ratio i.e. layout feature sizes
  • the shunt-feedback capacitor 60 is, or comprises, a MOS gate capacitor implemented with a MOS transistor of the same type as the input transistor 50.
  • Fig. 7 the shunt-feedback capacitor of the embodiment in Fig. 6 has been implemented with a MOS transistor 75.
  • Fig. 8 shows an embodiment of the LNA circuit 30 wherein the input transistor 50 is a bipolar junction transistor (BJT) in common-emitter configuration
  • the LNA circuit 30 comprises a series inductor operatively connected between the first terminal 56 (i.e. gate or base) of the input transistor 50 and the input terminal 32 of the LNA circuit 30. This is illustrated in Fig. 9 with an example embodiment where a series inductor 80 has been added (connected between the first terminal 52 of the input transistor 50 and the input terminal 32 of the LNA circuit 30) to the embodiment illustrated in Fig. 6 .
  • the output capacitor 65 is made relatively small. This is in contrast with so called DC blocking capacitors, for which the capacitance is normally selected relatively large to effectively block the DC-level from propagating and provide essentially a short circuit at the frequency of interest. More specifically, according embodiments of the present invention, the output capacitor 65 has a capacitance value C L ⁇ g m / f, which is significantly lower than what would be used for a DC-blocking capacitor. With this choice of capacitor value there will be some residual signal voltage across the capacitor which acts like a frequency dependent voltage-to-current converter. This converter action in combination with the frequency dependent voltage gain at the node 54 provides a frequency independent gain (i.e. transconductance) from LNA input to load capacitor current. When this gain is frequency independent a wideband operation is facilitated.
  • a frequency independent gain i.e. transconductance
  • the LNA circuit 30 may be comprised in a radio receiver circuit 10, together with a termination circuit 40.
  • the input terminal 42 of the termination circuit 40 which is connected to the output terminal 34 of the LNA circuit 30, is a current input terminal, i. e. a terminal that is specifically designed (or "particularly well suited") to receive an electrical current as input.
  • This property may e.g. be defined, or quantified, in terms of input impedance or scattering parameters.
  • of the input impedance Z in of the termination circuit 40 at the frequency f is less than 1/10 of the magnitude
  • 1/ (2 ⁇ f ⁇ C L ) of the impedance Z CL ( f ) of the output capacitor 65 of the LNA circuit 30.
  • Z in in the preceding sentence is used to denote the input impedance of the termination circuit 40, whereas in Eq. 2-3, it is used to denote the input impedance of the LNA circuit. Having emphasized that, there should be no risk for confusion.
  • the ratio 1/10 is only an example; other numbers may be used as well depending on application. A suitable ratio for a given application, with given performance requirements on the LNA circuit 30, may e.g. be determined using computer simulations. The ratio 1/10 may be a suitable starting point for such simulations.
  • the input impedance of the termination circuit 40 in turn affects the s11 scattering parameter of the LNA circuit 30, which thus in turn can be used to characterize the suitability of the termination circuit for receiving an electrical current as an input signal.
  • of the scattering parameter s 11 at the input terminal 32 of the LNA circuit 30 is less than -10 dB at the frequency f.
  • the s1 parameter value -10 dB is only an example; other numbers may be used as well depending on application.
  • a suitable s1 parameter value for a given application, with given performance requirements on the LNA circuit 30, may e.g. be determined using computer simulations.
  • the s 11 parameter value -10 dB may be a suitable starting point for such simulations.
  • Fig. 10 illustrates with an example how a termination circuit 40 with such a current input terminal may be accomplished.
  • the termination circuit 40 comprises a feedback-connected operational amplifier 100.
  • the negative feedback of the operational amplifier 100 provides a virtual ground node at the negative input terminal of the operational amplifier 100.
  • varying the current input to the input terminal 42 would only result in a relatively small voltage variation (ideally none for an operational amplifier with infinite gain) at the input terminal 42, whereby the input terminal 42 is suitable for receiving an input current.
  • the virtual-ground node of the feed-back connected operational amplifier 100 is used as current input terminal.
  • the example illustrated in Fig. 10 is only an example.
  • Other examples of circuits that can be designed to have a suitable input impedance value, or provide a suitable s1 value for the LNA circuit 30, to be suitable for receiving an electrical current as input signal are e.g. common-base amplifiers, common-gate amplifiers, trans-impedance amplifiers, and transformers.
  • the termination circuit 40 is or comprises a common-base amplifier, a common-gate amplifier, a trans-impedance amplifier, a feedback-connected operational amplifier 100 with a virtual-ground node as current input terminal, a transformer, or a current-mode mixer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Multimedia (AREA)
  • Amplifiers (AREA)
EP12153472.1A 2012-02-01 2012-02-01 Amplificateur de faible bruit Active EP2624448B1 (fr)

Priority Applications (9)

Application Number Priority Date Filing Date Title
EP15171109.0A EP2947769B1 (fr) 2012-02-01 2012-02-01 Amplificateur de faible bruit
EP12153472.1A EP2624448B1 (fr) 2012-02-01 2012-02-01 Amplificateur de faible bruit
DK12153472.1T DK2624448T3 (en) 2012-02-01 2012-02-01 Amplifier with low noise
ES12153472.1T ES2551883T3 (es) 2012-02-01 2012-02-01 Amplificador de bajo ruido
IN5942DEN2014 IN2014DN05942A (fr) 2012-02-01 2013-01-25
AU2013214368A AU2013214368B2 (en) 2012-02-01 2013-01-25 Low-noise amplifier
US14/375,127 US9312818B2 (en) 2012-02-01 2013-01-25 Low-noise amplifier
PCT/EP2013/051492 WO2013113636A2 (fr) 2012-02-01 2013-01-25 Amplificateur à faible bruit
MYPI2014701907A MY170838A (en) 2012-02-01 2013-01-25 Low-noise amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP12153472.1A EP2624448B1 (fr) 2012-02-01 2012-02-01 Amplificateur de faible bruit

Related Child Applications (2)

Application Number Title Priority Date Filing Date
EP15171109.0A Division-Into EP2947769B1 (fr) 2012-02-01 2012-02-01 Amplificateur de faible bruit
EP15171109.0A Division EP2947769B1 (fr) 2012-02-01 2012-02-01 Amplificateur de faible bruit

Publications (2)

Publication Number Publication Date
EP2624448A1 true EP2624448A1 (fr) 2013-08-07
EP2624448B1 EP2624448B1 (fr) 2015-08-19

Family

ID=45531812

Family Applications (2)

Application Number Title Priority Date Filing Date
EP12153472.1A Active EP2624448B1 (fr) 2012-02-01 2012-02-01 Amplificateur de faible bruit
EP15171109.0A Active EP2947769B1 (fr) 2012-02-01 2012-02-01 Amplificateur de faible bruit

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP15171109.0A Active EP2947769B1 (fr) 2012-02-01 2012-02-01 Amplificateur de faible bruit

Country Status (8)

Country Link
US (1) US9312818B2 (fr)
EP (2) EP2624448B1 (fr)
AU (1) AU2013214368B2 (fr)
DK (1) DK2624448T3 (fr)
ES (1) ES2551883T3 (fr)
IN (1) IN2014DN05942A (fr)
MY (1) MY170838A (fr)
WO (1) WO2013113636A2 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2947769A1 (fr) 2012-02-01 2015-11-25 Telefonaktiebolaget L M Ericsson (PUBL) Amplificateur de faible bruit
WO2017190764A1 (fr) * 2016-05-02 2017-11-09 Telefonaktiebolaget Lm Ericsson (Publ) Amplificateur
CN108988799A (zh) * 2018-08-28 2018-12-11 天津大学 用于低电压工作的宽带有源反馈型跨阻放大器
CN109474795A (zh) * 2018-10-31 2019-03-15 天津大学 一种基于跨导单元的低噪声像素电路结构
EP2854287B1 (fr) * 2013-08-28 2020-06-24 Analog Devices, Inc. Amplificateur à grande vitesse

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9413301B2 (en) 2012-02-01 2016-08-09 Telefonaktiebolaget Lm Ericsson (Publ) Noise canceling low-noise amplifier
TWI670930B (zh) * 2018-12-18 2019-09-01 財團法人工業技術研究院 無線接收裝置
DE102019205114B4 (de) * 2019-04-10 2022-02-10 Siemens Healthcare Gmbh Einstufiger Verstärker mit aktiver Rückwirkungskompensation
US11361786B1 (en) 2020-11-20 2022-06-14 Western Digital Technologies, Inc. Data storage device employing amplifier feedback for impedance matching
CN113746442B (zh) * 2021-11-05 2022-02-11 成都明夷电子科技有限公司 一种低电压高线性共源共栅放大器

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5589881A (en) * 1994-11-09 1996-12-31 The Regents Of The Univ. Of California Office Of Technology Transfer Enhanced performance CCD output amplifier
US5963094A (en) * 1998-02-20 1999-10-05 Raytheon Company Monolithic class AB shunt-shunt feedback CMOS low noise amplifier having self bias
US6211738B1 (en) * 1998-01-30 2001-04-03 Conexant Systems, Inc. Stability and enhanced gain of amplifiers using inductive coupling
WO2002015397A2 (fr) 2000-08-16 2002-02-21 Maxim Integrated Products, Inc. Amplificateur a grande linearite et adaptation d'impedance comportant un mode de derivation a faible perte
EP1635453A1 (fr) * 2004-09-12 2006-03-15 Semiconductor Ideas to The Market (ItoM) BV Amplificateur faible bruit ajustable
WO2006083200A1 (fr) * 2005-02-07 2006-08-10 Telefonaktiebolaget Lm Ericsson (Publ) Circuit electrique
US20080048785A1 (en) * 2006-08-22 2008-02-28 Mokhtar Fuad Bin Haji Low-noise amplifier
US20080169877A1 (en) * 2006-12-21 2008-07-17 Seiichi Banba Amplifier for use in radio-frequency band
US20080290944A1 (en) * 2007-05-25 2008-11-27 Rahul Sarpeshkar Micropower neural amplifier with adaptive input-referred noise
US7466205B1 (en) * 2007-06-20 2008-12-16 National Taiwan University Ultra-wideband low noise amplifier and amplification method thereof
US20090021295A1 (en) * 2007-07-19 2009-01-22 Chang-Tsung Fu Dual reactive shunt low noise amplifier

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4422052A (en) 1981-05-29 1983-12-20 Rca Corporation Delay circuit employing active bandpass filter
US4689578A (en) 1986-03-28 1987-08-25 The United States Of America As Represented By The Secretary Of The Navy Hydrophone pre-amplifier with self-calibration
US5015968A (en) * 1990-07-27 1991-05-14 Pacific Monolithics Feedback cascode amplifier
US6147559A (en) * 1998-07-30 2000-11-14 Philips Electronics North America Corporation Noise figure and linearity improvement technique using shunt feedback
US6204728B1 (en) * 1999-01-28 2001-03-20 Maxim Integrated Products, Inc. Radio frequency amplifier with reduced intermodulation distortion
KR101131272B1 (ko) 2004-03-24 2012-03-30 조지아 테크 리서치 코오포레이션 다중대역 저잡음 증폭기의 입력 매칭 회로
US7177616B2 (en) 2004-08-13 2007-02-13 Freescale Semiconductor, Inc. High linearity and low noise CMOS mixer and signal mixing method
US7177613B2 (en) * 2004-09-30 2007-02-13 Texas Instruments Incorporated Reducing noise and distortion in a receiver system
JP2009510866A (ja) * 2005-09-26 2009-03-12 グロナヴ リミテッド 多段共振増幅器システムおよび方法
US7202733B1 (en) 2005-11-02 2007-04-10 Marvell International Ltd. Transconductance amplifiers with compensation
US7701292B2 (en) 2007-03-13 2010-04-20 Realtek Semiconductor Corp. Programmable gain amplifier with noise cancellation
TWI341078B (en) 2008-02-21 2011-04-21 Univ Nat Taiwan Cascode-cascade doherty power amplifier
DK2624448T3 (en) 2012-02-01 2015-11-16 Ericsson Telefon Ab L M Amplifier with low noise
US9413301B2 (en) 2012-02-01 2016-08-09 Telefonaktiebolaget Lm Ericsson (Publ) Noise canceling low-noise amplifier

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5589881A (en) * 1994-11-09 1996-12-31 The Regents Of The Univ. Of California Office Of Technology Transfer Enhanced performance CCD output amplifier
US6211738B1 (en) * 1998-01-30 2001-04-03 Conexant Systems, Inc. Stability and enhanced gain of amplifiers using inductive coupling
US5963094A (en) * 1998-02-20 1999-10-05 Raytheon Company Monolithic class AB shunt-shunt feedback CMOS low noise amplifier having self bias
WO2002015397A2 (fr) 2000-08-16 2002-02-21 Maxim Integrated Products, Inc. Amplificateur a grande linearite et adaptation d'impedance comportant un mode de derivation a faible perte
EP1635453A1 (fr) * 2004-09-12 2006-03-15 Semiconductor Ideas to The Market (ItoM) BV Amplificateur faible bruit ajustable
WO2006083200A1 (fr) * 2005-02-07 2006-08-10 Telefonaktiebolaget Lm Ericsson (Publ) Circuit electrique
US20080048785A1 (en) * 2006-08-22 2008-02-28 Mokhtar Fuad Bin Haji Low-noise amplifier
US20080169877A1 (en) * 2006-12-21 2008-07-17 Seiichi Banba Amplifier for use in radio-frequency band
US20080290944A1 (en) * 2007-05-25 2008-11-27 Rahul Sarpeshkar Micropower neural amplifier with adaptive input-referred noise
US7466205B1 (en) * 2007-06-20 2008-12-16 National Taiwan University Ultra-wideband low noise amplifier and amplification method thereof
US20090021295A1 (en) * 2007-07-19 2009-01-22 Chang-Tsung Fu Dual reactive shunt low noise amplifier

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ADABI ET AL.: "CMOS Low Noise Amplifier with capacitive feedback matching", PROC. IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2007, pages 643 - 646

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2947769A1 (fr) 2012-02-01 2015-11-25 Telefonaktiebolaget L M Ericsson (PUBL) Amplificateur de faible bruit
EP2854287B1 (fr) * 2013-08-28 2020-06-24 Analog Devices, Inc. Amplificateur à grande vitesse
WO2017190764A1 (fr) * 2016-05-02 2017-11-09 Telefonaktiebolaget Lm Ericsson (Publ) Amplificateur
US10320341B2 (en) 2016-05-02 2019-06-11 Telefonaktiebolaget Lm Ericsson (Publ) Amplifier
US10673393B2 (en) 2016-05-02 2020-06-02 Telefonaktiebolaget Lm Ericsson (Publ) Amplifier
EP3678293A1 (fr) * 2016-05-02 2020-07-08 Telefonaktiebolaget LM Ericsson (publ) Amplificateur
US11290064B2 (en) 2016-05-02 2022-03-29 Telefonaktiebolaget Lm Ericsson (Publ) Amplifier
CN108988799A (zh) * 2018-08-28 2018-12-11 天津大学 用于低电压工作的宽带有源反馈型跨阻放大器
CN108988799B (zh) * 2018-08-28 2022-03-04 天津大学 用于低电压工作的宽带有源反馈型跨阻放大器
CN109474795A (zh) * 2018-10-31 2019-03-15 天津大学 一种基于跨导单元的低噪声像素电路结构

Also Published As

Publication number Publication date
WO2013113636A3 (fr) 2013-12-19
US20150002225A1 (en) 2015-01-01
DK2624448T3 (en) 2015-11-16
ES2551883T3 (es) 2015-11-24
US9312818B2 (en) 2016-04-12
AU2013214368B2 (en) 2015-09-03
EP2624448B1 (fr) 2015-08-19
EP2947769A1 (fr) 2015-11-25
EP2947769B1 (fr) 2017-04-05
IN2014DN05942A (fr) 2015-06-26
AU2013214368A1 (en) 2014-08-21
WO2013113636A2 (fr) 2013-08-08
MY170838A (en) 2019-09-06

Similar Documents

Publication Publication Date Title
EP2624448B1 (fr) Amplificateur de faible bruit
US8577325B2 (en) Low noise amplifier having both ultra-high linearity and low noise characteristic and radio receiver including the same
US7804361B2 (en) Low noise amplifier
JP5612034B2 (ja) アクティブポストディストーション線形化を有する差動増幅器
US8971831B2 (en) Front-end system for radio devices
KR20100092519A (ko) 저잡음 및 저입력 커패시턴스 차동 ｍｄｓ ｌｎａ
US20090206932A1 (en) Low noise amplifier gain controlled scheme
CN101273525A (zh) 具有有源后失真线性化的放大器
US9413301B2 (en) Noise canceling low-noise amplifier
KR100789918B1 (ko) 광대역 저잡음 증폭기의 입력 매칭 회로
JP2009207031A (ja) 増幅回路
AU2013214369B2 (en) Noise canceling low-noise amplifier
US8125272B1 (en) Low power wide-band amplifier with reused current
US7345548B2 (en) Radiofrequency amplifier device, in particular for cellular mobile telephone
EP2045913A1 (fr) Amplificateur à faible bruit et circuit de commande de gain en mode N correspondant
US7049878B2 (en) Down-converter using an on-chip bias circuit for enhancing symmetry and linearity and testing device thereof
CN110661494A (zh) 高频放大电路及半导体设备
US11888454B2 (en) Blocking signal cancellation low noise amplifier system
Loong et al. 1.575 GHz to 2.48 GHz multi-standard low noise amplifier using 0.18-µm CMOS with on-chip matching
CN111903054B (zh) 单端转差分放大器和射频接收机
US10164578B2 (en) Frequency selective low noise amplifier circuit
Kang et al. Design and analysis of a high-performance cascode bipolar low noise amplifier with shunt feedback capacitor
CN117499183A (zh) 一种信号处理方法、系统及电路
US6992530B2 (en) RF amplifier with improved impedance matching
Mak et al. A High-Voltage-Enabled Mobile-TV RF Front-End in 90-nm CMOS

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

17P Request for examination filed

Effective date: 20140205

RBV Designated contracting states (corrected)

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

17Q First examination report despatched

Effective date: 20140228

REG Reference to a national code

Ref country code: DE

Ref legal event code: R079

Ref document number: 602012009695

Country of ref document: DE

Free format text: PREVIOUS MAIN CLASS: H03F0001260000

Ipc: H03F0001300000

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

RIC1 Information provided on ipc code assigned before grant

Ipc: H03F 1/34 20060101ALI20150303BHEP

Ipc: H03F 1/56 20060101ALI20150303BHEP

Ipc: H03F 1/30 20060101AFI20150303BHEP

Ipc: H03F 3/185 20060101ALI20150303BHEP

Ipc: H03F 3/195 20060101ALI20150303BHEP

Ipc: H03F 1/26 20060101ALI20150303BHEP

INTG Intention to grant announced

Effective date: 20150318

RIN1 Information on inventor provided before grant (corrected)

Inventor name: MATTISSON, SVEN

Inventor name: ANDERSSON, STEFAN

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: AT

Ref legal event code: REF

Ref document number: 744413

Country of ref document: AT

Kind code of ref document: T

Effective date: 20150915

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602012009695

Country of ref document: DE

REG Reference to a national code

Ref country code: DK

Ref legal event code: T3

Effective date: 20151109

REG Reference to a national code

Ref country code: ES

Ref legal event code: FG2A

Ref document number: 2551883

Country of ref document: ES

Kind code of ref document: T3

Effective date: 20151124

REG Reference to a national code

Ref country code: AT

Ref legal event code: MK05

Ref document number: 744413

Country of ref document: AT

Kind code of ref document: T

Effective date: 20150819

REG Reference to a national code

Ref country code: LT

Ref legal event code: MG4D

REG Reference to a national code

Ref country code: NL

Ref legal event code: FP

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150819

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150819

Ref country code: NO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20151119

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150819

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20151219

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150819

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20151221

Ref country code: RS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150819

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150819

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150819

REG Reference to a national code

Ref country code: GR

Ref legal event code: EP

Ref document number: 20150402105

Country of ref document: GR

Effective date: 20151209

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150819

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150819

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150819

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150819

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602012009695

Country of ref document: DE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150819

Ref country code: BE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20160229

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20160520

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150819

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150819

Ref country code: LU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20160201

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20160229

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20160229

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20161028

REG Reference to a national code

Ref country code: IE

Ref legal event code: MM4A

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150819

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20160229

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20160201

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150819

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO

Effective date: 20120201

Ref country code: SM

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150819

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150819

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20160229

Ref country code: HR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150819

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150819

Ref country code: MK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150819

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150819

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150819

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: ES

Payment date: 20190301

Year of fee payment: 8

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DK

Payment date: 20190227

Year of fee payment: 8

Ref country code: GR

Payment date: 20190227

Year of fee payment: 8

REG Reference to a national code

Ref country code: DK

Ref legal event code: EBP

Effective date: 20200229

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20200909

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DK

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20200229

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: ES

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20200202

P01 Opt-out of the competence of the unified patent court (upc) registered

Effective date: 20230523

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: NL

Payment date: 20240226

Year of fee payment: 13

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20240228

Year of fee payment: 13

Ref country code: GB

Payment date: 20240227

Year of fee payment: 13