EP2556537A1 - Method for manufacturing two adjacent areas made of different materials - Google Patents
Method for manufacturing two adjacent areas made of different materialsInfo
- Publication number
- EP2556537A1 EP2556537A1 EP11712973A EP11712973A EP2556537A1 EP 2556537 A1 EP2556537 A1 EP 2556537A1 EP 11712973 A EP11712973 A EP 11712973A EP 11712973 A EP11712973 A EP 11712973A EP 2556537 A1 EP2556537 A1 EP 2556537A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- solvent
- electrodes
- volume
- materials
- liquid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/10—Deposition of organic active material
- H10K71/12—Deposition of organic active material using liquid deposition, e.g. spin coating
- H10K71/13—Deposition of organic active material using liquid deposition, e.g. spin coating using printing techniques, e.g. ink-jet printing or screen printing
- H10K71/135—Deposition of organic active material using liquid deposition, e.g. spin coating using printing techniques, e.g. ink-jet printing or screen printing using ink-jet printing
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/10—Deposition of organic active material
- H10K71/12—Deposition of organic active material using liquid deposition, e.g. spin coating
- H10K71/15—Deposition of organic active material using liquid deposition, e.g. spin coating characterised by the solvent used
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/464—Lateral top-gate IGFETs comprising only a single gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
- H10K10/471—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising only organic materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
- H10K10/472—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising only inorganic materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
- H10K10/80—Constructional details
- H10K10/82—Electrodes
- H10K10/84—Ohmic electrodes, e.g. source or drain electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/60—Forming conductive regions or layers, e.g. electrodes
- H10K71/611—Forming conductive regions or layers, e.g. electrodes using printing deposition, e.g. ink jet printing
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
- H10K85/40—Organosilicon compounds, e.g. TIPS pentacene
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
- H10K85/60—Organic compounds having low molecular weight
- H10K85/615—Polycyclic condensed aromatic hydrocarbons, e.g. anthracene
- H10K85/621—Aromatic anhydride or imide compounds, e.g. perylene tetra-carboxylic dianhydride or perylene tetracarboxylic di-imide
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
- H10K85/60—Organic compounds having low molecular weight
- H10K85/615—Polycyclic condensed aromatic hydrocarbons, e.g. anthracene
- H10K85/623—Polycyclic condensed aromatic hydrocarbons, e.g. anthracene containing five rings, e.g. pentacene
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
- H10K85/60—Organic compounds having low molecular weight
- H10K85/649—Aromatic compounds comprising a hetero atom
- H10K85/655—Aromatic compounds comprising a hetero atom comprising only sulfur as heteroatom
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
- H10K85/60—Organic compounds having low molecular weight
- H10K85/649—Aromatic compounds comprising a hetero atom
- H10K85/657—Polycyclic condensed heteroaromatic hydrocarbons
- H10K85/6576—Polycyclic condensed heteroaromatic hydrocarbons comprising only sulfur in the heteroaromatic polycondensed ring system, e.g. benzothiophene
Definitions
- the present invention relates to the manufacture of adjacent areas of a surface made of different materials. It finds particular application in the field of manufacturing microelectronic components, such as transistors for example. STATE OF THE ART
- a common technique for producing a layer of material on a surface is to disperse this material in a solvent, to deposit one or more drops of the liquid solution thus obtained on a target area that is to be coated with the material, and then to remove the solvent, for example by evaporation.
- microelectronic components such as transistors for example
- the manufacture of microelectronic components requires depositing drops of liquid on a reduced area, while avoiding that the same liquid is spilled on adjacent areas, only a few micrometers apart. Indeed, these adjacent areas have different functions implemented by different materials. It is therefore appropriate for an adjacent zone not to receive material that is not intended for it, at the risk of rendering the microelectronic component unusable.
- the production of an area by liquid deposition conventionally consists in previously covering the adjacent areas with a masking resin, in particular by means of photolithography, in the deposition and evaporation of the liquid on the target area. and then removing the masking resin by a suitable chemical bath. This operation is repeated for each zone to be manufactured, thus multiplying the manufacturing steps, and therefore the total cost thereof.
- the object of the present invention is to provide a method of manufacture which is simple, precise and which protects adjacent areas from each other without resorting to additional steps of protection.
- the subject of the invention is a method for manufacturing a first and second adjacent zones of a surface, constituted respectively of a first and a second different material, the process consisting in:
- the second volume is deposited simultaneously or successively at the deposition of the first volume, before the first volume reaches the second zone.
- solvent is understood here a liquid for the dissolution of a material, or the dispersion of particles or nano-objects. According to embodiments of the invention:
- one solvent is a polar solvent and the other solvent is an apolar solvent
- the apolar solvent is a fluorosolvant
- the polar solvent is alcohol, especially isopropanol
- the polar solvent is water, and the nonpolar solvent is hexane or tetralin;
- the polar solvent is an alcohol, particularly methanol, and the apolar solvent is tetralin or hexane;
- the first and second materials are for forming SAM
- the first and second zones comprise electrodes on which SAMs are formed, in particular electrodes of MOS transistors of a CMOS circuit;
- the first material is 2,3,4,5, 6-pentafluorobenzenethiol
- the second material is 4-methoxythiophenol
- the first and second materials are semiconductor materials
- the first material is 6,13-bis (triisopropylsilylethynyl) pentacene (TIPS pentacene) or a like molecule anthradithiophène fluorinated, preferably the 5,1-bis (triethylsilylethynyl) fluorinated anthradithiophène, and the second material is a type of molecule acene diimide;
- the first and second zones respectively constitute the electrodes of a transistor P and the electrodes of a transistor N;
- the first and second zones constitute the electrodes of a diode or a transistor LEFET
- the first and second materials are insulating materials
- the first and second zones constitute the gate oxides of juxtaposed transistors.
- FIGS. 1 to 6 illustrating a method according to the invention for manufacturing a basic structure.
- CMOS in which identical references designate identical elements.
- FIGS 1 to 6 illustrate, in sectional views, steps of manufacturing a CMOS basic structure, according to the invention.
- This structure comprises a transistor P and a transistor N.
- the source and drain metal electrodes 10 of the transistor P and the source and drain metal electrodes 12 of the transistor N are formed on a plastic substrate 14, for example polyethylene naphthalate (PEN).
- PEN polyethylene naphthalate
- the electrodes 10 are separated from the electrodes 12 by about 100 to 200 microns.
- One or more drops 16 of a first liquid comprising a dispersion of a first P type injection semiconductor material SAM, for example 2,3,4,5,6-pentafluorobenzenethiol, in a first solvent, are then deposited on the electrodes 12 by means of a nozzle 18 of an inkjet printing device (FIG. 1).
- a volume of liquid solution is thus formed comprising the first material and including the electrodes 12 (FIG. 2).
- the nozzle 18 is then translated to position above the electrodes 10 before the volume 20 has time to spread in the vicinity of the electrodes 10, and one or more drops of a second liquid, comprising a dispersion of a second N-type injection molding semiconductor material SAM, for example 4-methoxythiophenol, in a second solvent, are then deposited on the electrodes 10.
- a second liquid comprising a dispersion of a second N-type injection molding semiconductor material SAM, for example 4-methoxythiophenol, in a second solvent
- a SAM (acronym for the expression "self-assembled mpnolayer") is a layer obtained by grafting.
- the manufacture of SAM requires a large volume of organic solvent to achieve the self-assembly on the electrodes 10, 12, thus involving volumes 20 and 22 of substantial size, and therefore likely to spread well beyond. beyond the immediate vicinity of the electrodes for which they are intended.
- solutions concentration between 10 "5% and 10% of the material to be deposited.
- the SAMs make it possible to adapt the output work of an electrode to the semiconductor which covers the electrode. They are of two types: the P type SAMs, which increase the output work of the electrodes P and therefore improve their electron injection efficiency,
- the solvent of the volume 20 and the solvent of the volume 22 are chosen immiscible with each other, or "orthogonal", which has the effect that the volumes 20 and 22 are mutually blocking and thus protect their respective deposition area.
- the volume 20 blocks the volume 22 during its spreading and therefore prevents the volume 22 from reaching the electrodes 12 and their vicinity.
- a P-type SAM 24 is formed on the electrodes 12 and a SAM N-type 26 is formed on the electrodes 10 ( Figure 3).
- a dielectric layer 32 is then made on the assembly (FIG. 5) and metal electrodes for the gate of the transistors are formed on the dielectric 32 (FIG. 6).
- the first solvent is apolar
- the second solvent is polar.
- the apolar solvent is a fluorosolvent and the polar solvent is an alcohol, especially isopropanol.
- the polar solvent is water
- the apolar solvent is hexane or tetralin.
- the polar solvent is an alcohol, in particular methanol, and the apolar solvent is tetralin or hexane.
- the present invention applies to any type of material to be deposited, for example any type of conductive material, semiconductor or insulating, since it is desired that said material is deposited on a well-defined area.
- any type of material to be deposited for example any type of conductive material, semiconductor or insulating, since it is desired that said material is deposited on a well-defined area.
- MOS transistors of a CMOS circuit but also the realization of the electrodes of diodes or transistors LEFET.
- this embodiment of the invention consists in depositing one or more types of materials on adjacent and distinct zones by providing for each of them a mechanism of affinity with the material. which is intended for them.
- the affinity mechanism is that of the SAMs for which the materials involved (material to be deposited and material on the surface or constitutive of the target zone) are chosen. so as to achieve a strong bond, usually of metal type, between the surface material or constituent of the target area and the material to be deposited thereon.
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1052647A FR2958561B1 (en) | 2010-04-08 | 2010-04-08 | PROCESS FOR MANUFACTURING TWO ZONES ADJACENT IN DIFFERENT MATERIALS |
PCT/FR2011/050466 WO2011124792A1 (en) | 2010-04-08 | 2011-03-07 | Method for manufacturing two adjacent areas made of different materials |
Publications (1)
Publication Number | Publication Date |
---|---|
EP2556537A1 true EP2556537A1 (en) | 2013-02-13 |
Family
ID=42729408
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP11712973A Withdrawn EP2556537A1 (en) | 2010-04-08 | 2011-03-07 | Method for manufacturing two adjacent areas made of different materials |
Country Status (7)
Country | Link |
---|---|
US (1) | US8889473B2 (en) |
EP (1) | EP2556537A1 (en) |
JP (1) | JP2013526013A (en) |
CN (1) | CN102906878B (en) |
BR (1) | BR112012025054A2 (en) |
FR (1) | FR2958561B1 (en) |
WO (1) | WO2011124792A1 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10466193B2 (en) | 2017-03-01 | 2019-11-05 | Palo Alto Research Center Incorporated | Printed gas sensor |
US10490746B2 (en) * | 2017-03-01 | 2019-11-26 | Palo Alto Research Center Incorporated | Selective surface modification of OTFT source/drain electrode by ink jetting F4TCNQ |
FR3105573A1 (en) * | 2019-12-23 | 2021-06-25 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Manufacturing process of a secure integrated circuit |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003056641A1 (en) * | 2001-12-21 | 2003-07-10 | Plastic Logic Limited | Self-aligned printing |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999019900A2 (en) * | 1997-10-14 | 1999-04-22 | Patterning Technologies Limited | Method of forming an electronic device |
CN100530758C (en) * | 1998-03-17 | 2009-08-19 | 精工爱普生株式会社 | Thin film pattering substrate and surface treatment |
CN100375310C (en) * | 1999-12-21 | 2008-03-12 | 造型逻辑有限公司 | Inkjet-fabricated integrated circuits |
GB2379083A (en) * | 2001-08-20 | 2003-02-26 | Seiko Epson Corp | Inkjet printing on a substrate using two immiscible liquids |
GB2388709A (en) * | 2002-05-17 | 2003-11-19 | Seiko Epson Corp | Circuit fabrication method |
GB0321383D0 (en) * | 2003-09-12 | 2003-10-15 | Plastic Logic Ltd | Polymer circuits |
TWI316296B (en) * | 2006-09-05 | 2009-10-21 | Ind Tech Res Inst | Thin-film transistor and fabrication method thereof |
JP5111949B2 (en) * | 2007-06-18 | 2013-01-09 | 株式会社日立製作所 | Thin film transistor manufacturing method and thin film transistor device |
-
2010
- 2010-04-08 FR FR1052647A patent/FR2958561B1/en not_active Expired - Fee Related
-
2011
- 2011-03-07 CN CN201180017537.3A patent/CN102906878B/en not_active Expired - Fee Related
- 2011-03-07 WO PCT/FR2011/050466 patent/WO2011124792A1/en active Application Filing
- 2011-03-07 EP EP11712973A patent/EP2556537A1/en not_active Withdrawn
- 2011-03-07 JP JP2013503152A patent/JP2013526013A/en active Pending
- 2011-03-07 US US13/639,284 patent/US8889473B2/en active Active
- 2011-03-07 BR BR112012025054A patent/BR112012025054A2/en not_active IP Right Cessation
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003056641A1 (en) * | 2001-12-21 | 2003-07-10 | Plastic Logic Limited | Self-aligned printing |
Also Published As
Publication number | Publication date |
---|---|
US8889473B2 (en) | 2014-11-18 |
BR112012025054A2 (en) | 2016-06-21 |
FR2958561A1 (en) | 2011-10-14 |
CN102906878A (en) | 2013-01-30 |
JP2013526013A (en) | 2013-06-20 |
WO2011124792A1 (en) | 2011-10-13 |
FR2958561B1 (en) | 2012-05-04 |
US20130029455A1 (en) | 2013-01-31 |
CN102906878B (en) | 2016-04-13 |
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