EP2506370B1 - A submount arrangement for VCSELs - Google Patents
A submount arrangement for VCSELs Download PDFInfo
- Publication number
- EP2506370B1 EP2506370B1 EP11160547.3A EP11160547A EP2506370B1 EP 2506370 B1 EP2506370 B1 EP 2506370B1 EP 11160547 A EP11160547 A EP 11160547A EP 2506370 B1 EP2506370 B1 EP 2506370B1
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- EP
- European Patent Office
- Prior art keywords
- submount
- vcsel
- vcsels
- arrangement
- recess
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/023—Mount members, e.g. sub-mount members
- H01S5/02325—Mechanically integrated components on mount members or optical micro-benches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/02218—Material of the housings; Filling of the housings
- H01S5/0222—Gas-filled housings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/0233—Mounting configuration of laser chips
- H01S5/0234—Up-side down mountings, e.g. Flip-chip, epi-side down mountings or junction down mountings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
- H01S5/042—Electrical excitation ; Circuits therefor
- H01S5/0425—Electrodes, e.g. characterised by the structure
- H01S5/04256—Electrodes, e.g. characterised by the structure characterised by the configuration
- H01S5/04257—Electrodes, e.g. characterised by the structure characterised by the configuration having positive and negative electrodes on the same side of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/40—Arrangement of two or more semiconductor lasers, not provided for in groups H01S5/02 - H01S5/30
- H01S5/42—Arrays of surface emitting lasers
- H01S5/423—Arrays of surface emitting lasers having a vertical cavity
Definitions
- the present invention generally relates to mounting of Vertical-Cavity Surface-Emitting Lasers (VCSELs), a class of semiconductor laser devices that emits light perpendicular to a wafer's surface. More particularly, the invention concerns efficient flip-chip mounting of VCSELs reducing optical coupling losses and enabling passive alignment of the VCSELs.
- VCSELs Vertical-Cavity Surface-Emitting Lasers
- VCSELs or VCSEL arrays are mounted by direct or indirect attachment of the VCSELs' substrate to another substrate containing a waveguide.
- the substrate may be glass, silicon, InP, GaAs, etc.
- VCSELs are typically flip-chip mounted, i.e. the VCSELs are vertically flipped in order to present laser light to a light coupling device, e.g. a planar waveguide, a mirror, an optical detector, a diffraction grating, etc.
- a substrate or submount
- Use of such a submount enables easy testing and screening of defect VCSELs prior to flip-chip.
- FIG. 9-14 and the corresponding sections of the patent application text, i.e. page 9, line 10 to page 11, line 20 of WO 00/41281 , describe flip-chip mounting of a VCSEL (901, 1401) using a submount arrangement with substrate (902, 1402), hermetic seal (908, 1408) and cover (1010, 1410) wherein a lens (1008) is integrated.
- the substrate may or may not be formed with a recess.
- VCSELs as learned from the individual or combined teaching of WO 00/41281 and WO 03/058777 is disadvantageous for several reasons.
- electrical connectivity between the VCSEL and submount is realised through wire bonding.
- the wire bond shall extend at least 30 micrometers from the light emitting surface of the VCSEL. This is illustrated by Fig. 1 .
- a distance of at least 30 micrometers and usually more than 50 micrometers extending from the light emitting surface of the VCSEL must be kept free. This minimum distance of 30 micrometers to any light coupling device results in high optical coupling losses unless a lens is used.
- WO 00/41281 de facto integrates a lens (1008) in the cover of the submount arrangement. Such lenses add cost and introduce additional complexity.
- Another drawback resides in the alignment between VCSEL and light coupling device.
- One option is 'active alignment' where the VCSEL is powered up so that it emits light. As it is aligned over the light coupling device the amount of light actually coupled into the waveguide is measured to find the optimum position.
- Such active alignment involves measurements, is expensive and time consuming.
- Passive alignment relies on recognition of alignment marks on the two objects to be aligned and then placing of the objects in the correct position by aligning the sets of marks appropriately.
- Passive alignment is preferred but requires visual access to alignment marks on the light emitting surface of the VCSEL during flip chip. This is made impossible by WO 00/41281 as the light emitting side of the VCSEL is covered. In other words the lenses that are needed in WO 00/41281 to compensate for the optical losses prevent passive alignment between VCSEL and light coupling device.
- US 2005/0013562 entitled “Optical Component and Manufacture Method of the Same” shows in Fig. 5C a submount arrangement 13 for VCSELs 20.
- US 2005/0013562 aims at reducing the size and height of such submount arrangements, as is indicated in paragraph [0007] of US 2005/0013562 .
- the arrangement 13 shown in Fig. 5C of US 2005/0013562 is composed of several ceramic layers 131, wiring 16 between the ceramic layers 131, and a lens 11.
- Each of the ceramic layers 131 is at least 50 micrometers thick.
- the lens 11 has the aim to condense the beam emitted by VCSEL 20 and to compensate for the optical losses resulting from the vertical distance the light has to travel.
- EP 1 914 814 A1 refers to a method for producing a radiation-emitting optoelectronic component
- a semiconductor chip is mounted by a first main area onto a carrier body and is electrically conductively connected at a first contact area to a first connection region, and a transparent electrically insulating encapsulation layer is applied to the chip and the carrier body.
- a first cutout in the encapsulation layer for at least partly uncovering a second contact area of the chip is produced, and a second cutout in the encapsulation layer for at least partly uncovering a second connection region of the carrier body is produced.
- an electrically conductive layer which electrically conductively connects the second contact area of the semiconductor chip and the second connection region of the carrier body, is applied.
- JP 2008090218 provides in an optical element module, a first region having a liquidphilic property to a material constituting an adhesive is formed at a part of the optical waveguide which transmits light, a second region having the liquidphilic property to the material composing the adhesive is formed also on the surface of an optical element on which the light ray transmitted in the optical waveguide is emitted or made incident, and the optical waveguide and the optical element are fixed by the adhesive formed between the first region and the second region.
- US 2005/0147360 A1 refers to a vertical cavity surface emitting laser (VCSEL) module including a substrate provided with an etched region formed on a lower surface thereof, a plurality of layers, for photoproduction, laminated on an upper surface of the substrate, and a VCSEL for emitting the light upwards and downwards, wherein the VCSEL module monitors the output of the VCSEL by detecting the light emitted downwards from the VCSEL.
- VCSEL vertical cavity surface emitting laser
- JP 2007187870 refers to an optical element mounted which transmits or receives an optical signal in the direction perpendicular to a substrate; a cladding layer is formed on the substrate so that the above optical element is embedded therein; a core is formed on the cladding layer; and also a reflecting surface, which propagates the optical signal from the optical element to the core or propagates the optical signal from the core to the optical element, is formed on the core in the location of the above optical element.
- US 2001/0031117 A1 refers to optoelectronic packages comprising both an optical array and base chip.
- the array and base chip are aligned and coupled using a combination of V-grooves, wick stops, and alignment spheres (e.g., precision ball bearings).
- the array and base chip are passively aligned by disposing an optical fiber having an angled endface onto V-grooves in both the array and base chip.
- the base chip typically comprises an optical surface device, such as a vertical cavity, surface emitting laser or photodetector.
- US 4,936,808 seems to show some structural resemblance with the submount arrangement according to the invention, US 4,936,808 does not describe VCSEL arrays and does not recognize the problem of vertical distance and optical coupling losses because LED light is not coupled into a light coupling device. The skilled person hence cannot get inspired by US 4,936,808 to solve a problem of vertical distance to light coupling devices and minimizing optical coupling losses between VCSELs and light coupling devices.
- EP 1 786 043 entitled “Semiconductor Device and Manufacturing Method of Semiconductor Device” describes an arrangement for holding LEDs 102.
- the arrangement positions the LEDs on bumps 106 and contains rather high support walls that do not enable to position the LEDs at a distance of at most 30 micrometers from a light coupling device.
- Optical coupling and the losses resulting from the distance to a light coupling device are not relevant for LEDs and it is not suggested in EP 1 786 043 to replace the LEDs with VCSELs and re-dimension the support walls in order to tackle a problem of optical coupling losses there.
- the present invention refers to a method for producing a laser arrangement including a submount, said method comprising:
- the cavity or recess is filled, e.g. with a polymer or photoresist, and a metal seed layer is deposited to cover the entire substrate surface.
- a particular photoresist pattern is realized covering the entire surface except where the metal connections are needed.
- the metal connections are electroplated, and thereafter the photoresist is stripped and the thin seed layer is stripped everywhere except where the plated layer is deposited.
- the cavity fill material may or may not be removed.
- a photoresist is first applied and a patterned region is lithographically defined with a particular vertical or negative resist profile. Metal is then deposited everywhere but will be 'discontinuous' over the resist steps. The photoresist can then be stripped in a wet chemical bath and the metal deposited on top of the resist will be 'lifted off' and removed.
- Fig. 1 shows a state of the art VCSEL submount arrangement 100.
- the VCSEL 103 is mounted onto a flat submount 101.
- the submount 101 and VCSEL are electrically connected through bonding wires 104.
- the VCSEL/submount assembly is flipped.
- the VCSEL 103 and bonding wires 104 require the use of spacers 105 between the waveguide 106 and submount 101.
- the bonding wires 104 the light emitting surface of the VCSEL must respect a distance of at least 30 micrometers from the planar waveguide 106. As a consequence, optical coupling losses are high especially for single mode VCSELs.
- the distance between the light emitting surface of the VCSEL 203 and the waveguide 206 is reduced to at most 30 micrometers in the example result of the present invention of a VCSEL submount arrangement 200 illustrated by Fig. 2 .
- the VCSEL 203 mounted on a submount 201 with recess 202.
- the electrical connection between VCSEL 203 and submount 201 is realised through substantially flat metal connections 204.
- These metal connections 204 may be realized through a wafer-level processing technique, e.g. plating or lift-off processing. Thanks to the recess 202 and the substantially flat metal connections 204, the spacers 205 between planar waveguide 206 and and submount 201 can be reduced in height to at most 30 micrometers. As a direct consequence, optical coupling losses between VCSEL 203 and light coupling device 206 are reduced significantly especially for single mode VCSELs.
- Fig. 3 shows a variant result of the present invention of the submount arrangement 300.
- the submount 301 in Fig. 3 is dimensioned to hold an array of VCSELs 303 instead of a single VCSEL in recess 302.
- Substantially flat metal connections 304 similar to the metal connections 204 in the single VCSEL example of Fig. 2 , realize electrical connectivity between submount 301 and VCSEL array 303.
- the recess 302 and flat metal connections 304 allow the light emitting surface of the VCSELs 303 to be presented at close distance of a light coupling device, typically again at a distance below 30 micrometers.
- Fig. 4 shows a variant example result of the present invention of the submount arrangement 400, that allows to hermetically seal the cavity formed by the recess 402 and an eventual planar waveguide whereon the submount arrangement 400 is mounted.
- the hermetic sealing is made possible through a metal ring 405 on the front surface of the submount walls 401.
- An array of VCSELs 403 is again mounted in a recess 402 of the submount and flat metal connections 404 provide electrical conductivity between the submount walls 401 and the VCSELs 403.
- These substantially flat metal connections 404 are passing underneath the metal sealing ring 405 separated by an insulating material. This way, the metal connections 404 do not hinder hermetic sealing while they are kept at the front surface of the VCSEL submount. Similarly the sealing ring does not short circuit the different metal connections.
- Fig. 5 shows an example not forming part of the invention of the submount arrangement 500 that allows a hermetic seal between the cavity formed by the recess 502 and an eventual substrate containing a planar waveguide whereon the submount arrangement 500 is mounted.
- the connections are transferred to the back side of the submount, i.e. the top side in case the submount is flip-chip mounted on a horizontal planar waveguide.
- the VCSEL array 503 is again positioned in a recess 502 of the submount but the submount is now provided with sloped walls. These sloped walls enable to bring the substantially flat metal connections 504 to a bottom surface of the recess 502.
- Through-silicon vias 505 extending from the bottom surface of the recess 502 to the back side 506 of the submount enable to transfer the metal connections to the back surface 506.
- a metal ring provided on the front surface of the submount walls 501 enables hermetic sealing.
- Fig. 6 shows yet another example 600 of the submount arrangement not forming part of the invention that is suited for use with backside emitting VCSELs, i.e. VCSELs whose laser light is emitted at the side opposite to the side where the metal connections are provided.
- the substantially flat metal connections 604 are provided at the bottom surface of the recess 602. Through silicon vias lead the connections to the backside of the submount.
- a metal ring 605 is provided on top of the submount walls 601 enabling hermetic sealing.
- Fig. 7 shows the submount arrangement 600 of Fig. 6 with an array of backside emitting VCSELs 603. These VCSELs are flipped vertically into the cavity 602, their light emitting backside facing upwards.
- top, bottom, over, under, and the like are introduced for descriptive purposes and not necessarily to denote relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and embodiments of the invention are capable of operating according to the present invention in other sequences, or in orientations different from the one(s) described or illustrated above.
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Semiconductor Lasers (AREA)
- Optical Couplings Of Light Guides (AREA)
Description
- The present invention generally relates to mounting of Vertical-Cavity Surface-Emitting Lasers (VCSELs), a class of semiconductor laser devices that emits light perpendicular to a wafer's surface. More particularly, the invention concerns efficient flip-chip mounting of VCSELs reducing optical coupling losses and enabling passive alignment of the VCSELs.
- Individual VCSELs or VCSEL arrays are mounted by direct or indirect attachment of the VCSELs' substrate to another substrate containing a waveguide. The substrate may be glass, silicon, InP, GaAs, etc. VCSELs are typically flip-chip mounted, i.e. the VCSELs are vertically flipped in order to present laser light to a light coupling device, e.g. a planar waveguide, a mirror, an optical detector, a diffraction grating, etc. In most cases, prior to flip-chip, their non-light emitting surface is attached to a substrate (or submount) which is used to facilitate testing and burn-in. Use of such a submount enables easy testing and screening of defect VCSELs prior to flip-chip.
- A known way for flip-chip mounting of VCSELs is described in international patent application
WO 00/41281 WO 00/41281 - Electrical connectivity is required between the VCSEL and submount. Although not explicitly drawn or shown in Fig. 9-14 of
WO 00/41281 Fig. 6 ofWO 03/058777 Fig. 6 a submount (110) with recess or mounting well (112) wherein a VCSEL (82) is mounted. Bonding wires (80) provide electrical connectivity between the VCSEL and submount, but require locating spacers (114) for spacing any element such as a lens at a relative distance from the VCSEL. This is explicitly acknowledged in paragraph [0032] ofWO 03/058777 - Mounting VCSELs as learned from the individual or combined teaching of
WO 00/41281 WO 03/058777 Fig. 1 . As a result, a distance of at least 30 micrometers and usually more than 50 micrometers extending from the light emitting surface of the VCSEL must be kept free. This minimum distance of 30 micrometers to any light coupling device results in high optical coupling losses unless a lens is used. The distance and consequently also the optical coupling losses are even bigger when a flat substrate is used as suggested by Fig. 9-12 ofWO 00/41281 WO 00/41281 - Another drawback resides in the alignment between VCSEL and light coupling device. One option is 'active alignment' where the VCSEL is powered up so that it emits light. As it is aligned over the light coupling device the amount of light actually coupled into the waveguide is measured to find the optimum position. Such active alignment involves measurements, is expensive and time consuming. Passive alignment relies on recognition of alignment marks on the two objects to be aligned and then placing of the objects in the correct position by aligning the sets of marks appropriately. Passive alignment is preferred but requires visual access to alignment marks on the light emitting surface of the VCSEL during flip chip. This is made impossible by
WO 00/41281 WO 00/41281 - United States Patent Application
US 2005/0013562 entitled "Optical Component and Manufacture Method of the Same" shows inFig. 5C a submount arrangement 13 for VCSELs 20.US 2005/0013562 aims at reducing the size and height of such submount arrangements, as is indicated in paragraph [0007] ofUS 2005/0013562 . - The arrangement 13 shown in
Fig. 5C ofUS 2005/0013562 is composed of several ceramic layers 131, wiring 16 between the ceramic layers 131, and a lens 11. Each of the ceramic layers 131 is at least 50 micrometers thick. The lens 11 has the aim to condense the beam emitted by VCSEL 20 and to compensate for the optical losses resulting from the vertical distance the light has to travel. - United States Patent
US 7,004,644 entitled "Hermetic Chip-Scale Package for Photonic Devices" describes a submount arrangement with submount 15 having a recess to hold VCSELs 11, 12 that serve to source or detect light to or from an optical fiber 25. The arrangement contains a bumpbonded window 13, and the bumps 16 are further provided with metal traces 28 that have a thickness of less than 5 microns. - Further,
EP 1 914 814 A1 refers to a method for producing a radiation-emitting optoelectronic component, a semiconductor chip is mounted by a first main area onto a carrier body and is electrically conductively connected at a first contact area to a first connection region, and a transparent electrically insulating encapsulation layer is applied to the chip and the carrier body. A first cutout in the encapsulation layer for at least partly uncovering a second contact area of the chip is produced, and a second cutout in the encapsulation layer for at least partly uncovering a second connection region of the carrier body is produced. Finally, an electrically conductive layer, which electrically conductively connects the second contact area of the semiconductor chip and the second connection region of the carrier body, is applied. - Further,
JP 2008090218 - Further,
US 2005/0147360 A1 refers to a vertical cavity surface emitting laser (VCSEL) module including a substrate provided with an etched region formed on a lower surface thereof, a plurality of layers, for photoproduction, laminated on an upper surface of the substrate, and a VCSEL for emitting the light upwards and downwards, wherein the VCSEL module monitors the output of the VCSEL by detecting the light emitted downwards from the VCSEL. - Further,
JP 2007187870 - Further,
US 2001/0031117 A1 refers to optoelectronic packages comprising both an optical array and base chip. The array and base chip are aligned and coupled using a combination of V-grooves, wick stops, and alignment spheres (e.g., precision ball bearings). The array and base chip are passively aligned by disposing an optical fiber having an angled endface onto V-grooves in both the array and base chip. The base chip typically comprises an optical surface device, such as a vertical cavity, surface emitting laser or photodetector. - It is an objective of the present invention to disclose a laser arrangement for VCSELs that overcomes the above mentioned drawbacks of the closest prior art solutions. More particularly, it is an objective of the present invention to disclose a laser arrangement for VCSELs that enables optical coupling losses to be minimised by reducing the distance between VCSEL surface and light coupling device below 30 micrometers. It is a further objective to avoid the use of expensive components like lenses that introduce alignment complexity and prevent passive alignment between VCSEL and light coupling device.
- United States Patent
US 4,936,808 entitled "Method and LED Array Head" describes a LED array arrangement. Such LED array arrangements are used for instance in printers and scanners. In such applications, it is key to reduce the horizontal distance between neighbouring LEDs in the LED array in order to increase the density of LEDs per surface unit and accordingly increase the achievable DPI resolution in printers and scanners where the LED arrays are used. Increasing the density of LEDs in LED arrays is also the problem dealt with inUS 4,936,808 as indicated in Col. 1, lines 49-58. The solution to increase LED density proposed inUS 4,936,808 lies in a simplified wiring between the LED electrodes and a ceramic substrate. This simplified wiring consists of a metal film 34 that interconnects electrode 5 and external wiring 22. - Although
US 4,936,808 seems to show some structural resemblance with the submount arrangement according to the invention,US 4,936,808 does not describe VCSEL arrays and does not recognize the problem of vertical distance and optical coupling losses because LED light is not coupled into a light coupling device. The skilled person hence cannot get inspired byUS 4,936,808 to solve a problem of vertical distance to light coupling devices and minimizing optical coupling losses between VCSELs and light coupling devices. - Also European Patent Application
EP 1 786 043 entitled "Semiconductor Device and Manufacturing Method of Semiconductor Device" describes an arrangement for holding LEDs 102. The arrangement positions the LEDs onbumps 106 and contains rather high support walls that do not enable to position the LEDs at a distance of at most 30 micrometers from a light coupling device. Optical coupling and the losses resulting from the distance to a light coupling device are not relevant for LEDs and it is not suggested inEP 1 786 043 to replace the LEDs with VCSELs and re-dimension the support walls in order to tackle a problem of optical coupling losses there. - The present invention refers to a method for producing a laser arrangement including a submount, said method comprising:
- providing a submount with a recess;
- providing at least one Vertical-Cavity Surface-Emitting Laser or VCSEL in the recess;
- depositing metal connections extending between an upper surface of said at least one VCSEL and an upper surface of said submount, wherein said recess is dimensioned to hold said at least one VCSEL such that said metal connections are substantially flat; and
- providing a planar waveguide light coupling device at a distance of at most 30 micrometers from a light emitting surface of said at least one VCSEL, wherein said step of depositing metal connections comprises a plating technique or a lift-off technique.
- In one embodiment, after placing the VCSEL in the submount cavity the cavity or recess is filled, e.g. with a polymer or photoresist, and a metal seed layer is deposited to cover the entire substrate surface. Using photolithography, a particular photoresist pattern is realized covering the entire surface except where the metal connections are needed. The metal connections are electroplated, and thereafter the photoresist is stripped and the thin seed layer is stripped everywhere except where the plated layer is deposited. Following creation of the metal connections the cavity fill material may or may not be removed.
- With lift-off, a photoresist is first applied and a patterned region is lithographically defined with a particular vertical or negative resist profile. Metal is then deposited everywhere but will be 'discontinuous' over the resist steps. The photoresist can then be stripped in a wet chemical bath and the metal deposited on top of the resist will be 'lifted off' and removed.
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Fig. 1 illustrates a laser arrangement for mounting VCSEL(s) according to the prior art; -
Fig. 2 illustrates a first example of a result covered by the method according to independent claim 1 being a laser arrangement, whereon a flip-chip VCSEL is mounted; -
Fig. 3 illustrates a second example of a result covered by the method according to independent claim 1 being a laser arrangement, whereon an array of VCSELs is mounted; -
Fig. 4 . illustrates a third example of a result covered by the method according to independent claim 1 being a laser arrangement with metal ring enabling hermetic sealing; -
Fig. 5 illustrates a example not forming part of the invention with metal ring, slope-walled recess and through-vias; -
Fig. 6 illustrates a example of a laser arrangement not forming part of the invention, for backside emitting VCSELs; and -
Fig. 7 is a second illustration of the example ofFig. 6 of the submount arrangement, with backside emitting VCSELs. -
Fig. 1 shows a state of the artVCSEL submount arrangement 100. TheVCSEL 103 is mounted onto aflat submount 101. Thesubmount 101 and VCSEL are electrically connected throughbonding wires 104. In order to present laser light to aplanar waveguide 106 the VCSEL/submount assembly is flipped. TheVCSEL 103 andbonding wires 104 require the use ofspacers 105 between thewaveguide 106 andsubmount 101. As a result of thebonding wires 104, the light emitting surface of the VCSEL must respect a distance of at least 30 micrometers from theplanar waveguide 106. As a consequence, optical coupling losses are high especially for single mode VCSELs. - The distance between the light emitting surface of the
VCSEL 203 and thewaveguide 206 is reduced to at most 30 micrometers in the example result of the present invention of aVCSEL submount arrangement 200 illustrated byFig. 2 . TheVCSEL 203 mounted on asubmount 201 withrecess 202. The electrical connection betweenVCSEL 203 andsubmount 201 is realised through substantiallyflat metal connections 204. Thesemetal connections 204 may be realized through a wafer-level processing technique, e.g. plating or lift-off processing. Thanks to therecess 202 and the substantiallyflat metal connections 204, thespacers 205 betweenplanar waveguide 206 and andsubmount 201 can be reduced in height to at most 30 micrometers. As a direct consequence, optical coupling losses betweenVCSEL 203 andlight coupling device 206 are reduced significantly especially for single mode VCSELs. -
Fig. 3 shows a variant result of the present invention of thesubmount arrangement 300. Thesubmount 301 inFig. 3 is dimensioned to hold an array of VCSELs 303 instead of a single VCSEL inrecess 302. Substantiallyflat metal connections 304, similar to themetal connections 204 in the single VCSEL example ofFig. 2 , realize electrical connectivity betweensubmount 301 and VCSEL array 303. Therecess 302 andflat metal connections 304 allow the light emitting surface of the VCSELs 303 to be presented at close distance of a light coupling device, typically again at a distance below 30 micrometers. -
Fig. 4 shows a variant example result of the present invention of thesubmount arrangement 400, that allows to hermetically seal the cavity formed by therecess 402 and an eventual planar waveguide whereon thesubmount arrangement 400 is mounted. The hermetic sealing is made possible through ametal ring 405 on the front surface of thesubmount walls 401. An array ofVCSELs 403 is again mounted in arecess 402 of the submount andflat metal connections 404 provide electrical conductivity between thesubmount walls 401 and theVCSELs 403. These substantiallyflat metal connections 404 are passing underneath themetal sealing ring 405 separated by an insulating material. This way, themetal connections 404 do not hinder hermetic sealing while they are kept at the front surface of the VCSEL submount. Similarly the sealing ring does not short circuit the different metal connections. -
Fig. 5 shows an example not forming part of the invention of thesubmount arrangement 500 that allows a hermetic seal between the cavity formed by therecess 502 and an eventual substrate containing a planar waveguide whereon thesubmount arrangement 500 is mounted. In this alternative example , the connections are transferred to the back side of the submount, i.e. the top side in case the submount is flip-chip mounted on a horizontal planar waveguide. TheVCSEL array 503 is again positioned in arecess 502 of the submount but the submount is now provided with sloped walls. These sloped walls enable to bring the substantiallyflat metal connections 504 to a bottom surface of therecess 502. Through-silicon vias 505 extending from the bottom surface of therecess 502 to theback side 506 of the submount enable to transfer the metal connections to theback surface 506. A metal ring provided on the front surface of thesubmount walls 501 enables hermetic sealing. -
Fig. 6 shows yet another example 600 of the submount arrangement not forming part of the invention that is suited for use with backside emitting VCSELs, i.e. VCSELs whose laser light is emitted at the side opposite to the side where the metal connections are provided. The substantiallyflat metal connections 604 are provided at the bottom surface of therecess 602. Through silicon vias lead the connections to the backside of the submount. Ametal ring 605 is provided on top of thesubmount walls 601 enabling hermetic sealing. -
Fig. 7 shows thesubmount arrangement 600 ofFig. 6 with an array ofbackside emitting VCSELs 603. These VCSELs are flipped vertically into thecavity 602, their light emitting backside facing upwards. - Although the present invention has been illustrated by reference to specific embodiments, it will be apparent to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied with various changes and modifications without departing from the scope thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. In other words, it is contemplated to cover any and all modifications, variations or equivalents that fall within the scope of the basic underlying principles and whose essential attributes are claimed in this patent application. It will furthermore be understood by the reader of this patent application that the words "comprising" or "comprise" do not exclude other elements or steps, that the words "a" or "an" do not exclude a plurality, and that a single element, such as a computer system, a processor, or another integrated unit may fulfil the functions of several means recited in the claims. Any reference signs in the claims shall not be construed as limiting the respective claims concerned. The terms "first", "second", third", "a", "b", "c", and the like, when used in the description or in the claims are introduced to distinguish between similar elements or steps and are not necessarily describing a sequential or chronological order. Similarly, the terms "top", "bottom", "over", "under", and the like are introduced for descriptive purposes and not necessarily to denote relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and embodiments of the invention are capable of operating according to the present invention in other sequences, or in orientations different from the one(s) described or illustrated above.
Claims (1)
- A method for producing a laser arrangement (200; 300) including a submount (201, 301), said method comprising:- providing a submount (201;301) with a recess (202, 302);- providing at least one Vertical-Cavity Surface-Emitting Laser or VCSEL (203, 303) in the recess (202; 302);- depositing metal connections (204; 304) extending between an upper surface of said at least one VCSEL (203, 303) and an upper surface of said submount (201; 301), wherein said recess (202; 302) is dimensioned to hold said at least one VCSEL (203; 303) such that said metal connections (204; 304) are substantially flat; and- providing a planar waveguide light coupling device (206) at a distance of at most 30 micrometers from a light emitting surface of said at least one VCSEL (203,303),wherein said step of depositing metal connections (204; 304) comprises a plating technique or a lift-off technique.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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EP11160547.3A EP2506370B1 (en) | 2011-03-30 | 2011-03-30 | A submount arrangement for VCSELs |
DK11160547.3T DK2506370T3 (en) | 2011-03-30 | 2011-03-30 | Submount device for VCSELs |
PCT/EP2011/072281 WO2012130345A1 (en) | 2011-03-30 | 2011-12-09 | Vcsel with submount arrangement |
Applications Claiming Priority (1)
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EP11160547.3A EP2506370B1 (en) | 2011-03-30 | 2011-03-30 | A submount arrangement for VCSELs |
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EP2506370A1 EP2506370A1 (en) | 2012-10-03 |
EP2506370B1 true EP2506370B1 (en) | 2015-10-28 |
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EP11160547.3A Active EP2506370B1 (en) | 2011-03-30 | 2011-03-30 | A submount arrangement for VCSELs |
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EP (1) | EP2506370B1 (en) |
DK (1) | DK2506370T3 (en) |
WO (1) | WO2012130345A1 (en) |
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EP2746828B1 (en) | 2012-12-19 | 2019-08-21 | Huawei Technologies Co., Ltd. | Optical interposer |
JP6929103B2 (en) * | 2017-04-05 | 2021-09-01 | 日本ルメンタム株式会社 | Optical module |
CN109449754B (en) * | 2018-11-27 | 2023-12-01 | 佛山市国星半导体技术有限公司 | Vertical cavity surface emitting laser and manufacturing method thereof |
US11002926B1 (en) | 2019-11-07 | 2021-05-11 | Hewlett Packard Enterprise Development Lp | Wavelength division multiplexing optical module |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010031117A1 (en) * | 2000-04-07 | 2001-10-18 | Steinberg Dan A. | Methods and devices for coupling optoelectronic packages |
US20050147360A1 (en) * | 2004-01-02 | 2005-07-07 | Kyu-Sub Kwak | Vertical cavity surface emitting laser module |
JP2007187870A (en) * | 2006-01-13 | 2007-07-26 | Hitachi Cable Ltd | Optical module comprising structure of optical element embedded in substrate |
JP2008090218A (en) * | 2006-10-05 | 2008-04-17 | Matsushita Electric Ind Co Ltd | Optical element module |
Family Cites Families (7)
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KR910006706B1 (en) * | 1988-12-12 | 1991-08-31 | 삼성전자 주식회사 | Manufacturing method of light emitted diode array head |
US6588949B1 (en) | 1998-12-30 | 2003-07-08 | Honeywell Inc. | Method and apparatus for hermetically sealing photonic devices |
US7004644B1 (en) * | 1999-06-29 | 2006-02-28 | Finisar Corporation | Hermetic chip-scale package for photonic devices |
US6853007B2 (en) | 2001-12-28 | 2005-02-08 | Finisar Corporation | Submount for vertical cavity surface emitting lasers and detectors |
JP2005038956A (en) * | 2003-07-17 | 2005-02-10 | Matsushita Electric Ind Co Ltd | Optical component and manufacturing method thereof |
DE102004050371A1 (en) * | 2004-09-30 | 2006-04-13 | Osram Opto Semiconductors Gmbh | Optoelectronic component with a wireless contact |
JP5209177B2 (en) * | 2005-11-14 | 2013-06-12 | 新光電気工業株式会社 | Semiconductor device and manufacturing method of semiconductor device |
-
2011
- 2011-03-30 EP EP11160547.3A patent/EP2506370B1/en active Active
- 2011-03-30 DK DK11160547.3T patent/DK2506370T3/en active
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010031117A1 (en) * | 2000-04-07 | 2001-10-18 | Steinberg Dan A. | Methods and devices for coupling optoelectronic packages |
US20050147360A1 (en) * | 2004-01-02 | 2005-07-07 | Kyu-Sub Kwak | Vertical cavity surface emitting laser module |
JP2007187870A (en) * | 2006-01-13 | 2007-07-26 | Hitachi Cable Ltd | Optical module comprising structure of optical element embedded in substrate |
JP2008090218A (en) * | 2006-10-05 | 2008-04-17 | Matsushita Electric Ind Co Ltd | Optical element module |
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WO2012130345A1 (en) | 2012-10-04 |
DK2506370T3 (en) | 2016-01-18 |
EP2506370A1 (en) | 2012-10-03 |
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