EP2319022A1 - Wert- und/oder sicherheitsdokument sowie verfahren zur verifikation - Google Patents
Wert- und/oder sicherheitsdokument sowie verfahren zur verifikationInfo
- Publication number
- EP2319022A1 EP2319022A1 EP09777457A EP09777457A EP2319022A1 EP 2319022 A1 EP2319022 A1 EP 2319022A1 EP 09777457 A EP09777457 A EP 09777457A EP 09777457 A EP09777457 A EP 09777457A EP 2319022 A1 EP2319022 A1 EP 2319022A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- value
- security
- stack
- security document
- logic circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012795 verification Methods 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000007639 printing Methods 0.000 claims description 3
- 238000012545 processing Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000005679 Peltier effect Effects 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003203 everyday effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000008447 perception Effects 0.000 description 1
- 229920000767 polyaniline Polymers 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G07—CHECKING-DEVICES
- G07D—HANDLING OF COINS OR VALUABLE PAPERS, e.g. TESTING, SORTING BY DENOMINATIONS, COUNTING, DISPENSING, CHANGING OR DEPOSITING
- G07D7/00—Testing specially adapted to determine the identity or genuineness of valuable papers or for segregating those which are unacceptable, e.g. banknotes that are alien to a currency
- G07D7/01—Testing electronic circuits therein
Definitions
- the present invention relates to a value and / or security document having a preferably leaf-shaped body and an electrical circuit arranged in and / or on the body and at least two connecting elements arranged in and / or on the body and electrically connected to the circuit.
- the invention further relates to a method for verifying a stack of such value and / or security documents.
- the body of a value and / or security document may be formed in one piece or as a layer structure.
- connecting elements e.g. for the input of an electrical voltage or information serve electrically conductive contact surfaces, which are arranged on the surface of the respective security and / or security document. The contact surfaces are connected to the electrical circuit.
- a value and / or security document is known, on which a printed electrical circuit is provided.
- a Seebeck or Peltier element is provided which serves to verify a single security and / or security document.
- the electrical energy generated by the Seebeck element is used to supply a likewise belonging to the electrical circuit output or transmission unit, for example in the form of an organic light emitting diode.
- the element based on the Peltier effect is for it used, for example in a likewise arranged on the security document thermochromic color to produce a color change due to the temperature difference generated by the Peltier element.
- the object of the present invention is therefore to provide a value and / or security document that allows the verification and / or counting of a plurality of value and / or security documents at the same time. Accordingly, the object is also to provide a method for verification of a variety of value and / or security documents.
- the above object is achieved by a value and / or security document in which the connecting elements are provided such that in a stacking arrangement of a plurality of value and / or security documents one above the other, the connecting elements of adjacent value and / or security documents are electrically connected to one another and in which the circuit is designed as a logic circuit such that a verification of the value and / or security documents contained in the stack arrangement is made possible.
- the verification of the value and / or security documents contained in the stack arrangement is preferably carried out by inputting on the top side and / or bottom side of the stack arrangement an input information or a multiplicity of input information, which is input by each logic circuit of each individual value. and / or security document, preferably one after the other.
- the processed information which is preferably received on the respective other side of the stack arrangement, is then used to verify the value and / or security document stack.
- each value and / or security document has a parallel interface in the form of at least two electrically conductive connecting elements, in each case on its upper side and underside, with which it conducts electricity either with further value and / or security documents or with it with electrical conductivity can be connected to a verification device which generates the input information or the input information or receives the information (output information) which is passed on to the other side of the stack of the value and / or security documents and preferably processed.
- the electrical circuit designed as a logic circuit it is possible for a piece of information entered on one side of the stack to be stored in each value and / or security document of the stack by means of at least one simple mathematical operation (eg adding, subtracting, multiplying, dividing, exponentiating, logarithmizing, inverting), which is carried out in the logic circuit of each security and / or security document of the stack equally - if this is not forged, to be modified so that due to processed, received information can be made a statement about whether there is at least one forged value and / or security document in the stack. In certain embodiments of the present invention explained below, even a statement about the number of forged value and / or security documents in the stack is possible.
- simple mathematical operation eg adding, subtracting, multiplying, dividing, exponentiating, logarithmizing, inverting
- the logic circuit has no memory, but only elements which serve to process input information by means of at least one mathematical operation.
- such a logic circuit is cost-effective and, on the other hand, very tamper-proof, since, for want of a memory, it contains no information that can be spied out.
- the electrical circuit formed as a logic circuit it is also possible to count a stack of documents, in particular to check a predetermined document stack for completeness. It can be very, for example be quickly distinguished between a number of 99, 100 and 101 documents.
- the connecting elements of adjacent security and / or security documents of a stack are electrically connected directly to one another in a simple manner, so that in this preferred exemplary embodiment the connecting elements are arranged on mutually opposite sides of the body of the security and / or security document and as electrically conductive, ie galvanic, preferably metallized, contacts, in particular contact surfaces are formed.
- At least one connecting element is formed at least as part of a hologram and / or a security thread.
- the execution of at least one connecting element as a metallized security thread and / or metallized hologram patch is conceivable.
- a cost-effective combination of so-called public-feature security features such as security thread and hologram, and verification means such as logic circuit with connecting elements is possible.
- a motif arranged on the security and / or security document is e.g. in the form of an image and / or a caption makes the perception of the connecting elements more difficult.
- a motif can be formed both by the security thread and / or the hologram and / or by other means, e.g. a print, be realized.
- a particularly simple logic circuit can be realized by having at least one NOT or at least one XOR gate. The same applies to a logic circuit according to the invention which provides at least one through-connection.
- the plated-through hole may also be preferred here be formed at least as part of a security thread and / or hologram patches.
- the logic circuit is designed such that it processes digital information for verification of the value and / or security document, preferably by means of at least one mathematical operation (examples see above).
- this digital information is entered, for example, on top of the stack of value and / or security documents, and the digital information processed by the individual members of the stack is output on the bottom of the stack and the authenticity of the value and / or security contained in the stack / or security documents investigated.
- the body of the security and / or security document advantageously (n + 2) x2 connectors, at least 2 vias, 1 NOT gate, (n-1) XOR gate and (n-2) AND gate on (for all n> 2).
- the number of vias is at least n + 2 if the logic circuit is located on the top or bottom of the body of the security and / or security document. If the logic circuit is located in an inner layer of the value and / or security document, 2 vias from the top to the bottom and n vias from the top to the level of the logic circuit and n vias from the level of the logic circuit to the bottom are needed.
- the size of the bundle of value and / or security documents is estimated by estimating the approximate number of documents, for example
- Example to ⁇ 10% of the number so the determination of the exact number or the verification of the authenticity of the documents with comparatively few Components are made.
- n bits 2 n + 3 security and / or security documents can be counted and verified.
- An estimate of the number of security documents can be made, for example, about the thickness of the document bundle.
- the logic circuit is configured to perform an incrementation, i. a stepwise increase or decrease by a certain predetermined value, e.g. causes an increase by the value of 1, an input digital information or an inversion of the information.
- Inversion is understood to mean a process that involves a reversal of the information.
- the inversion is preferably done bitwise, i. 0 becomes 1 and 1 becomes 0 for every single bit of the input signal.
- a value and / or security document according to the present invention can be produced particularly simply if the logic circuit and / or the connection elements are produced by means of a printing method.
- the above object is also achieved by a method in which first of all the stack, starting from the top and / or bottom of the stack, is subjected to a mechanical pressure extending over at least part of the surface of the respective side, wherein each value and / or security document of the stack is arranged such that it is electrically conductively connected to the respective adjacent value and / or security document via respectively arranged on the top and bottom, opposing connecting elements, and then on the top and / or Un - page of the stack digital input information with a number of n bits (n is an integer and ⁇ 1) are inputted, and on the other side of the stack the output output information is received and evaluated for verification of the value and / or security documents contained in the stack.
- the sides of the stack are referred to as top and bottom, respectively, which extend substantially perpendicular to the direction in which the security and / or security documents are stacked in the stack. As a result, the top and bottom of the stack face each other.
- the pressure applied to the top and / or bottom of the stack causes the juxtaposed connecting elements of adjacent security and / or security documents of the stack to contact one another and thus be connected to one another in an electrically conductive manner. Subsequently, a digital input information e.g. be entered on the top of the stack.
- a digital input information e.g. be entered on the top of the stack.
- the information about the stack, of the stack and between the individual security and / or security documents can also be transmitted without contact (RFID).
- RFID alternating current to direct current
- the input information is thus processed by each individual logic circuit of the value and / or security documents, ie, as a rule, changed, and finally output in this example on the bottom of the stack.
- the output signal (output information) can now be checked to have the correct value, ie, whether the value and / or security documents of the stack are all genuine.
- the number of value and / or security documents in the stack corresponds to a certain fixed number.
- the entered information is not processed correctly so that an incorrect value is output on the bottom of the stack.
- the latter can then be checked for authenticity individually, ie each value and / or security document separately, for authenticity.
- At least one second digital input information different in value from the first input information is input, and the corresponding second output information is received, and additionally with respect to the verification of the one in the stack evaluated value and / or security documents evaluated. This means that the digital input information varies during the verification and the corresponding resulting variation of the output information is received and evaluated with regard to verifying the value and / or security documents contained in the stack.
- the logic circuit is limited to a simple contact, the verification can only take place via the presence of a signal or the resistance of the stack of value and / or security documents. It should be noted, however, that the particular variable by resistance variable contact resistance between the security and / or the security documents do not allow an accurate measurement, so that an accurate determination of the number of documents is not possible. Furthermore, such a feature provides little protection against counterfeiting and falsification.
- the value of incrementing the logic of the security and security document is dependent on its nomimal value.
- a banknote with the nominal value 5 increments the information by 1, a banknote with the nominal value 50 by 10 and a banknote of nominal value 500 by 100.
- a banknote with the nominal value 5 increments the information by 1
- a banknote with the nominal value 50 by 10 increments the information by 1
- a banknote with the nominal value 50 by 10 increments the information by 1
- a banknote with the nominal value 50 by 10 increments the information by 1
- a banknote with the nominal value 50 by 10 increments the information by 1
- a banknote with the nominal value 50 by 10 increments the information by 1
- a banknote with the nominal value 50 by 10 increments the information by 10
- a banknote with the nominal value 500 by 100 increments the information by 1
- a banknote with the nominal value 50 by 10 increments the information by 1
- a banknote with the nominal value 50 by 10 increments the information by 1
- a banknote with the nominal value 50 by 10 increments the information by 1
- FIG. 1 shows a cross section of a first embodiment of a security and / or security document according to the invention
- FIG. 2 shows a cross section of a stack of value and / or security documents according to FIG. 1, FIG.
- FIG. 3 shows a cross-section of a second exemplary embodiment of a value and / or security document according to the invention
- FIG. 4 shows a cross section of a third exemplary embodiment of a value and / or security document according to the invention
- Fig. 5 shows an example of the structure of an XOR gate
- Fig. 6 is a diagram illustrating the number of pads, transistors and distinguishable states when using a Verificationssignals with a number of bits plotted on the x-axis.
- the contact surfaces 31, 32, 33, 41, 42, 43 are each formed as metallized contact surfaces.
- the contact surfaces 31, 32 and 33 or 41, 42 and 43 each form an interface, wherein the interface on the upper side 21 and the interface on the underside 22 of the sheet-like body are connected in parallel to each other.
- the contact surfaces 31 and 41 and 33 and 43 are connected to each other via a via 4 and 5, respectively.
- the logic circuit 7 is composed of a resistor 8 and a transistor 9, wherein the input of the resistor 8 with the contact surface 31 and the contact surface 41 and the output of the resistor 8 is connected to the contact surface 42.
- the GATE of the transistor 9 is connected to the pad 32.
- the contact surfaces 33 and 43 are located at the SOURCE terminal of the transistor 9, while the output of the resistor 8 and the pad 42 are connected to the DRAIN terminal of the transistor 9.
- the logic circuit 7 may be arranged on the upper side, the underside and / or one or more inner layers of the document 2.
- the individual components of the logic circuit 7 are preferably arranged perpendicular to the plane of the drawing in a plane of the document.
- the logic circuit indicated in FIG. 1, which is designed as a NOT gate 7, causes a digital input information S1 with the value 1 (high signal), which is input via the contact surface 32, to be converted to a digital 0 (low-order signal). Signal) which is output at the pad 42, and vice versa.
- the contact surfaces 31 and 41 of adjacent banknotes are connected to each other and to the positive pole of the voltage source via the contact surface 31 of the uppermost banknote.
- the likewise connected contact surfaces 33, 43 are connected to the ground (negative pole) of the voltage source.
- the overlapping, adjacent and electrically connected contact surfaces 32, 42 of adjacent banknotes cause the information issued by one banknote, which is located further up in the present example, to be forwarded to the next banknote lying below in the example.
- a digital high signal (value 1) input to the center pad 32 on the top of the stack from the uppermost banknote logic circuit becomes a digital 0, from 0 the second banknote back to a digital 1, etc., and finally through the logic circuitry the lowermost banknote processes to a digital 1 which is output at the bottom via the pad 42 as an output signal S7 (output signal).
- the digital high signal (value 1) input at the middle contact surface 32 on the upper side of the stack is also switched to a low signal (value 0) and the change of the output signal S7 at the contact surface 42 is observed. In this way, the active switching behavior of the document stack can be verified.
- the logic circuit 7 ' which is arranged, for example, in the body 2 1 , consists of a parallel connection of an XOR and a NOT gate.
- On the upper side 21 'and the lower side 22' are each four contact surfaces 31, 32, 33, 34 and 41, 42, 43, 44 are arranged, wherein the contact surfaces 32 and 42 and 34 and 44 for input and output of signals serve.
- the logic circuit provided in the second embodiment processes a digital input information of 2 bits, each bit as signal S11 or S12 on the upper side of the value and / or Security document is entered.
- the processed digital signal is also output as an output signal consisting of 2 bits S21 and S22 on the bottom of the bill via the pads 42 and 44.
- the logic circuit 7 therefore increments 2 bits of digital information by the value 1 and requires a total of eight contact surfaces 31, 32, 33, 34, 41, 42, 43, 44 and nine transistors or seven transistors and two diodes in the context of XOR and the NOT gate existing circuit.
- a circuit diagram for the construction of an XOR circuit is shown in FIG.
- Fig. 4 third embodiment of a security and / or security document according to the invention differs from the embodiment shown in Fig. 3 in that two additional contact surfaces (each a contact surface 35 on the top 21 "and a contact surface)
- the logic circuit 7 " consists of the circuit shown in FIG. 3 and an additional further XOR gate 12 arranged parallel to the NOT and XOR gate, and an upstream one AND gates 13.
- a digital input information consisting of 3 bits can be processed, which is input at the contact surfaces 32, 34 and 35 as signal S11, S12 and S13 ,
- the circuit 7 " is composed of at least 17 transistors in a simple case
- the input digital information S11, S12, S13 are processed by the logic circuit 7" of the third exemplary embodiment of the value and / or security document as follows:
- the number of transistors and / or diodes used in the logic circuit also depends on the technology used (MOS, CMOS).
- the logic circuit shown requires 16 contact surfaces and 49 transistors.
- the relationship between distinguishable states, required contact areas and transistors necessary for the realization of the circuit is shown in FIG.
- the x-axis indicates the number of bits used for the information processed by the logic circuit.
- the respective information with the specified number of bits can be used to distinguish the number of states that are plotted in the curve marked with crosses and on the right y axis.
- the number of contact areas (relevant y-axis: left) shown by the dashed line and the minimum number of transistors indicated by the solid line is required (also relevant y-axis: left).
- a resistor, a transistor, for example made of polyaniline, as well as six contact surfaces are preferably produced by means of a printing method, and three through-contacts are realized.
- the third via may be provided at either the contact pad 32 or the pad 42 when the logic circuitry is on the bottom or top of the document is arranged.
- this contacting with a security thread since it must be prevented that there is a short circuit between the via and the opposite contact surface.
- the plated-through holes can be overprinted or glued over with an insulator, for example.
- a through-connection can be produced, for example, by introducing a perforation, for example by means of a laser, and filling it with a metallic material.
- a via can also be produced by applying silver-conducting paste to the surface, preferably on both sides, of the security and / or security document. Due to the pore structure of the body of the security and / or security document, which preferably consists of a paper material, the application of silver conductive paste to the surface causes the body to soak, and thus a via.
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Credit Cards Or The Like (AREA)
- Inspection Of Paper Currency And Valuable Securities (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102008035969A DE102008035969A1 (de) | 2008-07-31 | 2008-07-31 | Wert- und/oder Sicherheitsdokument sowie Verfahren zur Verifikation |
| PCT/EP2009/005423 WO2010012436A1 (de) | 2008-07-31 | 2009-07-27 | Wert- und/oder sicherheitsdokument sowie verfahren zur verifikation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| EP2319022A1 true EP2319022A1 (de) | 2011-05-11 |
| EP2319022B1 EP2319022B1 (de) | 2013-04-03 |
Family
ID=41130389
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP09777457A Not-in-force EP2319022B1 (de) | 2008-07-31 | 2009-07-27 | Wert- und/oder sicherheitsdokument sowie verfahren zur verifikation |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP2319022B1 (de) |
| DE (1) | DE102008035969A1 (de) |
| WO (1) | WO2010012436A1 (de) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL1008929C2 (nl) * | 1998-04-20 | 1999-10-21 | Vhp Ugchelen Bv | Uit papier vervaardigd substraat voorzien van een geïntegreerde schakeling. |
| CN1589457B (zh) | 2001-12-21 | 2010-05-12 | 德国捷德有限公司 | 片材及用于制造和处理该片材的设备与方法 |
| DE20200358U1 (de) | 2002-01-10 | 2003-05-22 | Bundesdruckerei GmbH Rechts- und Patentangelegenheiten, 10969 Berlin | Wert- oder Sicherheitsdokument mit LED-Elementen |
| US7249709B2 (en) * | 2002-03-18 | 2007-07-31 | Koninklijke Philips Electronics N.V. | Holder for papers of value, and method of registering the contents thereof |
| DE10343546A1 (de) * | 2003-09-19 | 2005-09-01 | Giesecke & Devrient Gmbh | Blattdokument mit einem elektrischen Schaltkreis |
| DE102004003309A1 (de) | 2004-01-22 | 2005-08-11 | Giesecke & Devrient Gmbh | Blattdokument mit Chip und kapazitiven Kontaktmitteln |
-
2008
- 2008-07-31 DE DE102008035969A patent/DE102008035969A1/de not_active Ceased
-
2009
- 2009-07-27 EP EP09777457A patent/EP2319022B1/de not_active Not-in-force
- 2009-07-27 WO PCT/EP2009/005423 patent/WO2010012436A1/de not_active Ceased
Non-Patent Citations (1)
| Title |
|---|
| See references of WO2010012436A1 * |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2010012436A1 (de) | 2010-02-04 |
| DE102008035969A1 (de) | 2010-02-04 |
| EP2319022B1 (de) | 2013-04-03 |
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