EP2294571A1 - Nuanceur complexe avec système de mémoire cache de niveau 1 réparti et mémoire cache de niveau 2 centralisée - Google Patents

Nuanceur complexe avec système de mémoire cache de niveau 1 réparti et mémoire cache de niveau 2 centralisée

Info

Publication number
EP2294571A1
EP2294571A1 EP09755282A EP09755282A EP2294571A1 EP 2294571 A1 EP2294571 A1 EP 2294571A1 EP 09755282 A EP09755282 A EP 09755282A EP 09755282 A EP09755282 A EP 09755282A EP 2294571 A1 EP2294571 A1 EP 2294571A1
Authority
EP
European Patent Office
Prior art keywords
level
cache
cache system
shader
filter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP09755282A
Other languages
German (de)
English (en)
Other versions
EP2294571A4 (fr
Inventor
Anthony P. Delaurier
Mark Leather
Robert S. Hartog
Michael J. Mantor
Mark C. Fowler
Marcos P. Zini
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of EP2294571A1 publication Critical patent/EP2294571A1/fr
Publication of EP2294571A4 publication Critical patent/EP2294571A4/fr
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/005—General purpose rendering architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/30—Providing cache or TLB in specific location of a processing system
    • G06F2212/302—In image processor or graphics adapter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/455—Image or video data
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/121—Frame memory handling using a cache memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers

Definitions

  • the present invention is generally directed to computing operations performed in computing systems, and more particularly directed to graphics processing tasks performed in computing systems.
  • a graphics processing unit is a complex integrated circuit that is specially designed to perform graphics processing tasks.
  • a GPU can, for example, execute graphics processing tasks required by an end-user application, such as a video game application. In such an example, there are several layers of software between the end-user application and the GPU.
  • the end-user application communicates with an application programming interface (API).
  • API allows the end-user application to output graphics data and commands in a standardized format, rather than in a format that is dependent on the GPU.
  • Several types of APIs are commercially available, including DirectX® developed by Microsoft Corp. and OpenGL® developed by Silicon Graphics, Inc.
  • the API communicates with a driver.
  • the driver translates standard code received from the API into a native format of instructions understood by the GPU.
  • the driver is typically written by the manufacturer of the GPU.
  • the GPU then executes the instructions from the driver.
  • a GPU produces the pixels that make up an image from a higher level description of its components in a process known as rendering.
  • GPUs typically utilize a concept of continuous rendering by the use of pipelines to processes pixel, texture, and geometric data. These pipelines are often referred to as a collection of fixed function special purpose pipelines such as rasterizers, setup engines, color blenders, hieratical depth, texture mapping and programmable stages that can be accomplished in shader pipes or shader pipelines, "shader” being a term in computer graphics referring to a set of software instructions used by a graphic resource primarily to perform rendering effects.
  • GPUs can also employ multiple programmable pipelines in a parallel processing design to obtain higher throughput. A multiple of shader pipelines can also be referred to as a shader pipe array.
  • GPUs also support a concept known as texture mapping.
  • Texture mapping is a process used to determine the texture color for a texture mapped pixel through the use of the colors of nearby pixels of the texture, or texels.
  • the process is also referred to as texture smoothing or texture interpolation.
  • texture smoothing or texture interpolation.
  • high image quality texture mapping requires a high degree of computational complexity.
  • GPUs equipped with a Unified Shader also simultaneously support many types of shader processing, from pixel, vertex, primitive, surface and generalized compute are raising the demand for higher performance generalized memory access capabilities.
  • Texture filters rely on high speed access to local cache memory for pixel data.
  • the use of dedicated local cache memory for texture filters typically precludes the use of more general purpose shared memory. While general purpose shared memory is more flexible, it typically has slower response time and hence is less performant.
  • the present invention includes method and apparatus whereby a shader pipe texture filter utilizes a level one cache system as a primary method of storage but with the ability to have the level one cache system read and write to a level two cache system when necessary. While each level one cache system is associated with a particular shader pipe texture filter, level two cache memory has no such association and is therefore available to all level one cache systems. In addition, level one cache systems can allocate a defined area of memory to be sharable amongst other resources.
  • a level one cache system is configured with dual access so that two shader pipe texture filters have access to a single level one cache system.
  • more than one level two cache systems are configured to be accessible by each level one cache systems.
  • the communication between a level one cache system and a level two cache systems utilizes more than one memory channel thereby resulting in a greater data throughput.
  • one or more level one cache systems can allocate defined areas of memory to be shared amongst other resources, including other level one cache systems. In certain instances this approach will allow for quicker fetch times of texel data where the required data has already been moved from a level two cache system to a level one cache system.
  • FIG. 1 is a system diagram depicting an implementation of a single level one cache system with a single level two cache system.
  • FIG. 2 is a system diagram depicting an implementation of a plurality of level one and level two cache systems.
  • FIG. 3 is a system diagram depicting an implementation of a dual ported level one and a plurality of level two cache systems.
  • FIG. 4 is a flowchart depicting an implementation of a method for a shader filter cache system.
  • the present invention relates to a distributed level one cache system with a centralized level two cache system.
  • Each shader pipe texture filter has a dedicated level one cache system configured to provide read and write access to texel data contained within the level one cache system.
  • an embodiment indicates that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of one skilled in the art to incorporate such a feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
  • FIG. 1 is an illustration of a single level one cache system and a single level two cache system 100 according to an embodiment of the present invention.
  • System 100 comprises a single shader pipe texture filter 110 with an associated level one cache system 120 configured to communicate with a level two cache system 130 utilizing a wide channel memory bus 125.
  • the shader pipe texture filter 110 employs the concept of bilinear filtering to determine the color of a particular pixel.
  • the shader pipe texture filter 110 analyzes texel data for the four nearest pixels to the pixel in question.
  • the texel data for the four texels is then combined by a weighted average according to distance to calculate the desired result.
  • the texel data in question is retrieved from the level one cache system 120 that is associated with the current shader pipe texture filter 110.
  • level one cache system 120 issues a read request to level two cache system 130 for the desired texel data.
  • the required data is then copied from level two cache system 130 to level one cache system 120 in order to be analyzed and processed by shader pipe texture filter 1 10.
  • FIG. 2 is an illustration of multiple shader pipe texture filters with associated level one caches and multiple level two cache systems according to an embodiment of the present invention.
  • System 200 comprises one or more shader pipe texture filters, here represented as shader pipe texture filter 1 through shader pipe texture filter N, labeled 110-1 through HO-N, where "N" represents a positive integer greater than one.
  • System 200 also comprises level one cache systems associated with each shader pipe texture filter, here represented as Ll-I cache system through Ll-N cache system, labeled 120-1 through 120-N, where "N" represents a positive integer greater than one.
  • Ll-I cache system Ll-I cache system through Ll-N cache system
  • 120-1 through 120-N where "N” represents a positive integer greater than one.
  • wide channel memory bus 125 that links level one cache systems 120-1 through 120-N to a set of level two cache systems.
  • the level two cache system includes one or more level two cache systems, here represented as L2-1 cache system through L2-M cache system, where "M”
  • each shader pipe texture filter, 110-1 through 110-N needs to analyze the texel data for the four nearest pixels to the pixel in question. Therefore, the texel data in question for each shader pipe texture filter is retrieved from its associated level one cache system. As such, shader pipe texture filter 1, 110-1, issues a request for texel data to Ll-I cache system, 120-1. The remaining shader pipe texture filters will issue texel data requests in a similar manner.
  • level one cache system can issue a read request to the level two cache system 130 for the desired texel data.
  • one or more of the level one cache systems can allocate defined areas of memory to be shared amongst other resources, including other level one cache systems. In certain instances, this approach allows for quicker fetch times of texel data where the required data has already been moved from a level two cache system to a level one cache system.
  • FIG. 3 is an illustration of multiple shader pipe texture filters with associated dual-ported level one caches and multiple level two cache systems according to an embodiment of the present invention.
  • System 300 comprises one or more dual-ported level one cache systems, of which each supports up to two shader pipe texture filters, and a level two cache system.
  • a level one cache system supports up to two shader pipe texture filters for their requests of texel data.
  • each level one cache supports two shader pipe texture filters, as illustrated, as shader pipe texture filter A, 310, and shader pipe texture filter B, 312.
  • the level one caches, 320-1 through 320-N have access, via wide channel memory bus 125, to the level two cache system illustrated as L2-1 through L2-N, where N is a positive integer.
  • one or more of the level one cache systems can allocate defined areas of memory to be shared amongst other resources, including other level one cache systems. In certain instances, this approach allows for quicker fetch times of texel data where the required data has already been moved from a level two cache system to a level one cache system.
  • FIG. 4 is a flowchart depicting a method 400 whereby a shader pipe texture filter utilizes a level one cache system as a primary method of storage with the ability to access a level two cache when necessary.
  • Method 400 begins at step 402.
  • each level one cache system can allocate defined areas of memory as sharable amongst other resources.
  • a shader pipe texture filter issues a read or write command to its associated level one cache system.
  • the associated level one cache system retrieves or writes texel data, as appropriate.
  • each level one cache system can issue read and write requests to a level two cache system.
  • Method 400 concludes at step 412.
  • 3, and 4 can be implemented in software, firmware, or hardware, or using any combination thereof. If programmable logic is used, such logic can execute on a commercially available processing platform or a special purpose device.
  • HDL hardware description language
  • Verilog Verilog
  • VHDL hardware description language
  • the HDL-design can model the behavior of an electronic system, where the design can be synthesized and ultimately fabricated into a hardware device.
  • the HDL-design can be stored in a computer product and loaded into a computer system prior to hardware manufacture.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Graphics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Image Generation (AREA)
  • Processing Or Creating Images (AREA)

Abstract

Un filtre de texture de tuyau de nuanceur utilise un système de mémoire cache de niveau 1 en tant que procédé principal de mémorisation, mais le système de mémoire cache de niveau 1 a la capacité de lire et d'écrire dans un système de mémoire cache de niveau 2 lorsque cela est nécessaire. Le système de mémoire cache de niveau 1 communique avec le système de mémoire cache de niveau 2 par l'intermédiaire d'un large bus de mémoire de canal. De plus, le système de mémoire cache de niveau 1 peut être configuré pour prendre en charge des filtres de texture de tuyau de nuanceur doubles tout en maintenant un accès au système de mémoire cache de niveau 2. L’invention concerne également un procédé utilisant un système de mémoire cache de niveau 1 en tant que procédé principal de mémorisation, le système de mémoire cache de niveau 1 ayant la capacité d’écrire et de lire dans un système de mémoire cache de niveau 2 lorsque cela est nécessaire. De plus, des systèmes de mémoire cache de niveau 1 peuvent attribuer une zone définie de mémoire destinée à être partagée avec d'autres ressources.
EP09755282.2A 2008-05-30 2009-06-01 Nuanceur complexe avec système de mémoire cache de niveau 1 réparti et mémoire cache de niveau 2 centralisée Ceased EP2294571A4 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US5749208P 2008-05-30 2008-05-30
PCT/US2009/003317 WO2009145919A1 (fr) 2008-05-30 2009-06-01 Nuanceur complexe avec système de mémoire cache de niveau 1 réparti et mémoire cache de niveau 2 centralisée

Publications (2)

Publication Number Publication Date
EP2294571A1 true EP2294571A1 (fr) 2011-03-16
EP2294571A4 EP2294571A4 (fr) 2014-04-23

Family

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EP09755282.2A Ceased EP2294571A4 (fr) 2008-05-30 2009-06-01 Nuanceur complexe avec système de mémoire cache de niveau 1 réparti et mémoire cache de niveau 2 centralisée

Country Status (5)

Country Link
EP (1) EP2294571A4 (fr)
JP (1) JP5832284B2 (fr)
KR (1) KR101427409B1 (fr)
CN (1) CN102047316B (fr)
WO (1) WO2009145919A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110471943A (zh) * 2018-05-09 2019-11-19 北京京东尚科信息技术有限公司 实时数据统计装置和方法以及计算机可读存储介质
US11507527B2 (en) 2019-09-27 2022-11-22 Advanced Micro Devices, Inc. Active bridge chiplet with integrated cache

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Also Published As

Publication number Publication date
JP5832284B2 (ja) 2015-12-16
EP2294571A4 (fr) 2014-04-23
CN102047316B (zh) 2016-08-24
JP2011523745A (ja) 2011-08-18
WO2009145919A1 (fr) 2009-12-03
KR20110015034A (ko) 2011-02-14
CN102047316A (zh) 2011-05-04
KR101427409B1 (ko) 2014-08-07

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