EP2257900A4 - OPTIMIZING THE DESIGN AND LIBRARY OF INTEGRATED CIRCUITS - Google Patents

OPTIMIZING THE DESIGN AND LIBRARY OF INTEGRATED CIRCUITS

Info

Publication number
EP2257900A4
EP2257900A4 EP09709144A EP09709144A EP2257900A4 EP 2257900 A4 EP2257900 A4 EP 2257900A4 EP 09709144 A EP09709144 A EP 09709144A EP 09709144 A EP09709144 A EP 09709144A EP 2257900 A4 EP2257900 A4 EP 2257900A4
Authority
EP
European Patent Office
Prior art keywords
library
optimization
integrated circuit
circuit design
design
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP09709144A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP2257900A2 (en
Inventor
Andre Inacio Reis
Anders Bo Rasmussen
Vinicius Pazutti Correia
Ole Christian Andersen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nangate AS
Original Assignee
Nangate AS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nangate AS filed Critical Nangate AS
Publication of EP2257900A2 publication Critical patent/EP2257900A2/en
Publication of EP2257900A4 publication Critical patent/EP2257900A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/06—Power analysis or power optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/12—Timing analysis or timing optimisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
EP09709144A 2008-02-05 2009-02-05 OPTIMIZING THE DESIGN AND LIBRARY OF INTEGRATED CIRCUITS Withdrawn EP2257900A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US2622208P 2008-02-05 2008-02-05
PCT/US2009/033243 WO2009100237A2 (en) 2008-02-05 2009-02-05 Optimization of integrated circuit design and library

Publications (2)

Publication Number Publication Date
EP2257900A2 EP2257900A2 (en) 2010-12-08
EP2257900A4 true EP2257900A4 (en) 2012-10-17

Family

ID=40952683

Family Applications (1)

Application Number Title Priority Date Filing Date
EP09709144A Withdrawn EP2257900A4 (en) 2008-02-05 2009-02-05 OPTIMIZING THE DESIGN AND LIBRARY OF INTEGRATED CIRCUITS

Country Status (4)

Country Link
EP (1) EP2257900A4 (ja)
JP (1) JP5127935B2 (ja)
CN (1) CN101990671A (ja)
WO (1) WO2009100237A2 (ja)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102279899B (zh) * 2011-04-01 2013-05-01 无锡中科微电子工业技术研究院有限责任公司 对精简标准单元库进行优化的方法
CN102663175B (zh) * 2012-03-27 2013-11-06 苏州芯禾电子科技有限公司 一种射频无源器件三维模型的构建系统以及构建方法
KR101904417B1 (ko) * 2012-03-30 2018-10-08 삼성전자주식회사 반도체 집적 회로 및 그 설계 방법
CN107567622B (zh) * 2015-07-08 2021-06-25 慧与发展有限责任合伙企业 光子电路设计系统和计算机可读介质
US10528696B2 (en) * 2016-02-29 2020-01-07 Synopsys, Inc. Creating and reusing customizable structured interconnects
US10572615B2 (en) * 2017-04-28 2020-02-25 Synopsys, Inc. Placement and routing of cells using cell-level layout-dependent stress effects
CN107610569A (zh) * 2017-10-23 2018-01-19 宜宾学院 模拟电路实验设备及其所需电子元件的确定方法
CN108846160B (zh) * 2018-05-03 2023-03-10 上海华虹宏力半导体制造有限公司 标准单元库电路设计方法
TWI761750B (zh) * 2020-01-08 2022-04-21 國立雲林科技大學 類比電路效能自動化分析系統及其方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010010090A1 (en) * 1998-02-11 2001-07-26 Boyle Douglas B. Method for design optimization using logical and physical information
US20010032067A1 (en) * 1999-12-28 2001-10-18 Mahadevamurty Nemani Method and system for determining optimal delay allocation to datapath blocks based on area-delay and power-delay curves

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05120372A (ja) * 1991-10-25 1993-05-18 Nec Corp ゲートアレイの設計方式
US5956257A (en) * 1993-03-31 1999-09-21 Vlsi Technology, Inc. Automated optimization of hierarchical netlists
US6539536B1 (en) * 2000-02-02 2003-03-25 Synopsys, Inc. Electronic design automation system and methods utilizing groups of multiple cells having loop-back connections for modeling port electrical characteristics
JP2001265842A (ja) * 2000-03-21 2001-09-28 Katsumi Hashimoto 複合ゲート合成装置、複合ゲート合成プログラムを格納した記録媒体および半導体装置
DE10025583A1 (de) * 2000-05-24 2001-12-06 Infineon Technologies Ag Verfahren zur Optimierung integrierter Schaltungen, Vorrichtung zum Entwurf von Halbleitern und Programmobjekt zum Entwerfen integrierter Schaltungen
JP2003036280A (ja) * 2001-07-23 2003-02-07 Hitachi Ltd 設計用データライブラリ、半導体集積回路の設計方法、及び半導体集積回路の製造方法
US7496867B2 (en) * 2007-04-02 2009-02-24 Lsi Corporation Cell library management for power optimization

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010010090A1 (en) * 1998-02-11 2001-07-26 Boyle Douglas B. Method for design optimization using logical and physical information
US20010032067A1 (en) * 1999-12-28 2001-10-18 Mahadevamurty Nemani Method and system for determining optimal delay allocation to datapath blocks based on area-delay and power-delay curves

Also Published As

Publication number Publication date
WO2009100237A3 (en) 2009-11-05
JP2011525261A (ja) 2011-09-15
EP2257900A2 (en) 2010-12-08
WO2009100237A2 (en) 2009-08-13
JP5127935B2 (ja) 2013-01-23
CN101990671A (zh) 2011-03-23

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RIN1 Information on inventor provided before grant (corrected)

Inventor name: ANDERSEN, OLE CHRISTIAN

Inventor name: CORREIA, VINICIUS PAZUTTI

Inventor name: RASMUSSEN, ANDERS BO

Inventor name: REIS, ANDRE INACIO

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