WO2009100237A3 - Optimization of integrated circuit design and library - Google Patents

Optimization of integrated circuit design and library Download PDF

Info

Publication number
WO2009100237A3
WO2009100237A3 PCT/US2009/033243 US2009033243W WO2009100237A3 WO 2009100237 A3 WO2009100237 A3 WO 2009100237A3 US 2009033243 W US2009033243 W US 2009033243W WO 2009100237 A3 WO2009100237 A3 WO 2009100237A3
Authority
WO
WIPO (PCT)
Prior art keywords
cells
library
design
different
cell
Prior art date
Application number
PCT/US2009/033243
Other languages
French (fr)
Other versions
WO2009100237A2 (en
Inventor
Andre Inacio Reis
Anders Bo Rasmussen
Vinicius Pazutti Correia
Ole Christian Andersen
Original Assignee
Nangate A/S
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nangate A/S filed Critical Nangate A/S
Priority to JP2010546000A priority Critical patent/JP5127935B2/en
Priority to EP09709144A priority patent/EP2257900A4/en
Priority to CN2009801123097A priority patent/CN101990671A/en
Publication of WO2009100237A2 publication Critical patent/WO2009100237A2/en
Publication of WO2009100237A3 publication Critical patent/WO2009100237A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/06—Power analysis or power optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/12—Timing analysis or timing optimisation

Abstract

A method co-optimizes a design and a library in such a way to choose the best set of cells to implement the design. The method takes into account the idea of limiting the number of new cells while reducing target costs and respecting design constraints. The method chooses a minimum nearly optimum set of cells to optimize a design. This involves the simultaneous optimization of a cell-based design and a cell library used to implement it. The invention can produce only an optimized library for a specific application, when the circuit is disregarded. The method takes into account a set of new cells described as finalized cells or as virtual cells, possibly having different transistor topologies, different sizes, different logic functions, and/or different cell template than the original library.
PCT/US2009/033243 2008-02-05 2009-02-05 Optimization of integrated circuit design and library WO2009100237A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2010546000A JP5127935B2 (en) 2008-02-05 2009-02-05 Integrated circuit design and library optimization
EP09709144A EP2257900A4 (en) 2008-02-05 2009-02-05 Optimization of integrated circuit design and library
CN2009801123097A CN101990671A (en) 2008-02-05 2009-02-05 Optimization of integrated circuit design and library

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US2622208P 2008-02-05 2008-02-05
US61/026,222 2008-02-05

Publications (2)

Publication Number Publication Date
WO2009100237A2 WO2009100237A2 (en) 2009-08-13
WO2009100237A3 true WO2009100237A3 (en) 2009-11-05

Family

ID=40952683

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2009/033243 WO2009100237A2 (en) 2008-02-05 2009-02-05 Optimization of integrated circuit design and library

Country Status (4)

Country Link
EP (1) EP2257900A4 (en)
JP (1) JP5127935B2 (en)
CN (1) CN101990671A (en)
WO (1) WO2009100237A2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102279899B (en) * 2011-04-01 2013-05-01 无锡中科微电子工业技术研究院有限责任公司 Method for optimizing simplified standard unit library
CN102663175B (en) * 2012-03-27 2013-11-06 苏州芯禾电子科技有限公司 System and method for constructing three-dimensional model of radio-frequency passive device
KR101904417B1 (en) * 2012-03-30 2018-10-08 삼성전자주식회사 Semiconductor integrated circuit and method of designing the same
WO2017007470A1 (en) * 2015-07-08 2017-01-12 Hewlett Packard Enterprise Development Lp Photonic circuit design systems
DE112017001063T5 (en) * 2016-02-29 2018-12-06 Synopsys, Inc. Create and reuse customizable structured links
US10572615B2 (en) * 2017-04-28 2020-02-25 Synopsys, Inc. Placement and routing of cells using cell-level layout-dependent stress effects
CN107610569A (en) * 2017-10-23 2018-01-19 宜宾学院 The determination method of analogous circuit experiment equipment and its required electronic component
CN108846160B (en) * 2018-05-03 2023-03-10 上海华虹宏力半导体制造有限公司 Standard cell library circuit design method
TWI761750B (en) * 2020-01-08 2022-04-21 國立雲林科技大學 Automatic performance analysis system and method thereof for analog circuits

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5956257A (en) * 1993-03-31 1999-09-21 Vlsi Technology, Inc. Automated optimization of hierarchical netlists
US6735742B2 (en) * 2000-05-24 2004-05-11 Infineon Technologies Ag Method for optimizing a cell layout using parameterizable cells and cell configuration data

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05120372A (en) * 1991-10-25 1993-05-18 Nec Corp Designing system for gate array
US6286128B1 (en) * 1998-02-11 2001-09-04 Monterey Design Systems, Inc. Method for design optimization using logical and physical information
US6327552B2 (en) * 1999-12-28 2001-12-04 Intel Corporation Method and system for determining optimal delay allocation to datapath blocks based on area-delay and power-delay curves
US6539536B1 (en) * 2000-02-02 2003-03-25 Synopsys, Inc. Electronic design automation system and methods utilizing groups of multiple cells having loop-back connections for modeling port electrical characteristics
JP2001265842A (en) * 2000-03-21 2001-09-28 Katsumi Hashimoto Composite gate synthesis device, recording medium with composite gate synthesis program stored thereon, and semiconductor device
JP2003036280A (en) * 2001-07-23 2003-02-07 Hitachi Ltd Design data library, design method and manufacturing method of semiconductor integrated circuit
US7496867B2 (en) * 2007-04-02 2009-02-24 Lsi Corporation Cell library management for power optimization

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5956257A (en) * 1993-03-31 1999-09-21 Vlsi Technology, Inc. Automated optimization of hierarchical netlists
US6735742B2 (en) * 2000-05-24 2004-05-11 Infineon Technologies Ag Method for optimizing a cell layout using parameterizable cells and cell configuration data

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2257900A4 *

Also Published As

Publication number Publication date
WO2009100237A2 (en) 2009-08-13
CN101990671A (en) 2011-03-23
JP5127935B2 (en) 2013-01-23
EP2257900A2 (en) 2010-12-08
JP2011525261A (en) 2011-09-15
EP2257900A4 (en) 2012-10-17

Similar Documents

Publication Publication Date Title
WO2009100237A3 (en) Optimization of integrated circuit design and library
EP2245740B8 (en) Layout method for soft-error hard electronics, and radiation hardened logic cell
WO2011073691A3 (en) Utility data processing system
WO2010056511A3 (en) Technique for promoting efficient instruction fusion
WO2008085759A3 (en) Multitouch data fusion
WO2008045281A3 (en) Matching pursuits basis selection design
UA97972C2 (en) Fermentative degumming of oil composition with mixture of phospholipases pla and plc
WO2012122381A3 (en) Power-management for integrated circuits
WO2008045280A3 (en) Matching pursuits basis selection
WO2010104719A3 (en) Method and apparatus for generating a floorplan using a reduced netlist
WO2011011295A3 (en) Reducing a rate of data transfer to at least a portion of memory
WO2012079052A3 (en) Processing involving multiple sensors
TWI372338B (en) System, method, and computer program product for saving power in a multi-graphics processor environment
WO2007149384A3 (en) Data coding
WO2008118805A3 (en) Processor with adaptive multi-shader
WO2010088156A3 (en) Standard gestures
WO2007133471A3 (en) Modifying the processing capabilities of containers
WO2009009076A3 (en) Error correction for memory
WO2009008411A1 (en) Electronic apparatus and method for controlling the same
WO2011071594A3 (en) Energy-efficient set write of phase change memory with switch
WO2012012577A3 (en) Contextual decision logic elicitation
EP1974391A4 (en) Passivating layer for photovoltaic cells
WO2010051298A3 (en) Instruction and logic for performing range detection
WO2009117203A3 (en) Creating a standard cell circuit design from a programmable logic device circuit design
EP1987620A4 (en) Method for performance enhancement in a cell edge region

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200980112309.7

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09709144

Country of ref document: EP

Kind code of ref document: A2

WWE Wipo information: entry into national phase

Ref document number: 2010546000

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2968/KOLNP/2010

Country of ref document: IN

WWE Wipo information: entry into national phase

Ref document number: 2009709144

Country of ref document: EP