EP2251914B1 - Procédé destiné à l'application d'une couche anti-réflexion sur une tranche de silicium - Google Patents

Procédé destiné à l'application d'une couche anti-réflexion sur une tranche de silicium Download PDF

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Publication number
EP2251914B1
EP2251914B1 EP09004431A EP09004431A EP2251914B1 EP 2251914 B1 EP2251914 B1 EP 2251914B1 EP 09004431 A EP09004431 A EP 09004431A EP 09004431 A EP09004431 A EP 09004431A EP 2251914 B1 EP2251914 B1 EP 2251914B1
Authority
EP
European Patent Office
Prior art keywords
wafer
silicon wafer
main surface
anions
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Not-in-force
Application number
EP09004431A
Other languages
German (de)
English (en)
Other versions
EP2251914A1 (fr
Inventor
Friedrich Dr. Kröner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KIOTO Photovoltaics GmbH
Original Assignee
KIOTO Photovoltaics GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by KIOTO Photovoltaics GmbH filed Critical KIOTO Photovoltaics GmbH
Priority to DE202009017765U priority Critical patent/DE202009017765U1/de
Priority to EP09004431A priority patent/EP2251914B1/fr
Priority to DE502009000601T priority patent/DE502009000601D1/de
Priority to AT09004431T priority patent/ATE507586T1/de
Priority to ES09004431T priority patent/ES2363305T3/es
Publication of EP2251914A1 publication Critical patent/EP2251914A1/fr
Application granted granted Critical
Publication of EP2251914B1 publication Critical patent/EP2251914B1/fr
Not-in-force legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention relates to a method for applying an anti-reflection layer to a silicon wafer and an associated silicon wafer
  • a generic silicon wafer which is to supply electricity later as a solar cell in a photovoltaic system, has, for example, on one of its main surfaces a so-called p-type doping of silicon, usually by elements from the third main group of the periodic table (for example boron, Indium, aluminum or gallium). "On a surface” includes a certain penetration depth perpendicular to the main surface.
  • n-type doping On the opposite second major surface of the wafer then said n-type doping must be applied. This is done in the prior art so that one can penetrate from a suitable gas at high temperature phosphorus atoms in the later facing the sun main surface of the silicon wafer (diffuse).
  • This n-type layer is usually extremely thin so that the light can freely penetrate to the pn junction (between the n-doped one major surface and the p-doped other major surface).
  • the thickness of the n-type layer is, for example, less than 0.001 mm, while the wafer itself has a thickness (distance between the main surfaces) of, for example, 0.1 to 0.4 mm.
  • n-type doping is that some highly toxic gases that may contain phosphine, or corrosive gases such as POCl 3 are used and only a part of the offered phosphorus (usually less than 50%) passes into the solar cell.
  • the solar cells silicon wafers
  • a thin layer which is formed as an anti-reflection layer, in order to reduce losses by reflection of the light.
  • the layer is applied for example in a filled with gaseous ammonia and silanes vacuum reactor at temperatures between 300 and 400 ° C.
  • the invention is based on the object to provide a silicon wafer having an effective anti-reflection layer and can be prepared in a simple process without the use of hazardous gases.
  • the basic idea of the invention is to form the anti-reflection layer with the aid of an electrochemical (galvanic) process.
  • a precipitate on the corresponding main surface can be achieved in this way, which subsequently allows both the n-doping in the surface region and the creation of the anti-reflection layer in a thermal aftertreatment.
  • the method has the further advantage that the phosphorus is present in the form of phosphate ions, ie in oxidized form.
  • Phosphorus is representative of all elements of the 5th main group of the periodic table as dopant available.
  • the anti-reflection layer has a proportion of elements of the 5th main group of the periodic table (in addition to the main silicate component) excellent optical properties with respect to the prevention of light reflections, which are additionally varied by the layer thickness can.
  • the invention relates to a method for applying an anti-reflection layer to a silicon wafer with the steps according to claim 1.
  • a first layer is applied as a diffusion source for producing a pn junction on a semiconductor body and on the first layer, the order of a further layer for the production of an antireflection layer.
  • the anti-reflection layer should absorb red light more than 90%, which is possible with a glass based on SiO 2 and P 2 O 5 .
  • the SiO 2 content is best above 80% by mass.
  • the residence time of the silicon wafer in the basin and in the oven is selected such that the anti-reflection layer has a thickness of more than 150 nm and / or the n-doped main surface has a thickness (perpendicular to the main surface ) of 100-1000nm.
  • the sketched first method step ensures that in the subsequent electrochemical treatment only the remaining surface interacts with the solution.
  • the seal can be made with an element which abuts all but the suction points against the silicon wafer and takes over the anode function.
  • silicate ions which are essential for the subsequent formation of the anti-reflection layer and dopant ions, the n-doping of the uncovered main Serve surface of the wafer.
  • the silicate ions are anions of silicic acid and / or anions of salts of silicic acid (such as water glass).
  • the electrochemical deposition (of the aqueous electrolyte, for example) from the solution on the uncovered main surface of the wafer is accomplished by passage of current.
  • the substrate the silicon wafer
  • a counter electrode cathode
  • the residence time of the wafer in the basin depends on the degree of desired (anodic) deposition of the silicate and dopant ions. As a rule, the process is carried out until a temporary layer thickness of 100 to 300 nm is formed.
  • the wafer is removed with the electrolyte precipitate on its main surface from the basin, dried and in particular in an oven thermally heated to a temperature above 700 ° C (fired) to the desired amount of dopant atoms in the silicon Install grid of the wafer.
  • the desired glassy anti-reflection layer is formed on the surface of the silicon wafer.
  • Phosphorus atoms are particularly suitable as doping atoms within the fifth main group of the Periodic Table.
  • the process can be optimized by adding a reaction accelerator in the galvanic solution.
  • the reaction accelerator includes, for example, titanate ions which can be incorporated as tetraethyl orthotitanate, or trisodium citrate.
  • the residence time of the wafer in the basin is between 2 and 10 minutes, wherein a residence time of 4 to 6 minutes has proven favorable, starting from a voltage between 10 and 30 volts and a current flow between 25 and 150 mA / dm 2 , 30 to 100 mA / dm 2 for the desired effect.
  • the excess aqueous electrolyte should first drain before the actual drying process begins, which usually takes between 0.5 and 5 minutes.
  • the drying process can be accelerated in a preheated room.
  • electrical heat radiators can be used for drying. The drying is then carried out by radiation. Radiant heaters with a power between 250 and 750 watts are sufficient to achieve the desired drying within the specified period.
  • the drying can also be combined with the final process step, in which the actual doping and formation of a glaze surface takes place on the wafer.
  • an ambient temperature of over 700 ° C is required, with temperatures between 800 and 1100 ° C have been found to be favorable.
  • the residence time of the wafers is in the oven usually 10 to 30 minutes, for example 15 to 25 minutes.
  • the desired amount of dopant ions is incorporated into the silicon lattice of the silicon wafer until the silicon lattice has the desired density of dopant atoms and the glassy anti-reflection layer is formed.
  • the doping process is completed thereafter. Otherwise, in a separate step, the p-doping (backside doping) must subsequently be carried out, for example by electrochemical deposition of boric acid and by a borosilicate glass deposit.
  • solder contacts On the back (p-doped main surface) corresponding solder contacts (busbars) can be applied.

Landscapes

  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Development (AREA)
  • Engineering & Computer Science (AREA)
  • Sustainable Energy (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photovoltaic Devices (AREA)
  • Surface Treatment Of Optical Elements (AREA)
  • Physical Vapour Deposition (AREA)
  • Laminated Bodies (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
  • Formation Of Insulating Films (AREA)

Claims (6)

  1. Procédé pour l'application d'une couche antireflets sur une tranche de silicium comprenant les étapes suivantes :
    1.1 une première surface principale de tranche est recouverte de façon étanche au fluide,
    1.2 la tranche est plongée ensuite dans un bassin qui contient une solution à base d'anions d'acide silique et/ou d'anions d' au moins un sel d'acide silique ainsi que d'ions de dopage d'au moins un élément du 5ème groupe principal du système périodique,
    1.3 pour la précipitation électrochimique des anions sur la seconde surface principale non-recouverte de la tranche, du courant continu est appliqué entre la tranche branchée comme anode et une autre électrode branchée comme cathode,
    1.4 après un temps de séjour dans le bassin, la tranche est sortie du bassin et
    1.5 séchée ensuite et cuite à une température supérieure à 700°C, jusqu'à ce qu'une quantité souhaitée d'atomes de dopage soit intégrée dans la grille de silicium de la tranche et une couche antireflets vitreuse s'est formée sur la seconde surface principale de la tranche de silicium.
  2. Procédé selon la revendication 1, dans lequel le temps de séjour de la tranche de silicium dans le bassin et dans le four est choisi de telle sorte que la couche antireflets présente une épaisseur de 50 à 250 nm.
  3. Procédé selon la revendication 1, dans lequel les ions de dopage sont des ions de phosphore.
  4. Procédé selon la revendication 1, dans lequel le temps de séjour de la tranche de silicium dans la solution est de 2 à 10 minutes.
  5. Procédé selon la revendication 1, dans lequel la précipitation électrochimique s'effectue avec une intensité de courant de 50 à 150 mA/dm2.
  6. Procédé selon la revendication 1, dans lequel la tranche de silicium est cuite dans un four à une température comprise entre 800 et 1100°C.
EP09004431A 2009-03-27 2009-03-27 Procédé destiné à l'application d'une couche anti-réflexion sur une tranche de silicium Not-in-force EP2251914B1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
DE202009017765U DE202009017765U1 (de) 2009-03-27 2009-03-27 Silicium-Wafer
EP09004431A EP2251914B1 (fr) 2009-03-27 2009-03-27 Procédé destiné à l'application d'une couche anti-réflexion sur une tranche de silicium
DE502009000601T DE502009000601D1 (de) 2009-03-27 2009-03-27 Verfahren zum Aufbringen einer Anti-Reflexionsschicht auf einen Silizium-Wafer
AT09004431T ATE507586T1 (de) 2009-03-27 2009-03-27 Verfahren zum aufbringen einer anti- reflexionsschicht auf einen silizium-wafer
ES09004431T ES2363305T3 (es) 2009-03-27 2009-03-27 Procedimiento para la aplicación de una capa antirreflectante sobre una oblea de silicio.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP09004431A EP2251914B1 (fr) 2009-03-27 2009-03-27 Procédé destiné à l'application d'une couche anti-réflexion sur une tranche de silicium

Publications (2)

Publication Number Publication Date
EP2251914A1 EP2251914A1 (fr) 2010-11-17
EP2251914B1 true EP2251914B1 (fr) 2011-04-27

Family

ID=40940461

Family Applications (1)

Application Number Title Priority Date Filing Date
EP09004431A Not-in-force EP2251914B1 (fr) 2009-03-27 2009-03-27 Procédé destiné à l'application d'une couche anti-réflexion sur une tranche de silicium

Country Status (4)

Country Link
EP (1) EP2251914B1 (fr)
AT (1) ATE507586T1 (fr)
DE (2) DE502009000601D1 (fr)
ES (1) ES2363305T3 (fr)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3345274A (en) * 1964-04-22 1967-10-03 Westinghouse Electric Corp Method of making oxide film patterns
US3615943A (en) * 1969-11-25 1971-10-26 Milton Genser Deposition of doped and undoped silica films on semiconductor surfaces
DE3340874A1 (de) 1983-11-11 1985-05-23 Telefunken electronic GmbH, 7100 Heilbronn Verfahren zum herstellen einer solarzelle

Also Published As

Publication number Publication date
DE502009000601D1 (de) 2011-06-09
DE202009017765U1 (de) 2010-05-12
ES2363305T3 (es) 2011-07-29
EP2251914A1 (fr) 2010-11-17
ATE507586T1 (de) 2011-05-15

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