EP2183653B1 - Linear-spannungsregler - Google Patents

Linear-spannungsregler Download PDF

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Publication number
EP2183653B1
EP2183653B1 EP08787129A EP08787129A EP2183653B1 EP 2183653 B1 EP2183653 B1 EP 2183653B1 EP 08787129 A EP08787129 A EP 08787129A EP 08787129 A EP08787129 A EP 08787129A EP 2183653 B1 EP2183653 B1 EP 2183653B1
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Prior art keywords
voltage
output
terminal
inverter
electrically coupled
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EP08787129A
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English (en)
French (fr)
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EP2183653A1 (de
Inventor
Seongwon Kim
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International Business Machines Corp
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International Business Machines Corp
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Priority claimed from US11/847,416 external-priority patent/US7847529B2/en
Priority claimed from US11/847,461 external-priority patent/US7855534B2/en
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Publication of EP2183653A1 publication Critical patent/EP2183653A1/de
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

Definitions

  • Voltage regulators have been utilized to control voltages applied to devices.
  • a problem with the voltage regulators is that the voltage regulators have not been able to effectively remove both high frequency noise and low frequency noise from a voltage source.
  • the voltage regulators utilize at least two relatively expensive comparator chips which utilize a relatively large amount of power (see e.g. US2007/0188154 )
  • a linear voltage regulator in accordance with an exemplary embodiment includes a first circuit configured to receive the first voltage from a voltage source and to remove frequency components of the first voltage in a first frequency range to obtain an output voltage at a primary output node.
  • the linear voltage regulator further includes a second circuit having first and second inverters electrically coupled to the primary output node of the first circuit.
  • the second circuit is configured to receive the output voltage and to remove frequency components of the output voltage in a second frequency range.
  • the second frequency range is greater than the first frequency range.
  • a linear voltage regulator in accordance with another exemplary embodiment includes a first inverter having a first input terminal and a first output terminal.
  • the first input terminal is electrically coupled to the first output terminal.
  • the first input terminal is further electrically coupled to a capacitor which is further coupled to electrical ground.
  • the first inverter is further electrically coupled to a primary output node such a first voltage on the first output terminal is less than the output voltage at the primary output node.
  • the linear voltage regulator further includes a second inverter having a second input terminal and a second output terminal.
  • the second input terminal is electrically coupled to the first output terminal of the first inverter.
  • the second inverter is further electrically coupled to the primary output node and receiving the first voltage from the first inverter.
  • the linear voltage regulator further includes a p-channel field effect transistor (P-FET transistor) having a gate terminal, a drain terminal and a source terminal.
  • the source terminal is electrically coupled to a voltage source.
  • the drain terminal is coupled to the primary output node.
  • the gate terminal electrically communicates either directly or indirectly with the second output terminal of the second inverter, such that when the output voltage at the primary output node is increased, the first voltage on the first output terminal of the first inverter is less than the output voltage on the primary output node which induces the second inverter to output a high logic voltage on the second output terminal.
  • the P-FET transistor reduces the output voltage on the primary output node in response to the high logic voltage.
  • an electrical system 10 having a linear voltage regulator 14 in accordance with an exemplary embodiment is illustrated.
  • the electrical system further includes a voltage source 12 and a load 18.
  • An advantage of the linear voltage regulator 14 is that the regulator is able to output a voltage that has minimal voltage deviation for voltage-sensitive load devices.
  • the voltage source 12 is provided to output a voltage that may deviate from a desired voltage level.
  • the voltage source 12 is electrically coupled to the linear voltage regulator 14.
  • the linear voltage regulator 14 is provided to receive the voltage from the voltage source 12 and to output a voltage that minimal voltage deviation from a desired voltage level.
  • the linear voltage regulator 14 includes a circuit 20 and a circuit 22.
  • the circuit 20 is provided to remove frequency components of the voltage received from voltage source 12 in a first frequency range to obtain an output voltage at the primary voltage node 36 with reduced voltage deviation.
  • the circuit 20 is configured to remove frequency components of the voltage received from the voltage source 12 in the frequency range of 0 to 10 Megahertz.
  • the circuit 20 can remove frequency components in other frequency ranges.
  • the circuit 20 includes a voltage reference device 30, an operational amplifier 32, and a P-FET transistor 34.
  • the operational amplifier 32 has an inverting input terminal "-", a non-inverting input terminal "+”, and an output terminal.
  • the P-FET transistor has a gate terminal (G1), a source terminal (S1), and a drain terminal (D1).
  • the voltage reference device 30 is electrically connected to the inverting input terminal "-" of the operational amplifier 32.
  • the voltage reference device 30 is configured to output a desired reference voltage level.
  • the output terminal of the operational amplifier 32 is electrically coupled to the gate terminal (G1) of the P-FET transistor 34.
  • the non-inverting terminal "+” of the operational amplifier 32 is electrically coupled to the drain terminal (D1) of the P-FET transistor 34 and further coupled to the primary output node 36.
  • the P-FET transistor 34 increases current flowing from the source terminal (S1) to the drain terminal (D1) which causes the output voltage on the primary output node 36 to increase.
  • the P-FET transistor 34 decreases current flowing from the source terminal (S1) to the drain terminal (D1) which causes the output voltage on the primary output node 36 to decrease.
  • the circuit 22 is provided to remove frequency components of the voltage received from voltage source 12 in a second frequency range to obtain an output voltage at the primary voltage node 36 with reduced voltage deviation.
  • the circuit 22 is configured to remove frequency components of the voltage received from the voltage source 12 in the frequency range of 10 Megahertz to 6 Gigahertz.
  • the circuit 22 can remove frequency components in other frequency ranges.
  • the circuit 22 includes a comparator circuit 62, 50, inverters 52, 54, 56, 58, 60, and a P-FET transistor 62.
  • the comparator circuit 50 is provided to detect a voltage deviation on the primary output node 36.
  • the comparator circuit 50 includes inverters 80, 82 and a capacitor 84.
  • the inverter 80 includes a P-FET transistor 90, a FET transistor 92, an input terminal 94, and an output terminal 96.
  • the P-FET transistor 90 includes a gate terminal (G3), a source terminal (S3), and a drain terminal (D3).
  • the FET transistor 92 includes a gate terminal (G4), a source terminal (S4), and a drain terminal (D4).
  • the P-FET transistor 90 is electrically coupled to the FET transistor 92.
  • the gate terminals (G3), (G4) are electrically coupled together at the input terminal 94.
  • the source terminal (S3) is electrically coupled to the primary output node 36.
  • the drain terminal (D3) is electrically coupled to the source terminal (S4) at the output terminal 96.
  • the output terminal 96 is electrically coupled to the input terminal 94.
  • the terminal (D4) is electrically coupled to electrical ground.
  • the capacitor 84 is electrically coupled between the input terminal 94 and electrical ground.
  • the comparator circuit 50 when an output voltage at the primary output node 36 is increased, the voltage on the output terminal 96 of the inverter 80 is less than the output voltage on the primary output node 36 which induces the inverter 82 to output a high logic voltage on the output terminal 106.
  • the high logic voltage is utilized to subsequently induce the P-FET transistor 62 to reduce the output voltage on the primary output node 36 in response to the high logic voltage.
  • the output voltage at the primary output node 36 is decreased, the voltage on the output terminal 96 of the inverter 80 is greater than the output voltage on the primary output node 36 which induces the inverter 82 to output a low logic voltage on the output terminal 106.
  • the low logic voltage is subsequently utilized to induce the P-FET transistor 62 to increase the output voltage on the primary output node 36 in response to the low logic voltage.
  • the chain of inverters 52, 54, 56, 58, 60 are provided to amplify the output voltage from the comparator circuit 50 which is received by the gate terminal (G2) of the P-FET transistor 62.
  • the inverter 52 includes a P-FET transistor 110, a FET transistor 112, an input terminal 114, and an output terminal 116.
  • the P-FET transistor 110 includes a gate terminal (G7), a source terminal (S7), and a drain terminal (D7).
  • the FET transistor 112 includes a gate terminal (G8), a source terminal (S8), and a drain terminal (D8).
  • the P-FET transistor 110 is electrically coupled to the FET transistor 112.
  • the gate terminals (G7), (G8) are electrically coupled together at the input terminal 114.
  • the source terminal (S7) is electrically coupled to the primary output node 36.
  • the drain terminal (D7) is electrically coupled to the source terminal (S8) at the output terminal 116.
  • the output terminal 116 is electrically coupled to an input terminal 124.
  • the terminal (D8) is electrically coupled to electrical ground.
  • the inverter 52 receives an output voltage at the input terminal 114 from the comparator circuit 50 and outputs an inverted amplified output voltage at the output terminal 116.
  • the inverter 54 includes a P-FET transistor 120, a FET transistor 122, an input terminal 124, and an output terminal 126.
  • the P-FET transistor 120 includes a gate terminal (G9), a source terminal (S9), and a drain terminal (D9).
  • the FET transistor 122 includes a gate terminal (G10), a source terminal (S10), and a drain terminal (D10).
  • the P-FET transistor 120 is electrically coupled to the FET transistor 122.
  • the gate terminals (G9), (G10) are electrically coupled together at the input terminal 124.
  • the source terminal (S9) is electrically coupled to the primary output node 36.
  • the drain terminal (D9) is electrically coupled to the source terminal (S10) at the output terminal 126.
  • the output terminal 126 is electrically coupled to an input terminal 134.
  • the terminal (D10) is electrically coupled to electrical ground.
  • the inverter 54 receives an output voltage at the input terminal 124 from the inverter 52 and outputs an inverted amplified output voltage at the output terminal 126.
  • the output terminal 136 is electrically coupled to an input terminal 144.
  • the terminal (D12) is electrically coupled to electrical ground.
  • the inverter 56 receives an output voltage at the input terminal 134 from the inverter 54 and outputs an inverted amplified output voltage at the output terminal 136.
  • the inverter 58 includes a P-FET transistor 140, a FET transistor 142, an input terminal 144, and an output terminal 146.
  • the P-FET transistor 140 includes a gate terminal (G 13), a source terminal (S13), and a drain terminal (D13).
  • the FET transistor 142 includes a gate terminal (G14), a source terminal (S14), and a drain terminal (D14).
  • the P-FET transistor 140 is electrically coupled to the FET transistor 142.
  • the gate terminals (G13), (G14) are electrically coupled together at the input terminal 144.
  • the source terminal (S13) is electrically coupled to the primary output node 36.
  • the drain terminal (D13) is electrically coupled to the source terminal (S14) at the output terminal 146.
  • the output terminal 146 is electrically coupled to an input terminal 154.
  • the terminal (D14) is electrically coupled to electrical ground.
  • the inverter 58 receives an output voltage at the input terminal 144 from the inverter 56 and outputs an inverted amplified output voltage at the output terminal 146.
  • the inverter 60 includes a P-FET transistor 150, a FET transistor 152, an input terminal 154, and an output terminal 156.
  • the P-FET transistor 150 includes a gate terminal (G 15), a source terminal (S15), and a drain terminal (D15).
  • the FET transistor 152 includes a gate terminal (G16), a source terminal (S16), and a drain terminal (D 16).
  • the P-FET transistor 150 is electrically coupled to the FET transistor 152.
  • the gate terminals (G15), (G16) are electrically coupled together at the input terminal 154.
  • the source terminal (S15) is electrically coupled to the primary output node 36.
  • the drain terminal (D15) is electrically coupled to the source terminal (S16) at the output terminal 156.
  • the linear voltage regulator 14 could be constructed by removing inverters 52, 54, 56, 58, 60 where inverter 82 would be directly electrically coupled to the P-FET transistor 62.
  • the number of inverters in the chain of inverters to amplify the voltage from the comparator circuit 50 can be greater than or less than the number of inverters shown in the chain of inverters of Figure 1 .
  • the P-FET transistor 62 is provided to remove voltage deviations at the primary output node 36.
  • the P-FET transistor 62 is provided to remove frequency components of the output voltage in a second frequency range.
  • the P-FET transistor 62 includes a gate terminal (G2), a source terminal (S2), and a drain terminal (D2).
  • the gate terminal (G2) is electrically coupled to the output terminal 156 of the inverter 60.
  • the source terminal (S2) is electrically coupled to the voltage source 12.
  • the drain terminal (D2) is electrically coupled to the primary node 36.
  • the resistor 18 is electrically between the primary output node 36 and electrical ground. The resistor 18 corresponds to a load receiving the output voltage from the linear voltage regulator 14.
  • the P-FET transistor 62 When the P-FET transistor 62 receives a high logic voltage from the inverter 60 at the gate terminal (G2), the P-FET transistor 62 decreases current flowing therethrough to reduce the output voltage on the primary output node 36 in response to the high logic voltage. Alternately, when the P-FET transistor 62 receives a low logic voltage from the inverter 60 at the gate terminal (G2), the P-FET transistor 62 increases current flowing therethrough to increase the output voltage on the primary output node 36 in response to the low logic voltage.
  • a voltage curve 170 corresponds to an exemplary output voltage generated by the voltage source 12. As shown, the voltage curve 170 has oscillatory shape over time.
  • a voltage curve 180 corresponds to an output voltage generated by the linear voltage regulator 14 at the primary output node 36. As shown, the voltage curve 180 is relatively constant over time as desired.
  • a voltage curve 190 corresponds to an output voltage at the output terminal 96 of the comparator 50.
  • a voltage curve 200 corresponds to a voltage received at the gate terminal (G2) of the P-FET transistor 62 for controlling operation of the P-FET transistor 62.
  • the circuit 20 of the linear voltage regulator 14 receives a first voltage from the voltage source 12.
  • the circuit 20 has the primary output node 36.
  • the circuit 20 removes frequency components of the first voltage in a first frequency range to obtain an output voltage at the primary output node 36.
  • the circuit 22 of the linear voltage regulator 14 has inverters 80, 82 electrically coupled either directly or indirectly to the primary output node 36 to remove frequency components of the output voltage in a second frequency range.
  • the second frequency range is greater than the first frequency range.
  • the step 224 is implemented utilizing steps 230-240.
  • the inverter 80 outputs a second voltage on the output terminal 96 that is less than the output voltage on the primary output node 36, when the output voltage at the primary output node 36 is increased.
  • the P-FET transistor 62 reduces the output voltage on the primary output node 36 in response to the high logic voltage.
  • the inverter 80 outputs the second voltage on the output terminal 96 that is greater than the output voltage on the primary output node 36, when the output voltage at the primary output node 36 is decreased.
  • the inverter 82 outputs a low logic voltage on the output terminal 106 in response to the second voltage being greater than the output voltage.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)

Claims (9)

  1. Linearer Spannungsregler, aufweisend:
    eine erste Schaltung (20), die so konfiguriert ist, dass sie eine erste Spannung von einer Spannungsquelle empfängt und Frequenzkomponenten der ersten Spannung in einem ersten Frequenzbereich entfernt, um eine Ausgangsspannung an einem primären Ausgangsknoten zu erhalten; und
    eine zweite Schaltung (22) mit einem ersten und einem zweiten Inverter, die mit dem primären Ausgangsknoten der ersten Schaltung elektrisch verbunden sind, wobei die zweite Schaltung so konfiguriert ist, dass sie die Ausgangsspannung empfängt und Frequenzkomponenten der Ausgangsspannung in einem zweiten Frequenzbereich entfernt, wobei die Frequenzen im zweiten Frequenzbereich höher als die Frequenzen im ersten Frequenzbereich sind;
    wobei der erste Inverter einen ersten Eingangsanschluss und einen ersten Ausgangsanschluss aufweist, wobei der erste Eingangsanschluss mit dem ersten Ausgangsanschluss elektrisch verbunden ist, wobei der erste Eingangsanschluss außerdem mit einem Kondensator elektrisch verbunden ist, der außerdem mit Masse verbunden ist, wobei der erste Inverter außerdem mit dem primären Ausgangsknoten elektrisch verbunden ist, so dass eine zweite Spannung am ersten Ausgangsanschluss niedriger als die Ausgangsspannung am primären Ausgangsknoten ist; und wobei der zweite Inverter einen zweiten Eingangsanschluss und einen zweiten Ausgangsanschluss aufweist, wobei der zweite Eingangsanschluss mit dem ersten Ausgangsanschluss des ersten Inverters elektrisch verbunden ist, wobei der zweite Inverter außerdem mit dem ersten Ausgangsknoten elektrisch verbunden ist; und
    wobei die zweite Schaltung außerdem einen p-FET(62) mit einem Gate-Anschluss, einem Drain-Anschluss und einem Source-Anschluss aufweist, wobei der Source-Anschluss mit der Spannungsquelle elektrisch verbunden ist, wobei der Drain-Anschluss mit dem primären Ausgangsknoten elektrisch verbunden ist, wobei der Gate-Anschluss direkt oder indirekt mit dem zweiten Ausgangsanschluss des zweiten Inverters elektrisch in Verbindung steht, so dass, wenn die Ausgangsspannung am primären Ausgangsknoten erhöht wird, die zweite Spannung am ersten Ausgangsanschluss des ersten Inverters geringer als die Ausgangsspannung am primären Ausgangsknoten wird, was den zweiten Inverter veranlasst, eine einem logischem HIGH entsprechende Spannung am zweiten Ausgangsanschluss auszugeben, und der p-FET senkt als Reaktion auf die einem logischem HIGH entsprechende Spannung die Ausgangsspannung am primären Ausgangsknoten.
  2. Linearer Spannungsregler nach Anspruch 1, wobei, wenn die Ausgangsspannung am primären Ausgangsknoten abgesenkt wird, die zweite Spannung am ersten Ausgangsanschluss des ersten Inverters größer als die Ausgangsspannung am primären Ausgangsknoten wird, was den zweiten Inverter veranlasst, eine einem logischen LOW entsprechende Spannung am zweiten Ausgangsanschluss auszugeben, und der p-FET erhöht als Reaktion auf die einem logischen LOW entsprechende Spannung die Ausgangsspannung am primären Ausgangsknoten.
  3. Linearer Spannungsregler nach Anspruch 1, der außerdem mindestens einen dritten und einen vierten Inverter aufweist, die zwischen dem zweiten Ausgangsanschluss des zweiten Inverters und dem Gate-Anschluss des p-FETs in Reihe geschaltet sind.
  4. Linearer Spannungsregler nach Anspruch 1, wobei sich der erste Frequenzbereich von 0 bis 10 Megahertz erstreckt.
  5. Linearer Spannungsregler nach Anspruch 1, wobei sich der zweite Frequenzbereich von 10 Megahertz bis 6 Gigahertz erstreckt.
  6. Verfahren zum Regeln einer Spannung unter Verwendung eines linearen Spannungsreglers, wobei der lineare Spannungsregler eine erste Schaltung (20) mit einem ersten primären Ausgangsknoten und eine zweite Schaltung (22) mit einem ersten und einem zweiten Inverter aufweist, die mit dem primären Ausgangsknoten elektrisch verbunden sind, wobei das Verfahren aufweist:
    Empfangen einer ersten Spannung von einer Spannungsquelle in der ersten Schaltung;
    Entfernen von Frequenzkomponenten der ersten Spannung in einem ersten Frequenzbereich unter Verwendung der ersten Schaltung, um eine Ausgangsspannung am primären Ausgangsknoten zu erhalten; und
    Entfernen von Frequenzkomponenten der Ausgangsspannung in einem zweiten Frequenzbereich unter Verwendung des ersten und des zweiten Inverters der zweiten Schaltung, wobei der zweite Frequenzbereich oberhalb des ersten Frequenzbereichs liegt;
    wobei die zweite Schaltung außerdem einen p-FET (62) aufweist, wobei der erste Inverter einen ersten Eingangsanschluss und einen ersten Ausgangsanschluss aufweist, wobei der erste Eingangsanschluss mit dem ersten Ausgangsanschluss elektrisch verbunden ist, wobei der erste Eingangsanschluss außerdem mit einem Kondensator elektrisch verbunden ist, der außerdem mit Masse verbunden ist, wobei der erste Inverter außerdem mit dem primären Ausgangsknoten elektrisch verbunden ist, wobei der zweite Inverter einen zweiten Eingangsanschluss und einen zweiten Ausgangsanschluss aufweist, wobei der zweite Eingangsanschluss mit dem ersten Ausgangsanschluss des ersten Inverters elektrisch verbunden ist, wobei der zweite Inverter außerdem mit dem primären Ausgangsknoten elektrisch verbunden ist, wobei der p-FET Transistor einen Gate-Anschluss, einen Drain-Anschluss und einen Source-Anschluss aufweist, wobei der Source-Anschluss mit der Spannungsquelle elektrisch verbunden ist, wobei der Drain-Anschluss mit dem primären Ausgangsknoten elektrisch verbunden ist, wobei der Gate-Anschluss direkt oder
    indirekt mit dem zweiten Ausgangsanschluss des zweiten Inverters elektrisch in Verbindung steht, wobei das Entfernen von Frequenzkomponenten der Ausgangsspannung im zweiten Frequenzbereich unter Verwendung der zweiten Schaltung aufweist:
    bei Erhöhung der Ausgangsspannung am primären Ausgangsknoten Ausgeben einer zweiten Spannung am ersten Ausgangsanschluss des ersten Inverters, die niedriger als die Ausgangsspannung am primären Ausgangsknoten ist;
    Ausgeben einer einem logischen HIGH entsprechenden Spannung am zweiten Ausgangsanschluss durch den zweiten Inverter als Reaktion darauf, dass die zweite Spannung niedriger als die Ausgangsspannung ist; und
    Absenken der Ausgangsspannung am primären Ausgangsknoten als Reaktion auf die einem logischen HIGH entsprechende Spannung unter Verwendung des p-FETs.
  7. Verfahren nach Anspruch 6, wobei das Entfernen von Frequenzkomponenten der Ausgangsspannung im zweiten Frequenzbereich unter Verwendung der zweiten Schaltung außerdem aufweist:
    Ausgeben der zweiten Spannung am ersten Ausgangsanschluss des ersten Inverters, die höher als die Ausgangsspannung am primären Ausgangsanschluss ist, wenn die Ausgangsspannung am primären Ausgangsanschluss abgesenkt wird;
    Ausgeben einer einem logischen LOW entsprechenden Spannung durch den zweiten Inverter am zweiten Ausgangsanschluss als Reaktion darauf, dass die zweite Spannung höher als die Ausgangsspannung ist; und
    Erhöhen der Ausgangsspannung am primären Ausgangsknoten als Reaktion auf die einem logischen LOW entsprechende Spannung unter Verwendung des p-FETs.
  8. Verfahren nach Anspruch 6, wobei sich der erste Frequenzbereich von 0 bis 10 Megahertz erstreckt.
  9. Verfahren nach Anspruch 6, wobei sich der zweite Frequenzbereich von 10 Megahertz bis 6 Gigahertz erstreckt.
EP08787129A 2007-08-30 2008-08-12 Linear-spannungsregler Active EP2183653B1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/847,416 US7847529B2 (en) 2007-08-30 2007-08-30 Dual loop linear voltage regulator with high frequency noise reduction
US11/847,461 US7855534B2 (en) 2007-08-30 2007-08-30 Method for regulating a voltage using a dual loop linear voltage regulator with high frequency noise reduction
PCT/EP2008/060565 WO2009027220A1 (en) 2007-08-30 2008-08-12 Linear voltage regulator

Publications (2)

Publication Number Publication Date
EP2183653A1 EP2183653A1 (de) 2010-05-12
EP2183653B1 true EP2183653B1 (de) 2013-01-02

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EP (1) EP2183653B1 (de)
JP (1) JP5295240B2 (de)
KR (1) KR20100053560A (de)
CN (1) CN101784975B (de)
WO (1) WO2009027220A1 (de)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4952863A (en) * 1989-12-20 1990-08-28 International Business Machines Corporation Voltage regulator with power boost system
JP2006053829A (ja) * 2004-08-13 2006-02-23 Mitsunori Katsu 電圧レギュレータ内蔵半導体集積回路
US7301320B2 (en) * 2005-01-21 2007-11-27 International Business Machines Corporation On-chip high frequency power supply noise sensor
TW200731046A (en) * 2006-02-14 2007-08-16 Richtek Techohnology Corp Linear voltage regulator and control method thereof
US7508177B2 (en) * 2007-06-08 2009-03-24 Freescale Semiconductor, Inc. Method and circuit for reducing regulator output noise
JP4642830B2 (ja) * 2007-11-06 2011-03-02 株式会社リコー 電源供給装置及びその電源供給方法

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Publication number Publication date
CN101784975B (zh) 2012-12-26
JP2010537335A (ja) 2010-12-02
EP2183653A1 (de) 2010-05-12
WO2009027220A1 (en) 2009-03-05
KR20100053560A (ko) 2010-05-20
CN101784975A (zh) 2010-07-21
JP5295240B2 (ja) 2013-09-18

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