EP2183653B1 - Linear voltage regulator - Google Patents
Linear voltage regulator Download PDFInfo
- Publication number
- EP2183653B1 EP2183653B1 EP08787129A EP08787129A EP2183653B1 EP 2183653 B1 EP2183653 B1 EP 2183653B1 EP 08787129 A EP08787129 A EP 08787129A EP 08787129 A EP08787129 A EP 08787129A EP 2183653 B1 EP2183653 B1 EP 2183653B1
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- European Patent Office
- Prior art keywords
- voltage
- output
- terminal
- inverter
- electrically coupled
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000000034 method Methods 0.000 claims description 8
- 239000003990 capacitor Substances 0.000 claims description 5
- 230000003247 decreasing effect Effects 0.000 claims description 4
- 230000001105 regulatory effect Effects 0.000 claims description 3
- 230000007423 decrease Effects 0.000 description 4
- 230000001276 controlling effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003534 oscillatory effect Effects 0.000 description 1
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Classifications
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
Definitions
- Voltage regulators have been utilized to control voltages applied to devices.
- a problem with the voltage regulators is that the voltage regulators have not been able to effectively remove both high frequency noise and low frequency noise from a voltage source.
- the voltage regulators utilize at least two relatively expensive comparator chips which utilize a relatively large amount of power (see e.g. US2007/0188154 )
- a linear voltage regulator in accordance with an exemplary embodiment includes a first circuit configured to receive the first voltage from a voltage source and to remove frequency components of the first voltage in a first frequency range to obtain an output voltage at a primary output node.
- the linear voltage regulator further includes a second circuit having first and second inverters electrically coupled to the primary output node of the first circuit.
- the second circuit is configured to receive the output voltage and to remove frequency components of the output voltage in a second frequency range.
- the second frequency range is greater than the first frequency range.
- a linear voltage regulator in accordance with another exemplary embodiment includes a first inverter having a first input terminal and a first output terminal.
- the first input terminal is electrically coupled to the first output terminal.
- the first input terminal is further electrically coupled to a capacitor which is further coupled to electrical ground.
- the first inverter is further electrically coupled to a primary output node such a first voltage on the first output terminal is less than the output voltage at the primary output node.
- the linear voltage regulator further includes a second inverter having a second input terminal and a second output terminal.
- the second input terminal is electrically coupled to the first output terminal of the first inverter.
- the second inverter is further electrically coupled to the primary output node and receiving the first voltage from the first inverter.
- the linear voltage regulator further includes a p-channel field effect transistor (P-FET transistor) having a gate terminal, a drain terminal and a source terminal.
- the source terminal is electrically coupled to a voltage source.
- the drain terminal is coupled to the primary output node.
- the gate terminal electrically communicates either directly or indirectly with the second output terminal of the second inverter, such that when the output voltage at the primary output node is increased, the first voltage on the first output terminal of the first inverter is less than the output voltage on the primary output node which induces the second inverter to output a high logic voltage on the second output terminal.
- the P-FET transistor reduces the output voltage on the primary output node in response to the high logic voltage.
- an electrical system 10 having a linear voltage regulator 14 in accordance with an exemplary embodiment is illustrated.
- the electrical system further includes a voltage source 12 and a load 18.
- An advantage of the linear voltage regulator 14 is that the regulator is able to output a voltage that has minimal voltage deviation for voltage-sensitive load devices.
- the voltage source 12 is provided to output a voltage that may deviate from a desired voltage level.
- the voltage source 12 is electrically coupled to the linear voltage regulator 14.
- the linear voltage regulator 14 is provided to receive the voltage from the voltage source 12 and to output a voltage that minimal voltage deviation from a desired voltage level.
- the linear voltage regulator 14 includes a circuit 20 and a circuit 22.
- the circuit 20 is provided to remove frequency components of the voltage received from voltage source 12 in a first frequency range to obtain an output voltage at the primary voltage node 36 with reduced voltage deviation.
- the circuit 20 is configured to remove frequency components of the voltage received from the voltage source 12 in the frequency range of 0 to 10 Megahertz.
- the circuit 20 can remove frequency components in other frequency ranges.
- the circuit 20 includes a voltage reference device 30, an operational amplifier 32, and a P-FET transistor 34.
- the operational amplifier 32 has an inverting input terminal "-", a non-inverting input terminal "+”, and an output terminal.
- the P-FET transistor has a gate terminal (G1), a source terminal (S1), and a drain terminal (D1).
- the voltage reference device 30 is electrically connected to the inverting input terminal "-" of the operational amplifier 32.
- the voltage reference device 30 is configured to output a desired reference voltage level.
- the output terminal of the operational amplifier 32 is electrically coupled to the gate terminal (G1) of the P-FET transistor 34.
- the non-inverting terminal "+” of the operational amplifier 32 is electrically coupled to the drain terminal (D1) of the P-FET transistor 34 and further coupled to the primary output node 36.
- the P-FET transistor 34 increases current flowing from the source terminal (S1) to the drain terminal (D1) which causes the output voltage on the primary output node 36 to increase.
- the P-FET transistor 34 decreases current flowing from the source terminal (S1) to the drain terminal (D1) which causes the output voltage on the primary output node 36 to decrease.
- the circuit 22 is provided to remove frequency components of the voltage received from voltage source 12 in a second frequency range to obtain an output voltage at the primary voltage node 36 with reduced voltage deviation.
- the circuit 22 is configured to remove frequency components of the voltage received from the voltage source 12 in the frequency range of 10 Megahertz to 6 Gigahertz.
- the circuit 22 can remove frequency components in other frequency ranges.
- the circuit 22 includes a comparator circuit 62, 50, inverters 52, 54, 56, 58, 60, and a P-FET transistor 62.
- the comparator circuit 50 is provided to detect a voltage deviation on the primary output node 36.
- the comparator circuit 50 includes inverters 80, 82 and a capacitor 84.
- the inverter 80 includes a P-FET transistor 90, a FET transistor 92, an input terminal 94, and an output terminal 96.
- the P-FET transistor 90 includes a gate terminal (G3), a source terminal (S3), and a drain terminal (D3).
- the FET transistor 92 includes a gate terminal (G4), a source terminal (S4), and a drain terminal (D4).
- the P-FET transistor 90 is electrically coupled to the FET transistor 92.
- the gate terminals (G3), (G4) are electrically coupled together at the input terminal 94.
- the source terminal (S3) is electrically coupled to the primary output node 36.
- the drain terminal (D3) is electrically coupled to the source terminal (S4) at the output terminal 96.
- the output terminal 96 is electrically coupled to the input terminal 94.
- the terminal (D4) is electrically coupled to electrical ground.
- the capacitor 84 is electrically coupled between the input terminal 94 and electrical ground.
- the comparator circuit 50 when an output voltage at the primary output node 36 is increased, the voltage on the output terminal 96 of the inverter 80 is less than the output voltage on the primary output node 36 which induces the inverter 82 to output a high logic voltage on the output terminal 106.
- the high logic voltage is utilized to subsequently induce the P-FET transistor 62 to reduce the output voltage on the primary output node 36 in response to the high logic voltage.
- the output voltage at the primary output node 36 is decreased, the voltage on the output terminal 96 of the inverter 80 is greater than the output voltage on the primary output node 36 which induces the inverter 82 to output a low logic voltage on the output terminal 106.
- the low logic voltage is subsequently utilized to induce the P-FET transistor 62 to increase the output voltage on the primary output node 36 in response to the low logic voltage.
- the chain of inverters 52, 54, 56, 58, 60 are provided to amplify the output voltage from the comparator circuit 50 which is received by the gate terminal (G2) of the P-FET transistor 62.
- the inverter 52 includes a P-FET transistor 110, a FET transistor 112, an input terminal 114, and an output terminal 116.
- the P-FET transistor 110 includes a gate terminal (G7), a source terminal (S7), and a drain terminal (D7).
- the FET transistor 112 includes a gate terminal (G8), a source terminal (S8), and a drain terminal (D8).
- the P-FET transistor 110 is electrically coupled to the FET transistor 112.
- the gate terminals (G7), (G8) are electrically coupled together at the input terminal 114.
- the source terminal (S7) is electrically coupled to the primary output node 36.
- the drain terminal (D7) is electrically coupled to the source terminal (S8) at the output terminal 116.
- the output terminal 116 is electrically coupled to an input terminal 124.
- the terminal (D8) is electrically coupled to electrical ground.
- the inverter 52 receives an output voltage at the input terminal 114 from the comparator circuit 50 and outputs an inverted amplified output voltage at the output terminal 116.
- the inverter 54 includes a P-FET transistor 120, a FET transistor 122, an input terminal 124, and an output terminal 126.
- the P-FET transistor 120 includes a gate terminal (G9), a source terminal (S9), and a drain terminal (D9).
- the FET transistor 122 includes a gate terminal (G10), a source terminal (S10), and a drain terminal (D10).
- the P-FET transistor 120 is electrically coupled to the FET transistor 122.
- the gate terminals (G9), (G10) are electrically coupled together at the input terminal 124.
- the source terminal (S9) is electrically coupled to the primary output node 36.
- the drain terminal (D9) is electrically coupled to the source terminal (S10) at the output terminal 126.
- the output terminal 126 is electrically coupled to an input terminal 134.
- the terminal (D10) is electrically coupled to electrical ground.
- the inverter 54 receives an output voltage at the input terminal 124 from the inverter 52 and outputs an inverted amplified output voltage at the output terminal 126.
- the output terminal 136 is electrically coupled to an input terminal 144.
- the terminal (D12) is electrically coupled to electrical ground.
- the inverter 56 receives an output voltage at the input terminal 134 from the inverter 54 and outputs an inverted amplified output voltage at the output terminal 136.
- the inverter 58 includes a P-FET transistor 140, a FET transistor 142, an input terminal 144, and an output terminal 146.
- the P-FET transistor 140 includes a gate terminal (G 13), a source terminal (S13), and a drain terminal (D13).
- the FET transistor 142 includes a gate terminal (G14), a source terminal (S14), and a drain terminal (D14).
- the P-FET transistor 140 is electrically coupled to the FET transistor 142.
- the gate terminals (G13), (G14) are electrically coupled together at the input terminal 144.
- the source terminal (S13) is electrically coupled to the primary output node 36.
- the drain terminal (D13) is electrically coupled to the source terminal (S14) at the output terminal 146.
- the output terminal 146 is electrically coupled to an input terminal 154.
- the terminal (D14) is electrically coupled to electrical ground.
- the inverter 58 receives an output voltage at the input terminal 144 from the inverter 56 and outputs an inverted amplified output voltage at the output terminal 146.
- the inverter 60 includes a P-FET transistor 150, a FET transistor 152, an input terminal 154, and an output terminal 156.
- the P-FET transistor 150 includes a gate terminal (G 15), a source terminal (S15), and a drain terminal (D15).
- the FET transistor 152 includes a gate terminal (G16), a source terminal (S16), and a drain terminal (D 16).
- the P-FET transistor 150 is electrically coupled to the FET transistor 152.
- the gate terminals (G15), (G16) are electrically coupled together at the input terminal 154.
- the source terminal (S15) is electrically coupled to the primary output node 36.
- the drain terminal (D15) is electrically coupled to the source terminal (S16) at the output terminal 156.
- the linear voltage regulator 14 could be constructed by removing inverters 52, 54, 56, 58, 60 where inverter 82 would be directly electrically coupled to the P-FET transistor 62.
- the number of inverters in the chain of inverters to amplify the voltage from the comparator circuit 50 can be greater than or less than the number of inverters shown in the chain of inverters of Figure 1 .
- the P-FET transistor 62 is provided to remove voltage deviations at the primary output node 36.
- the P-FET transistor 62 is provided to remove frequency components of the output voltage in a second frequency range.
- the P-FET transistor 62 includes a gate terminal (G2), a source terminal (S2), and a drain terminal (D2).
- the gate terminal (G2) is electrically coupled to the output terminal 156 of the inverter 60.
- the source terminal (S2) is electrically coupled to the voltage source 12.
- the drain terminal (D2) is electrically coupled to the primary node 36.
- the resistor 18 is electrically between the primary output node 36 and electrical ground. The resistor 18 corresponds to a load receiving the output voltage from the linear voltage regulator 14.
- the P-FET transistor 62 When the P-FET transistor 62 receives a high logic voltage from the inverter 60 at the gate terminal (G2), the P-FET transistor 62 decreases current flowing therethrough to reduce the output voltage on the primary output node 36 in response to the high logic voltage. Alternately, when the P-FET transistor 62 receives a low logic voltage from the inverter 60 at the gate terminal (G2), the P-FET transistor 62 increases current flowing therethrough to increase the output voltage on the primary output node 36 in response to the low logic voltage.
- a voltage curve 170 corresponds to an exemplary output voltage generated by the voltage source 12. As shown, the voltage curve 170 has oscillatory shape over time.
- a voltage curve 180 corresponds to an output voltage generated by the linear voltage regulator 14 at the primary output node 36. As shown, the voltage curve 180 is relatively constant over time as desired.
- a voltage curve 190 corresponds to an output voltage at the output terminal 96 of the comparator 50.
- a voltage curve 200 corresponds to a voltage received at the gate terminal (G2) of the P-FET transistor 62 for controlling operation of the P-FET transistor 62.
- the circuit 20 of the linear voltage regulator 14 receives a first voltage from the voltage source 12.
- the circuit 20 has the primary output node 36.
- the circuit 20 removes frequency components of the first voltage in a first frequency range to obtain an output voltage at the primary output node 36.
- the circuit 22 of the linear voltage regulator 14 has inverters 80, 82 electrically coupled either directly or indirectly to the primary output node 36 to remove frequency components of the output voltage in a second frequency range.
- the second frequency range is greater than the first frequency range.
- the step 224 is implemented utilizing steps 230-240.
- the inverter 80 outputs a second voltage on the output terminal 96 that is less than the output voltage on the primary output node 36, when the output voltage at the primary output node 36 is increased.
- the P-FET transistor 62 reduces the output voltage on the primary output node 36 in response to the high logic voltage.
- the inverter 80 outputs the second voltage on the output terminal 96 that is greater than the output voltage on the primary output node 36, when the output voltage at the primary output node 36 is decreased.
- the inverter 82 outputs a low logic voltage on the output terminal 106 in response to the second voltage being greater than the output voltage.
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Description
- This application relates to a linear voltage regulator.
- Voltage regulators have been utilized to control voltages applied to devices. A problem with the voltage regulators is that the voltage regulators have not been able to effectively remove both high frequency noise and low frequency noise from a voltage source. Further, the voltage regulators utilize at least two relatively expensive comparator chips which utilize a relatively large amount of power (see e.g.
US2007/0188154 ) - Accordingly, the inventor herein has recognized a need for an improved voltage regulator that minimizes and/or eliminates the above-mentioned problems.
- A linear voltage regulator in accordance with an exemplary embodiment is provided. The linear voltage regulator includes a first circuit configured to receive the first voltage from a voltage source and to remove frequency components of the first voltage in a first frequency range to obtain an output voltage at a primary output node. The linear voltage regulator further includes a second circuit having first and second inverters electrically coupled to the primary output node of the first circuit. The second circuit is configured to receive the output voltage and to remove frequency components of the output voltage in a second frequency range. The second frequency range is greater than the first frequency range.
- A linear voltage regulator in accordance with another exemplary embodiment is provided. The linear voltage regulator includes a first inverter having a first input terminal and a first output terminal. The first input terminal is electrically coupled to the first output terminal. The first input terminal is further electrically coupled to a capacitor which is further coupled to electrical ground. The first inverter is further electrically coupled to a primary output node such a first voltage on the first output terminal is less than the output voltage at the primary output node. The linear voltage regulator further includes a second inverter having a second input terminal and a second output terminal. The second input terminal is electrically coupled to the first output terminal of the first inverter. The second inverter is further electrically coupled to the primary output node and receiving the first voltage from the first inverter. The linear voltage regulator further includes a p-channel field effect transistor (P-FET transistor) having a gate terminal, a drain terminal and a source terminal. The source terminal is electrically coupled to a voltage source. The drain terminal is coupled to the primary output node. The gate terminal electrically communicates either directly or indirectly with the second output terminal of the second inverter, such that when the output voltage at the primary output node is increased, the first voltage on the first output terminal of the first inverter is less than the output voltage on the primary output node which induces the second inverter to output a high logic voltage on the second output terminal. The P-FET transistor reduces the output voltage on the primary output node in response to the high logic voltage.
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Figure 1 is an electrical schematic of an electrical system having a linear voltage regulator in accordance with an exemplary embodiment; -
Figure 2 is an electrical schematic of a comparator circuit utilized in the linear voltage regulator ofFigure 1 ; -
Figure 3 is an electrical schematic of a plurality of inverters utilized in the linear voltage regulator ofFigure 1 ; -
Figure 4 is a schematic of a voltage signal output by a voltage source in the electrical system ofFigure 1 ; -
Figure 5 is a schematic of a voltage signal output on a primary output node of the linear voltage regulator ofFigure 1 ; -
Figure 6 is a schematic of a voltage signal output on a node in the comparator circuit ofFigure 2 ; -
Figure 7 is a schematic of a voltage signal output on a PFET transistor utilized in the linear voltage regulator ofFigure 1 ; and -
Figures 8-9 are flowcharts of a method for regulating a voltage using the linear voltage regulator ofFigure 1 in accordance with another exemplary embodiment. - Referring to
Figure 1 , anelectrical system 10 having alinear voltage regulator 14 in accordance with an exemplary embodiment is illustrated. The electrical system further includes avoltage source 12 and aload 18. An advantage of thelinear voltage regulator 14 is that the regulator is able to output a voltage that has minimal voltage deviation for voltage-sensitive load devices. - The
voltage source 12 is provided to output a voltage that may deviate from a desired voltage level. Thevoltage source 12 is electrically coupled to thelinear voltage regulator 14. - The
linear voltage regulator 14 is provided to receive the voltage from thevoltage source 12 and to output a voltage that minimal voltage deviation from a desired voltage level. Thelinear voltage regulator 14 includes acircuit 20 and acircuit 22. - The
circuit 20 is provided to remove frequency components of the voltage received fromvoltage source 12 in a first frequency range to obtain an output voltage at theprimary voltage node 36 with reduced voltage deviation. In one exemplary embodiment, thecircuit 20 is configured to remove frequency components of the voltage received from thevoltage source 12 in the frequency range of 0 to 10 Megahertz. Of course, in alternative embodiments ofcircuit 20, thecircuit 20 can remove frequency components in other frequency ranges. Thecircuit 20 includes avoltage reference device 30, anoperational amplifier 32, and a P-FET transistor 34. Theoperational amplifier 32 has an inverting input terminal "-", a non-inverting input terminal "+", and an output terminal. The P-FET transistor has a gate terminal (G1), a source terminal (S1), and a drain terminal (D1). Thevoltage reference device 30 is electrically connected to the inverting input terminal "-" of theoperational amplifier 32. Thevoltage reference device 30 is configured to output a desired reference voltage level. The output terminal of theoperational amplifier 32 is electrically coupled to the gate terminal (G1) of the P-FET transistor 34. The non-inverting terminal "+" of theoperational amplifier 32 is electrically coupled to the drain terminal (D1) of the P-FET transistor 34 and further coupled to theprimary output node 36. - During operation of the
circuit 20, when the output voltage of thevoltage source 12 decreases, the voltage received by the non-inverting terminal "+" of theoperational amplifier 32 has a low logic voltage relative to a high logic voltage on the inverting terminal "-", which induces theoperational amplifier 32 to output a low logic voltage. In response to the low logic voltage on the gate terminal (G1) of the P-FET transistor 34, the P-FET transistor 34 increases current flowing from the source terminal (S1) to the drain terminal (D1) which causes the output voltage on theprimary output node 36 to increase. Alternately, when the output voltage of thevoltage source 12 increases, the voltage received by the non-inverting terminal "+" of theoperational amplifier 32 has a high logic voltage relative to a low logic voltage on the inverting terminal "-", which induces theoperational amplifier 32 to output a high logic voltage. In response to the high logic voltage on the gate terminal (G1) of the P-FET transistor 34, the P-FET transistor 34 decreases current flowing from the source terminal (S1) to the drain terminal (D1) which causes the output voltage on theprimary output node 36 to decrease. - The
circuit 22 is provided to remove frequency components of the voltage received fromvoltage source 12 in a second frequency range to obtain an output voltage at theprimary voltage node 36 with reduced voltage deviation. In one exemplary embodiment, thecircuit 22 is configured to remove frequency components of the voltage received from thevoltage source 12 in the frequency range of 10 Megahertz to 6 Gigahertz. Of course, in alternative embodiments ofcircuit 22, thecircuit 22 can remove frequency components in other frequency ranges. Thecircuit 22 includes acomparator circuit inverters FET transistor 62. - Referring to
Figures 1 and2 , thecomparator circuit 50 is provided to detect a voltage deviation on theprimary output node 36. Thecomparator circuit 50 includesinverters capacitor 84. - The
inverter 80 includes a P-FET transistor 90, aFET transistor 92, aninput terminal 94, and anoutput terminal 96. The P-FET transistor 90 includes a gate terminal (G3), a source terminal (S3), and a drain terminal (D3). TheFET transistor 92 includes a gate terminal (G4), a source terminal (S4), and a drain terminal (D4). The P-FET transistor 90 is electrically coupled to theFET transistor 92. In particular, the gate terminals (G3), (G4) are electrically coupled together at theinput terminal 94. The source terminal (S3) is electrically coupled to theprimary output node 36. The drain terminal (D3) is electrically coupled to the source terminal (S4) at theoutput terminal 96. Theoutput terminal 96 is electrically coupled to theinput terminal 94. The terminal (D4) is electrically coupled to electrical ground. Thecapacitor 84 is electrically coupled between theinput terminal 94 and electrical ground. During operation, a voltage on theoutput terminal 96 is less than the output voltage at theprimary output node 36. In particular, a voltage on theoutput terminal 96 is approximately one-half of the voltage at theprimary output node 36. - The
inverter 82 includes a P-FET transistor 100, aFET transistor 102, aninput terminal 104, and anoutput terminal 106. The P-FET transistor 100 includes a gate terminal (G5), a source terminal (S5), and a drain terminal (D5). TheFET transistor 102 includes a gate terminal (G6), a source terminal (S6), and a drain terminal (D6). The P-FET transistor 100 is electrically coupled to theFET transistor 102. In particular, the gate terminals (G5), (G6) are electrically coupled together at theinput terminal 104. Theinput terminal 104 is electrically coupled to theoutput terminal 96. The source terminal (S5) is electrically coupled to theprimary output node 36. The drain terminal (D5) is electrically coupled to the source terminal (S6) at theoutput terminal 106. Theoutput terminal 106 is electrically coupled to aninput terminal 114. The terminal (D6) is electrically coupled to electrical ground. - During operation of the
comparator circuit 50, when an output voltage at theprimary output node 36 is increased, the voltage on theoutput terminal 96 of theinverter 80 is less than the output voltage on theprimary output node 36 which induces theinverter 82 to output a high logic voltage on theoutput terminal 106. The high logic voltage is utilized to subsequently induce the P-FET transistor 62 to reduce the output voltage on theprimary output node 36 in response to the high logic voltage. Alternately, when the output voltage at theprimary output node 36 is decreased, the voltage on theoutput terminal 96 of theinverter 80 is greater than the output voltage on theprimary output node 36 which induces theinverter 82 to output a low logic voltage on theoutput terminal 106. The low logic voltage is subsequently utilized to induce the P-FET transistor 62 to increase the output voltage on theprimary output node 36 in response to the low logic voltage. - Referring to
Figures 1 and3 , the chain ofinverters comparator circuit 50 which is received by the gate terminal (G2) of the P-FET transistor 62. - The
inverter 52 includes a P-FET transistor 110, aFET transistor 112, aninput terminal 114, and anoutput terminal 116. The P-FET transistor 110 includes a gate terminal (G7), a source terminal (S7), and a drain terminal (D7). TheFET transistor 112 includes a gate terminal (G8), a source terminal (S8), and a drain terminal (D8). The P-FET transistor 110 is electrically coupled to theFET transistor 112. In particular, the gate terminals (G7), (G8) are electrically coupled together at theinput terminal 114. The source terminal (S7) is electrically coupled to theprimary output node 36. The drain terminal (D7) is electrically coupled to the source terminal (S8) at theoutput terminal 116. Theoutput terminal 116 is electrically coupled to aninput terminal 124. The terminal (D8) is electrically coupled to electrical ground. During operation, theinverter 52 receives an output voltage at theinput terminal 114 from thecomparator circuit 50 and outputs an inverted amplified output voltage at theoutput terminal 116. - The
inverter 54 includes a P-FET transistor 120, aFET transistor 122, aninput terminal 124, and anoutput terminal 126. The P-FET transistor 120 includes a gate terminal (G9), a source terminal (S9), and a drain terminal (D9). TheFET transistor 122 includes a gate terminal (G10), a source terminal (S10), and a drain terminal (D10). The P-FET transistor 120 is electrically coupled to theFET transistor 122. In particular, the gate terminals (G9), (G10) are electrically coupled together at theinput terminal 124. The source terminal (S9) is electrically coupled to theprimary output node 36. The drain terminal (D9) is electrically coupled to the source terminal (S10) at theoutput terminal 126. Theoutput terminal 126 is electrically coupled to aninput terminal 134. The terminal (D10) is electrically coupled to electrical ground. During operation, theinverter 54 receives an output voltage at theinput terminal 124 from theinverter 52 and outputs an inverted amplified output voltage at theoutput terminal 126. - The
inverter 56 includes a P-FET transistor 130, aFET transistor 132, aninput terminal 134, and anoutput terminal 136. The P-FET transistor 130 includes a gate terminal (G11), a source terminal (S11), and a drain terminal (D11). TheFET transistor 132 includes a gate terminal (G 12), a source terminal (S12), and a drain terminal (D 12). The P-FET transistor 130 is electrically coupled to theFET transistor 132. In particular, the gate terminals (G11), (G12) are electrically coupled together at theinput terminal 134. The source terminal (S11) is electrically coupled to theprimary output node 36. The drain terminal (D11) is electrically coupled to the source terminal (S12) at theoutput terminal 136. Theoutput terminal 136 is electrically coupled to aninput terminal 144. The terminal (D12) is electrically coupled to electrical ground. During operation, theinverter 56 receives an output voltage at theinput terminal 134 from theinverter 54 and outputs an inverted amplified output voltage at theoutput terminal 136. - The
inverter 58 includes a P-FET transistor 140, aFET transistor 142, aninput terminal 144, and anoutput terminal 146. The P-FET transistor 140 includes a gate terminal (G 13), a source terminal (S13), and a drain terminal (D13). TheFET transistor 142 includes a gate terminal (G14), a source terminal (S14), and a drain terminal (D14). The P-FET transistor 140 is electrically coupled to theFET transistor 142. In particular, the gate terminals (G13), (G14) are electrically coupled together at theinput terminal 144. The source terminal (S13) is electrically coupled to theprimary output node 36. The drain terminal (D13) is electrically coupled to the source terminal (S14) at theoutput terminal 146. Theoutput terminal 146 is electrically coupled to aninput terminal 154. The terminal (D14) is electrically coupled to electrical ground. During operation, theinverter 58 receives an output voltage at theinput terminal 144 from theinverter 56 and outputs an inverted amplified output voltage at theoutput terminal 146. - The
inverter 60 includes a P-FET transistor 150, aFET transistor 152, aninput terminal 154, and anoutput terminal 156. The P-FET transistor 150 includes a gate terminal (G 15), a source terminal (S15), and a drain terminal (D15). TheFET transistor 152 includes a gate terminal (G16), a source terminal (S16), and a drain terminal (D 16). The P-FET transistor 150 is electrically coupled to theFET transistor 152. In particular, the gate terminals (G15), (G16) are electrically coupled together at theinput terminal 154. The source terminal (S15) is electrically coupled to theprimary output node 36. The drain terminal (D15) is electrically coupled to the source terminal (S16) at theoutput terminal 156. Theoutput terminal 156 is electrically coupled to a gate terminal (G2) of the P-FET transistor 62. The terminal (D16) is electrically coupled to electrical ground. During operation, theinverter 60 receives an output voltage at theinput terminal 154 from theinverter 58 and outputs an inverted amplified output voltage at theoutput terminal 156. - It should be noted that in an alternative embodiment, the
linear voltage regulator 14 could be constructed by removinginverters inverter 82 would be directly electrically coupled to the P-FET transistor 62. Further, in other alternative embodiments, the number of inverters in the chain of inverters to amplify the voltage from thecomparator circuit 50 can be greater than or less than the number of inverters shown in the chain of inverters ofFigure 1 . - Referring to
Figure 1 , the P-FET transistor 62 is provided to remove voltage deviations at theprimary output node 36. In particular, the P-FET transistor 62 is provided to remove frequency components of the output voltage in a second frequency range. The P-FET transistor 62 includes a gate terminal (G2), a source terminal (S2), and a drain terminal (D2). The gate terminal (G2) is electrically coupled to theoutput terminal 156 of theinverter 60. The source terminal (S2) is electrically coupled to thevoltage source 12. The drain terminal (D2) is electrically coupled to theprimary node 36. Theresistor 18 is electrically between theprimary output node 36 and electrical ground. Theresistor 18 corresponds to a load receiving the output voltage from thelinear voltage regulator 14. During operation, when the P-FET transistor 62 receives a high logic voltage from theinverter 60 at the gate terminal (G2), the P-FET transistor 62 decreases current flowing therethrough to reduce the output voltage on theprimary output node 36 in response to the high logic voltage. Alternately, when the P-FET transistor 62 receives a low logic voltage from theinverter 60 at the gate terminal (G2), the P-FET transistor 62 increases current flowing therethrough to increase the output voltage on theprimary output node 36 in response to the low logic voltage. - Referring to
Figures 4-7 , a brief explanation of exemplary schematics of signals generated by thelinear voltage regulator 14 will now be provided. Referring toFigure 4 , avoltage curve 170 corresponds to an exemplary output voltage generated by thevoltage source 12. As shown, thevoltage curve 170 has oscillatory shape over time. Referring toFigure 5 , avoltage curve 180 corresponds to an output voltage generated by thelinear voltage regulator 14 at theprimary output node 36. As shown, thevoltage curve 180 is relatively constant over time as desired. Referring toFigure 6 , avoltage curve 190 corresponds to an output voltage at theoutput terminal 96 of thecomparator 50. Referring toFigure 7 , avoltage curve 200 corresponds to a voltage received at the gate terminal (G2) of the P-FET transistor 62 for controlling operation of the P-FET transistor 62. - Referring to
Figures 8-9 , a flowchart of a method for regulating a voltage utilizing thelinear voltage regulator 14 will now be described. - At
step 220, thecircuit 20 of thelinear voltage regulator 14 receives a first voltage from thevoltage source 12. Thecircuit 20 has theprimary output node 36. - At
step 222, thecircuit 20 removes frequency components of the first voltage in a first frequency range to obtain an output voltage at theprimary output node 36. - At
step 224, thecircuit 22 of thelinear voltage regulator 14 hasinverters primary output node 36 to remove frequency components of the output voltage in a second frequency range. The second frequency range is greater than the first frequency range. Thestep 224 is implemented utilizing steps 230-240. - At
step 230, theinverter 80 outputs a second voltage on theoutput terminal 96 that is less than the output voltage on theprimary output node 36, when the output voltage at theprimary output node 36 is increased. - At
step 232, theinverter 82 outputs a high logic voltage on theoutput terminal 106 in response to the second voltage being less than the output voltage. - At
step 234, the P-FET transistor 62 reduces the output voltage on theprimary output node 36 in response to the high logic voltage. - At
step 236, theinverter 80 outputs the second voltage on theoutput terminal 96 that is greater than the output voltage on theprimary output node 36, when the output voltage at theprimary output node 36 is decreased. - At
step 238, theinverter 82 outputs a low logic voltage on theoutput terminal 106 in response to the second voltage being greater than the output voltage. - At
step 240, the P-FET transistor 62 increases the output voltage on theprimary output node 36 in response to the low logic voltage. Afterstep 240, the method returns to step 220. - The linear voltage regulator provides a substantial advantage over other regulators. In particular, the linear voltage regulator provides a technical effect of removing highfrequency components of a voltage utilizing a plurality of inverters.
- While the invention is described with reference to an exemplary embodiment, it will be understood by those skilled in the art that various changes may be made and equivalent elements may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to the teachings of the invention to adapt to a particular situation without departing from the scope thereof. Therefore, it is intended that the invention not be limited the embodiment disclosed for carrying out this invention, but that the invention includes all embodiments falling with the scope of the intended claims. Moreover, the use of the term's first, second, etc. does not denote any order of importance, but rather the term's first, second, etc. are used to distinguish one element from another.
Claims (9)
- A linear voltage regulator, comprising:a first circuit (20) configured to receive a first voltage from a voltage source and to remove frequency components of the first voltage in a first frequency range to obtain an output voltage at a primary output node; anda second circuit (22) having first and second inverters electrically coupled to the primary output node of the first circuit, the second circuit configured to receive the output voltage and to remove frequency components of the output voltage in a second frequency range, the frequencies in the second frequency range being higher than the frequencies in the first frequency range;the first inverter having a first input terminal and a first output terminal, the first input terminal being electrically coupled to the first output terminal, the first input terminal being further electrically coupled to a capacitor which is further coupled to electrical ground, the first inverter being further electrically coupled to the primary output node such a second voltage on the first output terminal is less than the output voltage at the primary output node; andthe second inverter having a second input terminal and a second output terminal, the second input terminal being electrically coupled to the first output terminal of the first inverter, the second inverter being further electrically coupled to the primary output node; and the second circuit further comprising a P-FET (62) transistor having a gate terminal, a drain terminal and a source terminal, the source terminal being electrically coupled to the voltage source, the drain terminal being electrically coupled to the primary output node, the gate terminal electrically communicating either directly or indirectly with the second output terminal of the second inverter, such that when the output voltage at the primary output node is increased, the second voltage on the first output terminal of the first inverter is less than the output voltage on the primary output node which induces the second inverter to output a high logic voltage on the second output terminal, and the P-FET transistor reduces the output voltage on the primary output node in response to the high logic voltage.
- The linear voltage regulator of claim 1, wherein when the output voltage at the primary output node is decreased, the second voltage on the first output terminal of the first inverter is greater than the output voltage on the primary output node which induces the second inverter to output a low logic voltage on the second output terminal, and the P-FET transistor increases the output voltage on the primary output node in response to the low logic voltage.
- The linear voltage regulator of claim 1, further comprising at least third and fourth inverters electrically coupled in series between the second output terminal of the second inverter and the gate terminal of the P-FET transistor.
- The linear voltage regulator of claim 1, wherein the first frequency range is 0 to 10 Megahertz.
- The linear voltage regulator of claim 1, wherein the second frequency range is 10 Megahertz to 6 Gigahertz.
- A method for regulating a voltage using a linear voltage regulator, the linear voltage regulator having a first circuit (20) with a primary output node and a second circuit (22) having first and second inverters electrically coupled to the primary output node, the method comprising:receiving a first voltage from a voltage source at the first circuit;removing frequency components of the first voltage in a first frequency range to obtain an output voltage at the primary output node utilizing the first circuit; andremoving frequency components of the output voltage in a second frequency range utilizing the first and second inverters of the second circuit, the second frequency range being greater than the first frequency range;the second circuit further including a P-FET transistor (62), the first inverter having a first input terminal and a first output terminal, the first input terminal being electrically coupled to the first output terminal, the first input terminal being further electrically coupled to a capacitor which is further coupled to electrical ground, the first inverter being further electrically coupled to the primary output node, the second inverter having a second input terminal and a second output terminal, the second input terminal being electrically coupled to the first output terminal of the first inverter, the second inverter being further electrically coupled to the primary output node, the P-FET transistor having a gate terminal, a drain terminal and a source terminal, the source terminal being electrically coupled to the voltage source, the drain terminal being electrically coupled to the primary output node, the gate terminal electrically communicating either directly or indirectly with the second output terminal of the second inverter, wherein removing frequency components of the output voltage in the second frequency range utilizing the second circuit, comprises:outputting a second voltage on the first output terminal of the first inverter that is less than the output voltage on the primary output node, when the output voltage at the primary output node is increased;outputting a high logic voltage from the second inverter on the second output terminal in response to the second voltage being less than the output voltage; andreducing the output voltage on the primary output node in response to the high logic voltage utilizing the P-FET transistor.
- The method of claim 6, wherein removing frequency components of the output voltage in the second frequency range utilizing the second circuit, further comprises:outputting the second voltage on the first output terminal of the first inverter that is greater than the output voltage on the primary output node, when the output voltage at the primary output node is decreased;outputting a low logic voltage from the second inverter on the second output terminal in response to the second voltage being greater than the output voltage; andincreasing the output voltage on the primary output node in response to the low logic voltage utilizing the P-FET transistor.
- The method of claim 6, wherein the first frequency range is 0 to 10 Megahertz.
- The method of claim 6, wherein the second frequency range is 10 Megahertz to 6 Gigahertz.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/847,416 US7847529B2 (en) | 2007-08-30 | 2007-08-30 | Dual loop linear voltage regulator with high frequency noise reduction |
US11/847,461 US7855534B2 (en) | 2007-08-30 | 2007-08-30 | Method for regulating a voltage using a dual loop linear voltage regulator with high frequency noise reduction |
PCT/EP2008/060565 WO2009027220A1 (en) | 2007-08-30 | 2008-08-12 | Linear voltage regulator |
Publications (2)
Publication Number | Publication Date |
---|---|
EP2183653A1 EP2183653A1 (en) | 2010-05-12 |
EP2183653B1 true EP2183653B1 (en) | 2013-01-02 |
Family
ID=39938407
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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EP08787129A Active EP2183653B1 (en) | 2007-08-30 | 2008-08-12 | Linear voltage regulator |
Country Status (5)
Country | Link |
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EP (1) | EP2183653B1 (en) |
JP (1) | JP5295240B2 (en) |
KR (1) | KR20100053560A (en) |
CN (1) | CN101784975B (en) |
WO (1) | WO2009027220A1 (en) |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4952863A (en) * | 1989-12-20 | 1990-08-28 | International Business Machines Corporation | Voltage regulator with power boost system |
JP2006053829A (en) * | 2004-08-13 | 2006-02-23 | Mitsunori Katsu | Semiconductor integrated circuit incorporating voltage regulator |
US7301320B2 (en) * | 2005-01-21 | 2007-11-27 | International Business Machines Corporation | On-chip high frequency power supply noise sensor |
TW200731046A (en) * | 2006-02-14 | 2007-08-16 | Richtek Techohnology Corp | Linear voltage regulator and control method thereof |
US7508177B2 (en) * | 2007-06-08 | 2009-03-24 | Freescale Semiconductor, Inc. | Method and circuit for reducing regulator output noise |
JP4642830B2 (en) * | 2007-11-06 | 2011-03-02 | 株式会社リコー | Power supply apparatus and power supply method thereof |
-
2008
- 2008-08-12 JP JP2010522300A patent/JP5295240B2/en not_active Expired - Fee Related
- 2008-08-12 CN CN200880103775.4A patent/CN101784975B/en active Active
- 2008-08-12 WO PCT/EP2008/060565 patent/WO2009027220A1/en active Application Filing
- 2008-08-12 EP EP08787129A patent/EP2183653B1/en active Active
- 2008-08-12 KR KR1020107003465A patent/KR20100053560A/en not_active Application Discontinuation
Also Published As
Publication number | Publication date |
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CN101784975B (en) | 2012-12-26 |
JP2010537335A (en) | 2010-12-02 |
EP2183653A1 (en) | 2010-05-12 |
WO2009027220A1 (en) | 2009-03-05 |
KR20100053560A (en) | 2010-05-20 |
CN101784975A (en) | 2010-07-21 |
JP5295240B2 (en) | 2013-09-18 |
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