CN101784975B - Linear voltage regulator - Google Patents

Linear voltage regulator Download PDF

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CN101784975B
CN101784975B CN200880103775.4A CN200880103775A CN101784975B CN 101784975 B CN101784975 B CN 101784975B CN 200880103775 A CN200880103775 A CN 200880103775A CN 101784975 B CN101784975 B CN 101784975B
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voltage
output
phase inverter
terminal
electrically coupled
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CN101784975A (en
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金圣元
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International Business Machines Corp
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International Business Machines Corp
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Priority claimed from US11/847,416 external-priority patent/US7847529B2/en
Priority claimed from US11/847,461 external-priority patent/US7855534B2/en
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)

Abstract

A linear voltage regulator is provided. The linear voltage regulator includes a first circuit configured to receive the first voltage from a voltage source and to remove frequency components of the first voltage in a first frequency range to obtain an output voltage at a primaryoutput node. The linear voltage regulator further includes a second circuit having first and second inverterselectrically coupled to the primaryoutput node of the first circuit. The second circuit is configured to receive the output voltage and to remove frequency components of the output voltage in a second frequency range. The second frequency range is greater than the first frequency range.

Description

Linear voltage regulator
Technical field
The application relates to linear voltage regulator.
Background technology
Working voltage regulator control puts on the voltage of device.The problem of voltage regulator is: voltage regulator can not be eliminated high frequency noise and the low-frequency noise from voltage source effectively simultaneously.In addition, voltage regulator uses at least two relatively costly comparer chips, and said comparer chip uses a large amount of relatively electric power.
Correspondingly, the inventor recognizes at this needs a kind of improved voltage regulator that minimizes and/or eliminate the problems referred to above.
Summary of the invention
Linear voltage regulator according to an exemplary embodiment is provided.Said linear voltage regulator comprises first circuit, and it is configured to receive from first voltage of voltage source and eliminates the frequency content of said first voltage in the first frequency scope to obtain output voltage at main output node place.Said linear voltage regulator also comprises second circuit, and it has first and second phase inverters of the said main output node that is electrically coupled to said first circuit.Said second circuit is configured to receive said output voltage and eliminates the frequency content of said output voltage in the second frequency scope.Said second frequency scope is greater than said first frequency scope.
Linear voltage regulator according to another exemplary embodiment is provided.Said linear voltage regulator comprises first phase inverter with first input end and first output terminal.Said first input end is electrically coupled to said first output terminal.Said first input end also is electrically coupled to capacitor, and said capacitor also is coupled to the ground on electric.Said first phase inverter also is electrically coupled to main output node, makes first voltage on said first output terminal less than the said output voltage at said main output node place.Said linear voltage regulator also comprises second phase inverter with second input end and second output terminal.Said second input end is electrically coupled to said first output terminal of said first phase inverter.Said second phase inverter also is electrically coupled to said main output node and receives said first voltage from said first phase inverter.Said linear voltage regulator also comprises the p slot field-effect transistor with gate terminal, drain electrode end and source terminal, i.e. P-FET transistor.Said source terminal is electrically coupled to voltage source.Said drain electrode end is coupled to said main output node.Said gate terminal is directly or indirectly communicated by letter with said second output terminal of said second phase inverter with electric means; Make when the said output voltage at said main output node place increases; Said first voltage on said first output terminal of said first phase inverter is less than the said output voltage on the said main output node, and this causes said second phase inverter on said second output terminal, to export high logic voltage.Said P-FET transistor reduces said output voltage on the said main output node to respond said high logic voltage.
Description of drawings
Fig. 1 is the electrical schematics according to the electrical system with linear voltage regulator of an exemplary embodiment;
Fig. 2 is the electrical schematics of the comparator circuit that in the linear voltage regulator of Fig. 1, uses;
Fig. 3 is the electrical schematics of a plurality of phase inverters of in the linear voltage regulator of Fig. 1, using;
Fig. 4 is the synoptic diagram by the voltage signal of the output of the voltage source in the electrical system of Fig. 1;
Fig. 5 is the synoptic diagram of the voltage signal on the main output node of the linear voltage regulator of Fig. 1, exported;
Fig. 6 is the synoptic diagram of the voltage signal exported on the node in the comparator circuit of Fig. 2;
Fig. 7 is the synoptic diagram of the voltage signal exported on the PFET transistor that in the linear voltage regulator of Fig. 1, uses; And
Fig. 8-the 9th is according to the process flow diagram of method of linear voltage regulator regulation voltage that is used to use Fig. 1 of another exemplary embodiment.
Embodiment
With reference to figure 1, show the electrical system with linear voltage regulator 14 100 according to an exemplary embodiment.Said electrical system also comprises voltage source 12 and load 18.The advantage of linear voltage regulator 14 is the voltage that this regulator can have the minimum voltage deviation to the load device output of voltage-sensitive.
Provide voltage source 12 possibly depart from the voltage of required voltage level with output.Voltage source 12 is electrically coupled to linear voltage regulator 14.
Provide linear voltage regulator 14 also to export the voltage that has the minimum voltage deviation with the required voltage level to receive from the voltage of voltage source 12.Linear voltage regulator 14 comprises circuit 20 and circuit 22.
Provide circuit 20 eliminating the frequency content of voltage in the first frequency scope that receives from voltage source 12, so that obtain to have the output voltage of the voltage deviation that reduces at principal voltage node 36 places.In one exemplary embodiment, circuit 20 is configured to eliminate the frequency content of voltage in 0 to 10MHz frequency range that receives from voltage source 12.Certainly, in the alternative of circuit 20, circuit 20 can be eliminated the frequency content in other frequency ranges.Circuit 20 comprises voltage reference device 30, operational amplifier 32 and P-FET transistor 34.Operational amplifier 32 has inverting input "-", non-inverting input "+" and output terminal.The P-FET transistor has gate terminal (G1), source terminal (S1) and drain electrode end (D1).Voltage reference device 30 is electrically coupled to the inverting input "-" of operational amplifier 32.Voltage reference device 30 is configured to export required reference voltage level.The output terminal of operational amplifier 32 is electrically coupled to the gate terminal (G1) of P-FET transistor 34.The non-oppisite phase end "+" of operational amplifier 32 is electrically coupled to the drain electrode end (D1) of P-FET transistor 34 and also is electrically coupled to main output node 36.
Duration of work at circuit 20; When the output voltage of voltage source 12 reduces; The voltage that is received by the non-oppisite phase end "+" of operational amplifier 32 has low logic voltage (with respect to the high logic voltage on the end of oppisite phase "-"), and this causes the low logic voltage of operational amplifier 32 outputs.In response to the low logic voltage on the gate terminal (G1) of P-FET transistor 34, P-FET transistor 32 increases the electric current that flows to drain electrode end (D1) from source terminal (S1), and this causes the output voltage on the main output node 36 to increase.Alternatively, when the output voltage of voltage source 12 increased, the voltage that is received by the non-oppisite phase end "+" of operational amplifier 32 had high logic voltage (with respect to the low logic voltage on the end of oppisite phase "-"), and this causes the high logic voltage of operational amplifier 32 outputs.In response to the high logic voltage on the gate terminal (G1) of P-FET transistor 34, P-FET transistor 34 reduces to flow to from source terminal (S1) electric current of drain electrode end (D1), and this causes the output voltage on the main output node 36 to reduce.
Provide circuit 22 eliminating the frequency content of voltage in the second frequency scope that receives from voltage source 12, so that obtain to have the output voltage of the voltage deviation that reduces at principal voltage node 36 places.In one exemplary embodiment, circuit 22 is configured to eliminate the voltage that receives from voltage source 12 in the frequency content of 10MHz in the frequency range of 6GHz.Certainly, in the alternative of circuit 22, circuit 22 can be eliminated the frequency content in other frequency ranges.Circuit 22 comprises comparator circuit 62,50, phase inverter 52,54,56,58,60 and P-FET transistor 62.
With reference to Fig. 1 and 2, provide comparator circuit 50 to detect the voltage deviation on the main output node 36.Comparator circuit 50 comprises phase inverter 80,82 and capacitor 84.
Phase inverter 80 comprises P-FET transistor 90, FET transistor 92, input end 94 and output terminal 96.P-FET transistor 90 comprises gate terminal (G3), source terminal (S3) and drain electrode end (D3).FET transistor 92 comprises gate terminal (G4), source terminal (S4) and drain electrode end (D4).P-FET transistor 90 is electrically coupled to FET transistor 92.Specifically, gate terminal (G3), (G4) are at input end 94 places by electric coupling together.Source terminal (S3) is electrically coupled to main output node 36.Drain electrode end (D3) is electrically coupled to source terminal (S4) at output terminal 96 places.Output terminal 96 is electrically coupled to input end 94.Drain electrode end (D4) is electrically coupled to the ground on electric.Capacitor 84 by electric coupling input end 94 and electric on ground between.During operation, the voltage on the output terminal 96 is less than the output voltage at main output node 36 places.Specifically, the voltage on the output terminal 96 approximately is voltage half the at main output node 36 places.
Phase inverter 82 comprises P-FET transistor 100, FET transistor 102, input end 104 and output terminal 106.P-FET transistor 100 comprises gate terminal (G5), source terminal (S5) and drain electrode end (D5).FET transistor 102 comprises gate terminal (G6), source terminal (S6) and drain electrode end (D6).P-FET transistor 100 is electrically coupled to FET transistor 102.Specifically, gate terminal (G5), (G6) are at input end 104 places by electric coupling together.Input end 104 is electrically coupled to output terminal 96.Source terminal (S5) is electrically coupled to main output node 36.Drain electrode end (D5) is electrically coupled to source terminal (S6) at output terminal 106 places.Output terminal 106 is electrically coupled to input end 114.Drain electrode end (D6) is electrically coupled to the ground on electric.
At the duration of work of comparator circuit 50, when the output voltage at main output node 36 places increased, the voltage on the output terminal 96 of phase inverter 80 was less than the output voltage on the main output node 36, and this causes phase inverter 82 on output terminal 106, to export high logic voltage.High logic voltage is used for impelling subsequently P-FET transistor 62 to reduce output voltage on the main output node 36 to respond said high logic voltage.Alternatively, when the output voltage at main output node 36 places reduced, the voltage on the output terminal 96 of phase inverter 80 was greater than the output voltage on the main output node 36, and this causes phase inverter 82 on output terminal 106, to export low logic voltage.Low logic voltage is used for impelling subsequently P-FET transistor 62 to increase output voltage on the main output node 36 to respond said low logic voltage.
With reference to figure 1 and 3, provide phase inverter 52,54,56,58,60 chains to amplify output voltage from the gate terminal by P-FET transistor 62 (G2) reception of comparator circuit 50.
Phase inverter 52 comprises P-FET transistor 110, FET transistor 112, input end 114 and output terminal 116.P-FET transistor 110 comprises gate terminal (G7), source terminal (S7) and drain electrode end (D7).FET transistor 112 comprises gate terminal (G8), source terminal (S8) and drain electrode end (D8).P-FET transistor 110 is electrically coupled to FET transistor 112.Specifically, gate terminal (G7), (G8) are at input end 114 places by electric coupling together.Source terminal (S7) is electrically coupled to main output node 36.Drain electrode end (D7) is electrically coupled to source terminal (S8) at output terminal 116 places.Output terminal 116 is electrically coupled to input end 124.Drain electrode end (D8) is electrically coupled to the ground on electric.During operation, phase inverter 52 receives output voltage and the amplification output voltage after the output anti-phase of output terminal 116 places from comparator circuit 50 at input end 114 places.
Phase inverter 54 comprises P-FET transistor 120, FET transistor 122, input end 124 and output terminal 126.P-FET transistor 120 comprises gate terminal (G9), source terminal (S9) and drain electrode end (D9).FET transistor 122 comprises gate terminal (G10), source terminal (S10) and drain electrode end (D10).P-FET transistor 120 is electrically coupled to FET transistor 122.Specifically, gate terminal (G9), (G10) are at input end 124 places by electric coupling together.Source terminal (S9) is electrically coupled to main output node 36.Drain electrode end (D9) is electrically coupled to source terminal (S10) at output terminal 126 places.Output terminal 126 is electrically coupled to input end 134.Drain electrode end (D10) is electrically coupled to the ground on electric.During operation, phase inverter 54 receives output voltage and the amplification output voltage after the output anti-phase of output terminal 126 places from phase inverter 52 at input end 124 places.
Phase inverter 56 comprises P-FET transistor 130, FET transistor 132, input end 134 and output terminal 136.P-FET transistor 130 comprises gate terminal (G11), source terminal (S11) and drain electrode end (D11).FET transistor 132 comprises gate terminal (G12), source terminal (S12) and drain electrode end (D12).P-FET transistor 130 is electrically coupled to FET transistor 132.Specifically, gate terminal (G11), (G12) are at input end 134 places by electric coupling together.Source terminal (S11) is electrically coupled to main output node 36.Drain electrode end (D11) is electrically coupled to source terminal (S12) at output terminal 136 places.Output terminal 136 is electrically coupled to input end 144.Drain electrode end (D12) is electrically coupled to the ground on electric.During operation, phase inverter 56 receives output voltage and the amplification output voltage after the output anti-phase of output terminal 136 places from phase inverter 54 at input end 134 places.
Phase inverter 58 comprises P-FET transistor 140, FET transistor 142, input end 144 and output terminal 146.P-FET transistor 140 comprises gate terminal (G13), source terminal (S13) and drain electrode end (D13).FET transistor 142 comprises gate terminal (G14), source terminal (S14) and drain electrode end (D14).P-FET transistor 140 is electrically coupled to FET transistor 142.Specifically, gate terminal (G13), (G14) are at input end 144 places by electric coupling together.Source terminal (S13) is electrically coupled to main output node 36.Drain electrode end (D13) is electrically coupled to source terminal (S14) at output terminal 146 places.Output terminal 146 is electrically coupled to input end 154.Drain electrode end (D14) is electrically coupled to the ground on electric.During operation, phase inverter 58 receives output voltage and the amplification output voltage after the output anti-phase of output terminal 146 places from phase inverter 56 at input end 144 places.
Phase inverter 60 comprises P-FET transistor 150, FET transistor 152, input end 154 and output terminal 156.P-FET transistor 150 comprises gate terminal (G15), source terminal (S15) and drain electrode end (D15).FET transistor 152 comprises gate terminal (G16), source terminal (S16) and drain electrode end (D16).P-FET transistor 150 is electrically coupled to FET transistor 152.Specifically, gate terminal (G15), (G16) are at input end 154 places by electric coupling together.Source terminal (S15) is electrically coupled to main output node 36.Drain electrode end (D15) is electrically coupled to source terminal (S16) at output terminal 156 places.Output terminal 156 is electrically coupled to the gate terminal (G2) of P-FET transistor 62.Drain electrode end (D16) is electrically coupled to the ground on electric.During operation, phase inverter 60 receives output voltage and the amplification output voltage after the output anti-phase of output terminal 156 places from phase inverter 58 at input end 154 places.
Be to be noted that in an alternative can make up linear voltage regulator 14 through removing phase inverter 52,54,56,58,60, wherein phase inverter 82 will directly be electrically coupled to P-FET transistor 62.In addition, in other alternatives, be used to amplify the quantity of the phase inverter shown in the chain of inverters that quantity from the phase inverter of the voltage of comparator circuit 50 can be greater than or less than Fig. 1 in the chain of inverters.
With reference to figure 1, provide P-FET transistor 62 to eliminate the voltage deviation at main output node 36 places.Specifically, provide P-FET transistor 62 to eliminate the frequency content of output voltage in the second frequency scope.P-FET transistor 62 comprises gate terminal (G2), source terminal (S2) and drain electrode end (D2).Gate terminal (G2) is electrically coupled to the output terminal 156 of phase inverter 60.Source terminal (S2) is electrically coupled to voltage source 12.Drain electrode end (D2) is electrically coupled to host node 36.Resistor 18 on electric main output node 36 and electric on ground between.Resistor 18 is corresponding to the load that receives from the output voltage of linear voltage regulator 14.During operation, when P-FET transistor 62 when gate terminal (G2) locates to receive the high logic voltage from phase inverter 60, the electric current that P-FET transistor 62 reduces to flow through at this place is to reduce the output voltage on the main output node 36, so that respond said high logic voltage.Alternatively, when P-FET transistor 62 when gate terminal (G2) locates to receive the low logic voltage from phase inverter 60, P-FET transistor 62 increase flow through this place electric current to increase the output voltage on the main output node 36, so that respond said low logic voltage.
With reference to figure 4-7, the brief description of the illustrative diagram of the signal that is produced by linear voltage regulator 14 will be provided now.With reference to figure 4, the exemplary output voltage that voltage curve 170 produces corresponding to voltage source 12.As illustrating, voltage curve 170 presents wobble shape along with the increase of time.With reference to figure 5, the output voltage that voltage curve 180 is produced by linear voltage regulator 14 corresponding to main output node 36 places.As illustrating, voltage curve 180 as constant relatively along with the increase of time expecting.With reference to figure 6, voltage curve 190 is corresponding to the output voltage at output terminal 96 places of comparer 50.With reference to figure 7, voltage curve 200 is controlled the voltage of the work of P-FET transistor 62 corresponding to being used to of locating to receive in the gate terminal (G2) of P-FET transistor 62.
With reference to figure 8-9, use description to use the process flow diagram of the method for linear voltage regulator 14 regulation voltages now.
In step 220, first voltage that the circuit 20 of linear voltage regulator 14 receives from voltage source 12.Circuit 20 has main output node 36.
In step 222, circuit 20 is eliminated the frequency content of said first voltage in the first frequency scope to obtain output voltage at main output node 36 places.
In step 224, the circuit 22 of linear voltage regulator 14 has phase inverter 80,82, and the latter directly or indirectly is electrically coupled to main output node 36 to eliminate the frequency content of said output voltage in the second frequency scope.Said second frequency scope is greater than said first frequency scope.Step 224 uses step 230-240 to realize.
In step 230, when the output voltage at main output node 36 places increased, phase inverter 80 was at second voltage of exporting on the output terminal 96 less than the output voltage on the main output node 36.
In step 232, phase inverter 82 is exported high logic voltage to respond said second voltage less than said output voltage on output terminal 106.
In step 234, P-FET transistor 62 reduces output voltage on the main output node 36 to respond said high logic voltage.
In step 236, when the output voltage at main output node 36 places reduced, phase inverter 80 was at second voltage of exporting on the output terminal 96 greater than the said output voltage on the main output node 36.
In step 238, phase inverter 82 is exported low logic voltage to respond said second voltage greater than said output voltage on output terminal 106.
In step 240, the output voltage on the main output node 36 of P-FET transistor 62 increases is to respond said low logic voltage.After step 240, said method is returned step 220.
Said linear voltage regulator provides the significant advantage that surmounts other regulators.Particularly, said linear voltage regulator provides the technique effect that uses a plurality of phase inverters to eliminate the voltage radio-frequency component.
Though reference example property embodiment has described the present invention, it will be understood by those skilled in the art that and to carry out various changes and can use equivalent elements to replace element wherein and do not depart from scope of the present invention.In addition, can carry out many modifications to instruction of the present invention and not depart from its scope to be fit to particular case.Therefore, the present invention is intended to be limited to be used to realize the embodiment that discloses of the present invention, but the present invention includes all embodiment that fall in the claim scope.In addition, any sequence of importance is not represented in the use of term " first ", " second " etc., and on the contrary, term " first ", " second " etc. are used to distinguish each element.

Claims (5)

1. linear voltage regulator comprises:
First circuit, it is configured to receive from first voltage of voltage source and eliminates the frequency content of said first voltage in the first frequency scope to obtain output voltage at main output node place; And
Second circuit; It has first and second phase inverters of the said main output node that is electrically coupled to said first circuit; Said second circuit is configured to receive said output voltage and eliminates the frequency content of said output voltage in the second frequency scope; Said second frequency scope be 10MHz to 6GHz, said first frequency scope is 0 to 10MHz;
Said first phase inverter has the first input end and first output terminal; Said first input end is electrically coupled to said first output terminal; Said first input end also is electrically coupled to capacitor; Said capacitor also is coupled to the ground on electric, and said first phase inverter also is electrically coupled to said main output node, makes second voltage on said first output terminal less than the said output voltage at said main output node place; And
Said second phase inverter has second input end and second output terminal, and said second input end is electrically coupled to said first output terminal of said first phase inverter, and said second phase inverter also is electrically coupled to said main output node; And said second circuit also comprises the P-channel field-effect transistor (PEFT) transistor with gate terminal, drain electrode end and source terminal; Said source terminal is electrically coupled to voltage source; Said drain electrode end is electrically coupled to said main output node; Said gate terminal is directly or indirectly communicated by letter with said second output terminal of said second phase inverter with electric means; Make when the said output voltage at said main output node place increases; Said second voltage on said first output terminal of said first phase inverter is less than the said output voltage on the said main output node, and this causes said second phase inverter on said second output terminal, to export high logic voltage, and said P-channel field-effect transistor (PEFT) transistor reduces said output voltage on the said main output node to respond said high logic voltage.
2. the linear voltage regulator described in claim 1; Wherein when the said output voltage at said main output node place reduces; Said second voltage on said first output terminal of said first phase inverter is greater than the said output voltage on the said main output node; This causes said second phase inverter on said second output terminal, to export low logic voltage, and said P-channel field-effect transistor (PEFT) transistor increases said output voltage on the said main output node to respond said low logic voltage.
3. the linear voltage regulator described in claim 1 also is included between said second output terminal and the transistorized said gate terminal of said P-channel field-effect transistor (PEFT) of said second phase inverter in series third and fourth phase inverter of electric coupling at least.
4. method of using the linear voltage regulator regulation voltage; Said linear voltage regulator comprises first circuit and second circuit; Said first circuit has main output node and said second circuit has first and second phase inverters that are electrically coupled to said main output node, and said method comprises:
Receive first voltage at the said first circuit place from voltage source;
Use the frequency content of said first voltage of said first circuit for eliminating in the first frequency scope to obtain output voltage at said main output node place; And
Use said first and second phase inverters of said second circuit to eliminate the frequency content of said output voltage in the second frequency scope, said second frequency scope be 10MHz to 6GHz, said first frequency scope is 0 to 10MHz;
Said second circuit further comprises the P-channel field-effect transistor (PEFT) transistor; Said first phase inverter has the first input end and first output terminal; Said first input end is electrically coupled to said first output terminal; Said first input end also is electrically coupled to capacitor, and said capacitor also is coupled to the ground on electric, and said first phase inverter also is electrically coupled to said main output node; Said second phase inverter has second input end and second output terminal; Said second input end is electrically coupled to said first output terminal of said first phase inverter, and said second phase inverter also is electrically coupled to said main output node, and said P-channel field-effect transistor (PEFT) transistor has gate terminal, drain electrode end and source terminal; Said source terminal is electrically coupled to said voltage source; Said drain electrode end is electrically coupled to said main output node, and said gate terminal is directly or indirectly communicated by letter with said second output terminal of said second phase inverter with electric means, and the step of wherein using said second circuit to eliminate the frequency content of said output voltage in the second frequency scope comprises:
When the said output voltage at said main output node place increased, output was less than second voltage of the said output voltage on the said main output node on said first output terminal of said first phase inverter;
On said second output terminal output from the high logic voltage of said second phase inverter to respond said second voltage less than said output voltage; And
Use said P-channel field-effect transistor (PEFT) transistor to reduce said output voltage on the said main output node to respond said high logic voltage.
5. the method described in claim 4, the step of wherein using said second circuit to eliminate the frequency content of said output voltage in the second frequency scope further comprises:
When the said output voltage at said main output node place reduced, output was greater than second voltage of the said output voltage on the said main output node on said first output terminal of said first phase inverter;
On said second output terminal output from the low logic voltage of said second phase inverter to respond said second voltage greater than said output voltage; And
Use said P-channel field-effect transistor (PEFT) transistor to increase said output voltage on the said main output node to respond said low logic voltage.
CN200880103775.4A 2007-08-30 2008-08-12 Linear voltage regulator Active CN101784975B (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US11/847,461 2007-08-30
US11/847,416 2007-08-30
US11/847,416 US7847529B2 (en) 2007-08-30 2007-08-30 Dual loop linear voltage regulator with high frequency noise reduction
US11/847,461 US7855534B2 (en) 2007-08-30 2007-08-30 Method for regulating a voltage using a dual loop linear voltage regulator with high frequency noise reduction
PCT/EP2008/060565 WO2009027220A1 (en) 2007-08-30 2008-08-12 Linear voltage regulator

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CN101784975A CN101784975A (en) 2010-07-21
CN101784975B true CN101784975B (en) 2012-12-26

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Publication number Priority date Publication date Assignee Title
US4952863A (en) * 1989-12-20 1990-08-28 International Business Machines Corporation Voltage regulator with power boost system
JP2006053829A (en) * 2004-08-13 2006-02-23 Mitsunori Katsu Semiconductor integrated circuit incorporating voltage regulator
US7301320B2 (en) * 2005-01-21 2007-11-27 International Business Machines Corporation On-chip high frequency power supply noise sensor
TW200731046A (en) * 2006-02-14 2007-08-16 Richtek Techohnology Corp Linear voltage regulator and control method thereof
US7508177B2 (en) * 2007-06-08 2009-03-24 Freescale Semiconductor, Inc. Method and circuit for reducing regulator output noise
JP4642830B2 (en) * 2007-11-06 2011-03-02 株式会社リコー Power supply apparatus and power supply method thereof

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WO2009027220A1 (en) 2009-03-05
EP2183653A1 (en) 2010-05-12
KR20100053560A (en) 2010-05-20
JP2010537335A (en) 2010-12-02
JP5295240B2 (en) 2013-09-18
CN101784975A (en) 2010-07-21
EP2183653B1 (en) 2013-01-02

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