EP2124510A1 - Procédé de commande d'une lampe fluorescente et appareil de montage de lampes - Google Patents

Procédé de commande d'une lampe fluorescente et appareil de montage de lampes Download PDF

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Publication number
EP2124510A1
EP2124510A1 EP08009105A EP08009105A EP2124510A1 EP 2124510 A1 EP2124510 A1 EP 2124510A1 EP 08009105 A EP08009105 A EP 08009105A EP 08009105 A EP08009105 A EP 08009105A EP 2124510 A1 EP2124510 A1 EP 2124510A1
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EP
European Patent Office
Prior art keywords
signal
switch
current
resonant circuit
time
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Application number
EP08009105A
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German (de)
English (en)
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EP2124510B1 (fr
Inventor
Martin Feldtkeller
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Infineon Technologies Austria AG
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Infineon Technologies Austria AG
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Priority to EP08009105A priority Critical patent/EP2124510B1/fr
Priority to US12/467,008 priority patent/US8242702B2/en
Publication of EP2124510A1 publication Critical patent/EP2124510A1/fr
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B41/00—Circuit arrangements or apparatus for igniting or operating discharge lamps
    • H05B41/14—Circuit arrangements
    • H05B41/26—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc
    • H05B41/28—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters
    • H05B41/295—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters with semiconductor devices and specially adapted for lamps with preheating electrodes, e.g. for fluorescent lamps
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B41/00—Circuit arrangements or apparatus for igniting or operating discharge lamps
    • H05B41/14—Circuit arrangements
    • H05B41/26—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc
    • H05B41/28—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters
    • H05B41/282—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters with semiconductor devices
    • H05B41/2825—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters with semiconductor devices by means of a bridge converter in the final stage
    • H05B41/2828—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters with semiconductor devices by means of a bridge converter in the final stage using control circuits for the switching elements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B41/00—Circuit arrangements or apparatus for igniting or operating discharge lamps
    • H05B41/14—Circuit arrangements
    • H05B41/26—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc
    • H05B41/28—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters
    • H05B41/282—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters with semiconductor devices
    • H05B41/285—Arrangements for protecting lamps or circuits against abnormal operating conditions
    • H05B41/2851—Arrangements for protecting lamps or circuits against abnormal operating conditions for protecting the circuit against abnormal operating conditions
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B41/00—Circuit arrangements or apparatus for igniting or operating discharge lamps
    • H05B41/14—Circuit arrangements
    • H05B41/26—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc
    • H05B41/28—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters
    • H05B41/282—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters with semiconductor devices
    • H05B41/285—Arrangements for protecting lamps or circuits against abnormal operating conditions
    • H05B41/2851—Arrangements for protecting lamps or circuits against abnormal operating conditions for protecting the circuit against abnormal operating conditions
    • H05B41/2856—Arrangements for protecting lamps or circuits against abnormal operating conditions for protecting the circuit against abnormal operating conditions against internal abnormal circuit conditions

Definitions

  • the present invention relates to a method for controlling a fluorescent lamp, in particular for igniting the fluorescent lamp, and a lamp ballast.
  • Lamp ballasts for fluorescent lamps or gas discharge lamps typically have a half-bridge circuit and a series resonant circuit connected to the half-bridge circuit, which can be connected to the fluorescent lamp.
  • the half-bridge circuit serves to excite the series resonant circuit and for this purpose generates an AC voltage from a DC voltage applied across the half-bridge.
  • a start phase of a lamp ballast comprises a preheat phase and an ignition phase for igniting the lamp.
  • filaments of the lamp are heated by a frequency of the AC voltage, which is hereinafter referred to as the excitation frequency, is set so that it is above the resonance frequency of the series resonant circuit.
  • the excitation frequency is increasingly reduced in the direction of the resonant frequency of the resonant circuit, with the aim of increasing a voltage across the fluorescent lamp by an increase in resonance so that an ignition voltage of the lamp is reached and the lamp ignites.
  • the excitation frequency can then be further reduced.
  • the coil of the resonant circuit is often dimensioned so that it already works in the vicinity of its magnetic saturation when the lamp voltage is in the range of the ignition voltage.
  • the effective inductance of a coil is known to be reduced. If an excitation frequency is reached during the ignition process at which the coil starts to saturate, the resonant frequency of the series resonant circuit increases due to the decreasing inductance of the coil, and a distance between the current excitation frequency and the resonance frequency decreases. If the excitation frequency remains the same, the voltage continues to rise, the coil continues to saturate, and the resonance frequency continues to approach the instantaneous excitation frequency. This explained positive feedback effect can lead to instabilities in the setting of the ignition voltage.
  • a lamp ballast which has a half-bridge with two switches, which are alternately turned on and off.
  • a current through the half-bridge is determined in each case during the duty cycle of a first of the two switches, and this first switch is then disabled when the half-bridge current exceeds a predetermined threshold.
  • the object of the present invention is to provide a method for controlling a fluorescent lamp, which ensures reliable ignition of an intact fluorescent lamp and reliably limits a lamp voltage to high voltage values, and to provide a lamp ballast.
  • An example of a method of driving a fluorescent lamp connected to a series resonant circuit having resonant circuit inductance and resonant circuit capacitance comprises applying an excitation AC voltage having an excitation frequency to the series resonant circuit using a half-bridge circuit having an output to which the series resonant circuit is coupled , and having a first and a second switch, which are controlled by a predetermined by a frequency signal fundamental frequency or at a lower frequency relative to the fundamental frequency conductive and blocking; Detecting a resonant circuit current flowing through the resonant circuit; and driving the switch with the fundamental frequency or with respect to the fundamental frequency lower frequency depending on a temporal change of the resonant circuit current between two temporally spaced evaluation times that are within a duty cycle of the switch.
  • An example of a lamp ballast comprises: a series resonant circuit with terminals for connecting a fluorescent lamp; a half-bridge circuit having a first and a second switch and having an output connected to the series resonant circuit; a drive circuit which assumes a first and a second operating state can and which is adapted to the first and second switch alternately conducting and blocking with a dependent of a frequency signal fundamental frequency or with a lower frequency compared to the fundamental frequency, and is adapted to detect a current through the resonant circuit and depending on a time change the resonant circuit current between two time-spaced evaluation, which are within a duty cycle of one of the switches to control the switch with the fundamental frequency or with respect to the fundamental frequency lower frequency.
  • FIG. 1 shows an example of a drive circuit for driving a fluorescent lamp LL.
  • This drive circuit which is also referred to as a lamp ballast, comprises a series resonant circuit with a resonant circuit inductance L1 and a resonant circuit capacitance C1 connected in series with the resonant circuit inductance L1.
  • a fluorescent lamp LL is coupled to the series resonant circuit via heating coils.
  • the fluorescent lamp LL can refer to FIG. 1 be switched parallel to the resonant circuit capacitance C1.
  • the resonant circuit capacitance C1 remote free ends of the heating coils can be connected in a manner not shown to a heating circuit.
  • the lamp ballast also has a half-bridge circuit with a first and a second switch T11, T12, each having a drive terminal and load paths.
  • the load paths of the switches T11, T12 are in this case in series between terminals for a positive Supply potential V and a negative supply potential or reference potential GND connected.
  • the half-bridge circuit has an output OUT, which is formed by a node common to the load paths of the switches T11, T12 and to which the series resonant circuit L1, C1 is coupled.
  • the series resonant circuit L1, C1 is in this case connected between the output OUT and the terminal for the second supply potential GND.
  • a coupling capacitor C2 is connected between the output OUT and the series resonant circuit L1, C1, which serves to block off DC components at an excitation alternating voltage Vout generated by the half-bridge circuit T11, T12 for the series resonant circuit L1, C1.
  • the half-bridge circuit T11, T12 serves for applying an excitation alternating voltage with an excitation frequency to the series resonant circuit.
  • the switches T11, T12 are actuated mutually conducting and blocking during operation by a drive circuit 1 to be explained.
  • conductively controlled first switch T11 which is also referred to as a high-side switch or upper half-bridge switch
  • blocking driven second switch T12 which is also referred to as a low-side switch or lower half-bridge switch
  • L1, C1 which corresponds to the supply voltage applied between the supply potential terminals.
  • the switches T11, T12 of the half-bridge circuit are in the in FIG. 1 illustrated lamp ballast formed as n-type MOSFET, each having a gate terminal as a control terminal and drain and source terminals as load line connections.
  • any switch can be used as a switch of the half-bridge circuit, in particular other semiconductor switches such as p-type MOSFET or IGBT.
  • complementary semiconductor switches for example to realize the high-side switch T11 as a p-MOSFET and the low-side switch T12 as an n-MOSFET.
  • the switches T11, T12 are activated such that a wait time, the so-called dead time, is awaited between the blocking activation of one switch and the conductive activation of the other switch.
  • a freewheeling current of the series resonant circuit can be taken during this dead time by a parallel to the low-side switch switched freewheeling element, such as a diode D.
  • a body diode integrated in the MOSFET can fulfill this freewheeling function, so that an external freewheeling element can be dispensed with.
  • a drive circuit 1 For driving the switches T11, T12 of the half-bridge circuit, a drive circuit 1 is provided which generates a first drive signal S11 for driving the high-side switch T11 and a second drive signal S12 for driving the low-side switch T12.
  • the drive terminals of the switches T11, T12 are preceded by driver circuits DRV11, DRV12, which serve to convert signal levels of the drive signals S11, S12 to those signal levels which are suitable for driving the switches T11, T12.
  • the drive circuit 1 is a frequency signal FS supplied, which determines the frequency at which the switches T11, T12 are mutually driven, and thus determines the excitation frequency of the series resonant circuit L1, C1.
  • This frequency signal FS is generated in a manner not shown, for example by a central control circuit which controls the operation of the lamp ballast.
  • Time profiles of the first and second drive signals S11, S12 generated by the drive circuit 1 are exemplified in FIG. 2 shown. Without limiting the invention to this, it is assumed for the following explanation that these drive signals S11, S12 are bivalent signals alternately assuming a turn-on level and a turn-off level, and that the switches T11, T12 conduct and at a turn-on level of the respective drive signal S11, S12 disable a turn-off of the respective drive signal. For purposes of the following explanation, assume that the turn-on level is a high level and the turn-off level is a low level of the respective drive signal S11, S12.
  • the in FIG. 2 Tp is designated, followed by a conductive driving of the first switch T11 for a first duty T1 and a conductive driving of the second switch T12 for a second duty T2.
  • Td1 denotes in FIG. 2 a first dead time after a duty cycle of the first switch T11 and before a duty cycle of the second switch T12.
  • Td2 denotes a second dead time after a turn-on time of the second switch T12 and before a turn-on time of the first switch T11.
  • the drive signals S11, S12 in FIG. 2 shown as rectangular signals with infinitely steep signal edges. In fact, these signals of course have switching edges with a finite slope.
  • the dead times Td1, Td2 ensure that the two switches T11, T12 do not conduct simultaneously, so that cross currents are safely avoided.
  • the time profile of a current I1 is represented by the series connection or a current measurement signal which is generated by a measuring arrangement M connected in the series resonant circuit.
  • This current measurement signal Vs1 in this case is at least approximately proportional to the resonant circuit current I1.
  • FIG. 2 shows the time course of this current I1 for a period before igniting the fluorescent lamp LL.
  • the current I1 through the series resonant circuit here runs at least approximately sinusoidally, the frequency of this sinusoidal signal waveform corresponds to the excitation frequency f.
  • the excitation frequency is controlled by the frequency signal FS, starting from an initial value which is above a resonant frequency of the resonant circuit L1, C1, gradually reduced.
  • This is synonymous with an extension of the period Tp and thus with an extension of the first and second turn-on T1, T2.
  • the dead times Td1, Td2 can in this case be independent of the turn-on durations T1, T2 and can have a predetermined constant value. However, the dead times can also be variable.
  • a reduction in the excitation frequency of the alternating voltage in the direction of the resonant frequency that excites the resonant circuit L1, C1 causes an increase in a maximum amplitude value of the current I1 flowing through the series resonant circuit or an AC voltage Vc1 applied across the resonant circuit capacitor C1.
  • the time course of this voltage Vc1 follows phase-shifted the time course of the current I1. If this voltage reaches the value of the ignition voltage of the fluorescent lamp LL when the excitation frequency drops and ignites the fluorescent lamp, then the excitation frequency can continue via the control circuit 1 up to the value of an operating frequency be lowered.
  • the energy consumed by the fluorescent lamp is re-supplied via the excitation voltage; the current profile is no longer sinusoidal in a manner not shown in the case of the ignited fluorescent lamp.
  • the lowering of the frequency to the operating frequency after ignition of the fluorescent lamp can be carried out by means of conventionally known measures, so that it is possible to dispense with further explanations on this.
  • the resonant circuit inductance L1 In order to keep the material costs for the resonant circuit inductance L1 as low as possible, it is desirable to select the resonant circuit inductance L1 so that it is operated in the region of its magnetic saturation when the resonant circuit current I1 rises to a value at which the lamp ignites. In this case, the feedback effect explained above can occur.
  • the first switch T11 is switched off immediately and before the "normal" switch-on duration dependent on the excitation frequency is reached.
  • the measuring signal Vs1 reaches the value of the lower threshold value Vr2 when the second switch T12 is activated, the second switch is switched off immediately and before the duty cycle dependent on the excitation frequency is reached. This leads to shortening the turn-on durations of the first and second switches T11, T12 in relation to the turn-on durations which are dependent on the instantaneous excitation frequency.
  • a dead time Td1 'or Td2' is waited before switching on the other switch, these dead times may be the same and in particular may correspond to the dead times Td1, Td2 during such operating phases in which no premature saturation caused Shutdown takes place.
  • a premature saturation-related switching off of the switches effectively leads to an increase in the excitation frequency and thus counteracts a further resonance peaking and thus a further increase in the voltage in the oscillatory circuit L1, C1. In particular, this avoids the positive feedback effect explained above.
  • FIG. 3 shows a detail of a lamp ballast, in which for providing the measurement signal Vs1 a measuring resistor Rs1 with at least approximately ohmic resistance behavior in series with the series resonant circuit L1, C1 and in the example between the series resonant circuit L1, C1 and the second supply potential GND is connected. A voltage across this measuring resistor Rs1 corresponds to the current measuring signal Vs1.
  • FIG. 4 shows a modification of the in FIG. 3 shown lamp ballast, in which the measuring resistor Rs1 is also connected between the series resonant circuit L1, C1 and the terminal for the second supply potential GND, but in which the fluorescent lamp LL is connected in parallel to a series circuit with the resonant circuit capacitance C1 and the measuring resistor Rs1.
  • FIG. 5 shows a block diagram of an example of such a lamp ballast.
  • lamp ballast comprises a half-bridge with a first and a second switch T11, T12 and connected to an output OUT of the half-bridge T11, T12 series resonant circuit L1, C1, to which a fluorescent lamp LL can be connected during operation of the lamp ballast.
  • a drive circuit 1 is provided to provide drive signals S11, S12 for the switches T11, T12 of the half-bridge.
  • this drive circuit has an oscillator 6 for providing an oscillator signal S6. This oscillator signal specifies with which frequency the two switches T11, T12 of the half-bridge circuit are to be activated.
  • This oscillator signal S6 is supplied to a drive signal generating circuit 5 which supplies the drive signals S11, S12 Dependent on this oscillator signal S6 generated such that the two switches T11, T12 are alternately driven alternately in the cycle of the oscillator signal S6 and that in each case a dead time between a conductive control of a switch and the conductive control of the other switch is present.
  • Each of the drive signals S11, S12 is thereby provided by the drive signal generating circuit, that the respective switch T11, T12, to which the drive signal is supplied, is clocked at a switching frequency, which is dependent on the frequency of the oscillator signal S6.
  • the frequency with which the two switches are driven in a phase-shifted manner to one another may correspond to the frequency of the oscillator signal, but may also be a fraction, such as half, or a multiple of the frequency of the oscillator signal S6.
  • the oscillator 6 can assume two different operating states: a first operating state, which is referred to below as a normal operating state; and a second operating condition, hereinafter referred to as a saturation operation condition.
  • a first operating state which is referred to below as a normal operating state
  • a second operating condition hereinafter referred to as a saturation operation condition.
  • the oscillator 6 In the normal operating state, the oscillator 6 generates the oscillator signal S6 at a predetermined frequency. This frequency is predetermined for example by the frequency signal FS or dependent on the frequency signal and is referred to below as the fundamental frequency. This fundamental frequency can change in basically already explained manner during an ignition process.
  • the saturation operating state the oscillator 6 generates the oscillator signal S6 at a frequency which is higher than the fundamental frequency, thereby counteracting the described positive feedback effect at an incipient saturation of the resonant circuit inductance L1.
  • the operating state of the oscillator 6 is dependent on a duty control signal S7, which is generated by a duty control circuit 9.
  • a duty control signal S7 evaluates the duty control circuit 9 a measurement signal Vs2, which of the resonant circuit current (I1 in FIG. 1 ) is dependent and in particular is proportional to this resonant circuit current.
  • the switch-on duration control circuit 7 is designed to control the switch-on duration control signal S7 as a function of the phase position of the measurement signal Vs2 with respect to the phase of the clock signal S6 or the phase of one of the two drive signals S11, S12 and depending on the time profile of the measurement signal Vs2 during a or several drive periods Tp.
  • a measuring resistor Rs2 is present in the illustrated example, which is connected in series with the switches T11, T12 of the half-bridge and in the illustrated example between the second switch T12 and the lower supply potential or reference potential.
  • an upper supply potential of the drive circuit 1 and an upper supply potential of the half-bridge T11, T12 are different. While the upper supply potential of the half-bridge can assume values of up to a few 100 volts, the upper supply potential of the drive circuit 1 is, for example, in the range of a few volts.
  • the lower supply potential of the half-bridge can correspond to the lower supply potential of the drive circuit 1 and can be, for example, a reference potential, in particular ground.
  • the measurement of the resonant circuit current I1 takes place in the illustrated lamp ballast only during a portion of the drive period, namely when the second switch T12 is turned on or when a freewheeling diode integrated in the second switch T12 or an external freewheeling diode (not shown) conducts.
  • a time profile of a measuring voltage Vs2 applied across this measuring resistor Rs2 is shown in FIG FIG. 6 depending on the clock signal S6 and the resulting drive signals S11, S12 shown schematically.
  • This measurement signal Vs2 follows after blocking the first switch T11 to the blocking of the second switch T12 the current I1 through the resonant circuit and is otherwise zero.
  • the duty control circuit 9 could also evaluate a measurement signal Vs1 corresponding to the embodiments of FIGS Figures 2 and 3 is produced.
  • a measuring resistor it would also be possible to use any other current measuring arrangement which is suitable for generating a measuring signal Vs2 which is dependent on the resonant circuit current I1 and in particular on the resonant circuit current I1.
  • the current measurement could be carried out in particular according to the so-called "current-sense principle". In this case, the current flowing through a power transistor is evaluated directly.
  • the illustrated oscillator 6 generates a clock signal S6 which alternately assumes a first level, in the example a high level, and a second level, in the example a low level.
  • this oscillator 6 comprises a capacitive storage element 61 with a first terminal which is connected via a series circuit with a first current source 62 and a first switch 63 to an upper supply potential or positive supply potential and which via a series circuit with a second current source 64 and a second switch 65 is connected to a second supply potential or reference potential.
  • this upper supply potential may in particular be smaller than an upper supply potential of the half-bridge T11, T12.
  • a second terminal of the capacitive storage element 61 which is realized for example as a capacitor, is connected in the example to the second supply potential.
  • This capacitive storage element 61 is alternately charged via the first series circuit 62, 63 and the second series circuit 64, 65 discharged.
  • a voltage V61 applied across the capacitive storage element 61 in this case has a triangular waveform, which is shown by way of example in FIG FIG. 6 is shown.
  • the first switch 63 of the first series circuit is driven in this case via the non-inverting output of the flip-flop 68, and the second switch 65 of the second series circuit is driven via the inverting output of this flip-flop 68.
  • the switches 63, 65 are each turned on at a high level of the associated flip-flop output signal and blocking at a low level of the respective flip-flop output signal. Since a high level alternately applied to the outputs of the flip-flop 68, an alternating activation of the series circuits is ensured.
  • the clock signal S6 is at the in FIG. 6 represented oscillator at the inverting output of the flip-flop 68 and thus assumes its flip-flop 68 its first level (high level) and when set flip-flop its second level (low level).
  • This clock signal S6 is supplied to the drive signal generating circuit 5 which generates the first and second drive signals S11, s12 in response to this oscillator signal S6.
  • drive signal generating circuit 5 is adapted to the two switches phase-shifted to each other with the frequency of the oscillator signal S6 conductively control.
  • a conductive control of the two switches T11, T12 takes place in each case after the expiration of a by the Anêtsignalerzeugungssckar
  • the first switch T11 after the expiration of the dead time after resetting the flip-flop 68 is turned on
  • the second switch T12 is after expiration of the dead time after setting the flip-flop 68 is energized.
  • the two switches T11, T12 are activated in a blocking manner when a state change of the flip-flop occurs which is complementary to the state change in which a conductive activation has taken place, ie the first switch T11 is immediately blocked when the flip-flop 68 is set and the second one Switch T12 is immediately disabled upon reset of the flip-flop.
  • “Immediate” in this context means that no minimum delay time between the state change of the flip-flop 68 and the blocking of the respective switch T11, T12 is provided but that delays occur only due to unavoidable signal propagation delays and due to switching delays of the first switches T11, T12.
  • Setting and resetting of flip-flop 68 is dependent on a comparison of capacitor voltage V61 with upper and lower thresholds V67, V66.
  • the flip-flop 68 is reset in the circuit shown, when the capacitor voltage V61 rises when the first switch 63 is energized to the upper threshold value V67 and set when the capacitor voltage V61 decreases when the second switch 65 is energized to the lower threshold value V66.
  • the capacitor voltage V61 and the lower threshold V66 are for this purpose a first comparator 66 which has an output which is connected to the set input of the flip-flop 68.
  • the capacitor voltage V61 and the upper threshold value V67 are fed to a second comparator 67 whose output is fed to the reset input R of the flip-flop 68 via an OR gate 69, which will be explained later.
  • the operation of this oscillator arrangement 6 will be briefly explained below:
  • the flip-flop 68 If the flip-flop 68 is set, the first series circuit is activated, whereby the capacitor voltage V61 increases. When the rising capacitor voltage V61 reaches the upper threshold value V67, the flip-flop 68 is reset, whereby the first series circuit 62, 63 is deactivated and the second series circuit 64, 65 is activated. The capacitor 61 is then discharged, whereby the capacitor voltage V61 drops. When the capacitor voltage V61 reaches the lower threshold value V66, the flip-flop 68 is reset, thereby activating the upper series circuit 62, 63 and deactivating the lower series circuit 64, 65. As in FIG. 6 is shown, takes the clock signal S6 in the illustrated example with decreasing capacitor voltage V61 a high level and with increasing capacitor voltage to a low level.
  • the drive signal generation circuit 5 comprises a delay element 51, to which the clock signal S6 is fed, and which generates an output signal S51 which delays the clock signal S6 by a delay duration Td.
  • a time profile of this output signal S51 is in FIG. 8 depending on the clock signal S6.
  • the drive signal generating circuit 5 also has two logic gates 51, 53, to each of which the clock signal S6 and the delayed clock signal S51 are supplied, and which respectively generate one of the drive signals S11, S12.
  • the first drive signal S11 is available at the output of the first logic gate 52, which in the example is realized as an AND gate.
  • This drive signal S11 assumes a switch-on level - in the example a high level - during such periods, during which the clock signal S6 and the delayed clock signal S51 have a high level.
  • a time profile of this first drive signal S11 resulting from the clock signal S6 and the delayed clock signal S51 is also shown in FIG FIG. 6 shown.
  • the second drive signal S12 is available at the output of the second logic gate 53, which in the Example realized as a NOR gate.
  • This drive signal S12 assumes a switch-on level during such periods - in the example a high level - during which both the clock signal S6 and the delayed clock signal S51 assume a low level.
  • a dead time between a turn-on level of the first drive signal S11, i. a conductive drive of the first switch T11, and a turn-on level of the second drive signal S12, i. a conductive drive of the second switch T12, in the illustrated drive signal generating circuit 5 is determined by the delay time Td of the delay element 51.
  • the clock signal S6 and the delayed clock signal S51 have mutually complementary signal levels, so that both the first and the second drive signal S11, S12 assume a low level.
  • Dead times between the lock of the first switch T11 and the conduction of the second switch T12 and between the lock of the second switch T12 and the conduction of the first switch T11 are the same in this drive signal generating circuit 5.
  • the delay element 51 may have a fixed delay time, but may also be adjustable in terms of its delay time. In the latter case, the dead time can be adjusted via the delay element.
  • the duty control circuit 9 is configured to generate the duty control signal S7 upon detection of incipient saturation of the resonant circuit inductance so as to change from a first signal level which does not affect the operation of the oscillator 6 to a second signal level during a drive period , If the switch-on duration control signal assumes the second signal level, an instantaneous drive period is immediately terminated or the oscillator is reset before the drive period specified by the fundamental frequency expires.
  • the switch is at the second signal level upon a change of the duty control signal S7 is switched off immediately, the second switch T12.
  • the first signal level of the duty control signal S7 is a low level and the second signal level of the duty control signal S7 is a high level.
  • the duty control signal S7 is supplied to the other input of the OR gate 69 in the illustrated example, whose output is connected to the reset input of the flip-flop 68. If the switch-on duration control signal S7 assumes a high level during a drive period, the flip-flop 68 is reset, whereby the second switch T12 is immediately blocked via the inverting output of the flip-flop 68 and the NOR gate 53 of the drive signal generating circuit 5, ie even before the voltage V61 reaches the upper threshold, ie even before the end of the predetermined by the fundamental frequency drive period is reached.
  • Such a scenario is in the right part of the FIG. 6 represented for some drive periods.
  • the signal level of the duty control signal S7 at which the flip-flop 68 is reset, and thus the second switch T12 is turned off, is hereinafter also referred to as the turn-off level of the duty control signal S7.
  • the time course of the duty cycle control signal S7 is in FIG. 6 also shown.
  • the flip-flop 68 is reset even before the triangular voltage signal V61 reaches the upper threshold value V67 of the oscillator circuit 6, not only the duration of a low level of the clock signal S6, and thus the duration of a conductive activation of the second switch T12, but also a subsequent one Discharge duration of the capacitor until reaching the lower threshold V66, which is based on the time course of the voltage signal V61 in the right part of the FIG. 6 is immediately apparent; This shortens a subsequent period of a high level of the clock signal S6 and thus the duration of a conductive activation of the first switch T11.
  • the capacitor 61 of the oscillator circuit 6 fulfills the in FIG.
  • the two current sources 62, 64 can in particular be realized in such a way that they deliver equal currents, whereby a symmetrical clock signal, ie a clock signal with equal high levels and low levels, is achieved during normal operation.
  • the fundamental frequency of the clock signal S6 can be set, for example, via the two current sources 62, 64.
  • the current sources 62, 64 are in this case controlled current sources to which the frequency signal FS is supplied as a setting signal.
  • the fundamental frequency can also be set via the thresholds V66, V67. In this case, the threshold values V66, V67 and their difference, depending on the frequency signal FS.
  • the difference between the two threshold values V66, V67 determines the signal swing of the voltage V61 across the capacitive storage element 61. If this signal swing is reduced, for example, the frequency of the oscillator signal S6 increases.
  • the capacitor 61 is also used in the illustrated oscillator 6 for timing, namely for determining a time duration between a blocking drive of the first switch S11 and a beginning saturation of the resonant circuit inductance L2. This period of time is proportional to the difference between the capacitor voltage V61 at the time of a saturation-related shutdown and the lower threshold value V66. Assuming that the triangular signal is generated symmetrically, a discharge duration of the capacitor 61 from this value during saturation-related shutdown to the lower threshold value V66 corresponds precisely to the preceding rise time, whereby symmetrical activation of the half-bridge switches T11, T12 is achieved even with saturation-induced shutdown. d. H. a switch-on duration of the second switch T12 before a saturation-related switch-off corresponds at least approximately to a switch-on duration of the first switch T11 during the subsequent conductive activation of this first switch T11.
  • the basis of FIG. 6 explained circuit is merely an example.
  • the determination of the time duration between the blocking of the first switch T11 and a beginning saturation of the resonant circuit inductance L1 can be determined in any other way, stored and used for a subsequent conductive actuation of the first switch T11.
  • the capacitor could, for example, by an incrementable and decrementable counter, the signal generators could be realized by activatable clock generators for incrementing and decrementing this counter.
  • the drive signals S11, S12 For driving the first and second switches T11, T12, it is provided to generate the drive signals S11, S12 in such a way depending on the current profile of the current I1 of the series resonant circuit that one of the switches T11 or T12 has a maximum of a predetermined period of time Tmax remains on after a certain phase position of the resonant circuit current I1 is present during the on-time of this switch T11 or T12.
  • Such a specific phase position is achieved, for example, when the resonant circuit current has reached a predetermined current value.
  • This predetermined current value is zero, for example.
  • a shutdown level of the duty control signal S7 is generated after the expiration of the period Tmax after the presence of a certain phase position, for example, a zero crossing.
  • a current actuation period is thus terminated at the latest after expiration of this time period Tmax after the presence of the determined phase position. If this time duration Tmax ends only after the drive period predetermined by the fundamental frequency has ended, the switch-on duration control signal S7 has no influence on the oscillator frequency or on the activation of the two switches T11, T12. Such a scenario is in the left part of the FIG. 6 shown. For this representation, it is assumed by way of example that the time duration Tmax begins in each case with a zero crossing of the resonant circuit current. The time duration Tmax ends in each case only after the end of the drive period has already been reached, after the flip-flop 68 has thus already been reset.
  • FIG. 6 shows in the right part by way of example the time course of the measurement signal Vs2 or the resonant circuit current I1 during such a beginning saturation of the resonant circuit inductance L1.
  • the zero crossings of the resonant circuit current I1 are no longer in the middle of the drive pulses - in the example of the drive pulses of the second switch T12 - but are shifted in the direction of a start of this drive pulse.
  • the second switch T12 remains switched on after such zero crossings for a maximum of a predetermined duty cycle Tmax, it is ensured that very high resonant circuit currents be avoided at a beginning saturation of the resonant circuit inductor L1.
  • the duty cycle control 9 has a first detection circuit 91, which is designed to compare the current measurement signal Vs2 with a predetermined signal level.
  • a detection signal S91 is available, which is dependent on a comparison of the current measurement signal Vs2 with the predetermined signal level.
  • the first detection circuit has a comparator with an inverting and a noninverting input, to which the current measuring signal Vs2 is supplied as an input signal.
  • the detection signal S91 is directly dependent on the sign of the current measurement signal Vs2 in this detection circuit and has a first signal level at a positive sign of the current measurement signal Vs2 and a second signal level at a negative sign of the current measurement signal Vs2.
  • the detection signal S91 is in this case dependent on a comparison of the current measurement signal Vs2 with zero and contains immediately information about zero crossings of the current measurement signal Vs2 and the resonant circuit current I1.
  • the detection signal S91 will therefore also be referred to below as the zero-crossing signal and the first detection circuit 91 as the zero-crossing detector.
  • the comparator is connected such that the first signal level of the detection signal present at a negative current measurement signal Vs2 is a high level and the second signal level of the detection signal present at a positive current measurement signal Vs2 is a low level.
  • the current measurement signal Vs2 for generating the detection signal S91 can of course also be compared with any other, fixed predetermined signal level, to the phase position of the resonant circuit current I1 or the current measurement signal Vs2 to determine.
  • a reference signal (not shown) must be supplied with the predetermined (comparison) signal level.
  • the zero crossing signal S91 generated by the zero crossing detector 91 is supplied together with the current measurement signal Vs2 to an evaluation circuit 90, which is designed to generate the duty control signal S7 in such a manner dependent on the zero crossing signal S91 and the current measurement signal Vs2 that the duty control signal S7 after expiration of the time Tmax after a cut-off level is detected at a detected zero crossing of the current measuring signal S7.
  • the time duration Tmax is dependent on the resonant circuit current I1, wherein in the illustrated example the current measuring signal Vs2 is used as the measured variable for this resonant circuit current I1.
  • This evaluation circuit 90 comprises a timing arrangement 8 which generates a timing signal V8, a comparison value generating circuit 7 which generates a comparison value V7, and a comparator 95 which compares the timing signal V8 with the comparison value V7 and which generates the duty control signal S7 depending on the result of the comparison.
  • the timing arrangement 8 has a series connection with a current source 83 and a capacitive storage element 81, such as a capacitor, and a switching element 82 connected in parallel with the capacitive storage element 81.
  • the time measurement signal V8 corresponds to a voltage across the capacitive storage element 81 in this time measurement arrangement.
  • This time measurement arrangement 8 can be activated and deactivated via the switching element 82 connected in parallel with the capacitive storage element 81, which is controlled by the zero crossing detector 91.
  • the timing arrangement is activated in the illustrated example with the switching element 82 open and deactivated when the switching element 82 is closed.
  • the capacitive storage element 82 is discharged via the switching element 82, so that the time measurement signal V8 in the deactivated state is zero.
  • the zero-crossing detector 91 is in the basis of the Figures 5 and 7 explained example connected so that after a zero crossing of the measuring voltage Vs2, after which this measuring voltage assumes a reference to the reference potential GND positive value, the switching element 82 opens, and thus the timing assembly 8 is activated.
  • the voltage V8 across the capacitive storage element 81 increases depending on a current supplied by the current source 83.
  • the voltage V8 present across the capacitive storage element 81 in this case represents directly a measure of the time that has elapsed since activation, and therefore since the zero crossing.
  • FIG. 9 illustrated evaluation circuit 90 is a time course of the voltage V8 across the capacitive storage element 81 of the timing device 8 in FIG. 6 shown.
  • the voltage V8 across the capacitive storage element 81 rises after a zero crossing of the current measurement signal Vs2.
  • V7 the comparison value V7
  • the second switch T12 is switched off and the timing device 8 is deactivated.
  • a state of charge of the capacitor 61 of the oscillator 6 when resetting the flip-flop 68 is a measure of the switch-on duration of the lower switch T12.
  • This state of charge determines the subsequent switch-on duration of the first switch T11, wherein for the same sized current sources 62, 64 of the oscillator 6, this duty cycle of the first switch T11 of the previous duty cycle of the second switch T12 corresponds.
  • a symmetrical control of the switches T11, T12 of the half-bridge is ensured, although the resonant circuit current I1 is evaluated only during a partial period of the drive period Tp of the half-bridge.
  • an evaluation of the resonant circuit current takes place during such a partial period, during which the resonant circuit current I1 flows through the branch of the half-bridge with the second switching element T12.
  • the current can of course also be evaluated during such subperiods, during which the resonant circuit current I1 flows through the branch of the half-bridge with the first switching element T11. An evaluation of the current during the entire driving period is possible.
  • the timing device 8 can be activated in a manner not shown at each zero crossing of the current measurement signal Vs2 and the oscillator 6 can be realized in a manner not shown so that the flip-flop 68 changes state each time the comparison value V7 is reached by the timing signal V8.
  • the described characteristic of the oscillator 6 that the time duration from switching off the first switch T11 to the saturation-related switching off of the second switch T12 is equal to the subsequent time until the next switch-off of the first switch is not required in this case.
  • the voltage V8 across the capacitive storage element 81 increases linearly over time. This can be achieved by making the current supplied by the current source 83 constant. However, the current source 83 can also be realized so that it provides a time-varying current. In this case, there is no linear relationship between the timing signal V8 and the time since the zero crossing more; However, the timing signal V8 is still dependent on this period.
  • the charging current I83 delivered by the current source 83 is in this case dependent on the frequency signal FS.
  • the rise time of the timing signal V8 until it reaches a certain reference value V7 or the transconductance of the timing signal V8 over time is in a fixed relationship to the drive period in the normal operating state of the oscillator.
  • the required for a Zündschreibsregelung Signal range / range of variation of the comparison value V7 is thus independent of the resonant frequency of the connected resonant circuit, because the rise time of the timing signal V8 is virtually normalized to the resonant frequency.
  • the comparison signal V7 is in FIG. 6 represented as a constant signal.
  • this comparison signal V7 is variable in time and dependent on the time course of the resonant circuit current I1. It is used in the explained lamp ballast to advantage that the rate of rise of the current measurement signal Vs2 after the zero crossing is dependent on the oscillation amplitude, ie the amplitude of the applied voltage across the lamp. This slew rate increases sharply when the excitation frequency of the resonant circuit moves in the direction of the resonance frequency of the resonant circuit, so when the oscillation amplitude increases so much.
  • the comparison value generation circuit 7 is designed to evaluate the current measurement signal Vs2 at two different times during a subperiod and to determine the comparison signal V7 as a function of the evaluation results obtained thereby.
  • a "subperiod” is generally understood to mean a time segment of the drive period Tp during which the current flows through one of the two half-bridge branches.
  • FIG. 10 Illustrated for a better understanding FIG. 10 the time course of the current measuring signal Vs2 during such a period. Is shown in FIG.
  • the evaluation of the current measuring signal Vs2 takes place in such a way that a temporal change of the current measuring signal Vs2 from a first evaluation time t1 to a second evaluation time t2 is determined.
  • a change over time of the current measurement signal Vs2 from the first evaluation time t1 to a second evaluation time t2 here is to be understood as a change in the amplitude of the current measurement signal Vs2 relative to the time duration between the first and second evaluation time.
  • V1 denotes the amplitude value of the current measurement signal Vs2 at the first evaluation time t1
  • V2 denotes the amplitude value of the current measurement signal Vs2 at the second evaluation time t2.
  • ⁇ t denotes the time interval between the evaluation times t1, t2.
  • comparison value signal V7 it is also provided to compare the change value ⁇ Vs2 / ⁇ t determined during each partial period with a reference value and to generate the comparison signal V7 such that it depends on a difference between the change value ⁇ Vs2 / ⁇ t and the reference value.
  • An example of a comparison value generation circuit 7 having such a functionality is shown in FIG FIG. 12 shown.
  • This comparison value generating circuit 7 has a sampling circuit 71 to which the current measurement signal Vs2 is applied and which generates a variation value ⁇ Vs2 / ⁇ t.
  • This change value .DELTA.Vs2 / .DELTA.t is supplied to a controller 72 together with a reference value Vref.
  • the controller 72 is a proportional-integral controller that obtains a difference between the variation value ⁇ Vs2 / ⁇ t and the reference value Vref and that generates the comparison signal V7 to have both a proportional component and an integral component.
  • the proportional component is dependent on a momentary difference between the current change value ⁇ Vs2 / ⁇ t and the reference value Vref.
  • the integral component is dependent on differences between change values and the reference value which have been determined for a number of past activation periods.
  • the time interval of the sampling times t1, t2 is set to be smaller than the time period between the zero crossing and the timing of generation of the cut-off level of the duty control signal S7.
  • This time is in FIG. 10 denoted by t7.
  • t0 denotes in FIG. 10 the time of a zero crossing of the voltage measurement signal Vs2.
  • the time interval between the sampling times t1, t2 may in particular be selected such that it is equal to or less than half of the time interval between the zero crossing t0 and the time t7.
  • the sampling times t1, t2 can both be after the zero crossing t0, wherein the first sampling time t1 can also coincide with the time t0 of the zero crossing.
  • the first sampling time t1 could also be before the zero crossing.
  • the first sampling time t1 may be set above the time t0 of the zero crossing and may be selected to always be at a fixed time interval, including zero, at the zero crossing time.
  • the first sampling time t1 can also be determined by a comparison of the current measurement signal Vs2 with a comparison value. In this case, this first sampling time t1 is present when the current measurement signal Vs2 reaches this comparison value.
  • the temporal position of the second sampling time t2 is predetermined in both cases by the temporal position of the first sampling time t1 and the desired time interval ⁇ t between the sampling times t1, t2.
  • the sampling times are sufficiently close to the zero-crossing instant that it is ensured that there is no saturation of the resonant circuit inductance at the evaluation times, that the resonant circuit current present at the evaluation times is still smaller than a current at which saturation of the resonant circuit inductance starts. In this way, it is ensured that an evaluation of the resonant circuit current for determining the oscillation amplitude takes place at a time when there is still no saturation-related distortion of the current profile.
  • FIG. 11 is provided in a further example for determining the change value .DELTA.Vs2 / .DELTA.t to specify first and second threshold values V1, V2 and to determine a time interval .DELTA.t or .DELTA.t 'between two times at which the current measurement signal Vs2 respectively reaches these thresholds.
  • t1 and t2 denote first and second sampling instants at which the current sense signal Vs2 reaches the thresholds V1, V2 when the steep waveform shown by the solid line is present
  • t1 ', t2' denotes the sampling instants at which these thresholds V1, V2 be achieved when the flatter waveform is present.
  • the reciprocal of the time difference ⁇ t, ⁇ t 'taking into account the difference between the threshold values V1, V2 directly represents a measure of the change value ⁇ Vs2 / ⁇ t.
  • the first and second threshold values V1, V2 can both be positive.
  • the first threshold V1 may also be negative and the second threshold V2 positive.
  • the generation of the change value .DELTA.Vs2 / .DELTA.t and the generation of the comparison signal V7 are coordinated so that the comparison value V7 becomes smaller, the larger the change value .DELTA.Vs2 / .DELTA.t compared to the reference value Vref.
  • a large change value ⁇ Vs2 / ⁇ t indicates a steep signal curve of the current measurement signal Vs2; In this case, the maximum time duration Tmax, during which the second switch T12 still remains switched on after the zero crossing of the current measuring signal Vs2, should be reduced in order to reliably prevent the achievement of very high current values of the resonant circuit current I1.
  • the current measurement signal Vs2 provides for an offset of the time measurement signal V8, which is greater the greater the amplitude of the current measurement signal Vs2.
  • a steep rise of the current measuring signal Vs2 and the associated high amplitudes of the current measuring signal thus have an immediate effect on a shortening of the time duration Tmax between a zero crossing of the current measuring signal Vs2 and the switching off of the second switch T12.
  • FIG. 14 A circuit implementation example of a controlled current source 83 with the basis of FIG. 13 explained functionality, is in FIG. 14 shown.
  • This controlled current source 83 has a first current source 831 and a second current source 832.
  • the first current source 831 determines the "base current" of the controlled current source 83, which flows independently of the current measurement signal Vs2.
  • This first current source 832 may be a current source controlled by the frequency signal FS, in which case the base current is dependent on the frequency signal FS.
  • the controlled current source 83 has a current mirror arrangement with two current mirrors each having an input transistor and an output transistor.
  • These current mirrors are connected in such a way that they map a "ground current" I 831 provided by the first current source 831 to the charging current I 83 provided by the controlled current source 83.
  • the first current source 831 is connected in series with an input transistor 835 of the first current mirror 835, 836.
  • the charging current I83 is provided by an output transistor 837 of the second current mirror 837, 838.
  • An output transistor 836 of the first current mirror is connected in series with an input transistor 838 of the second current mirror.
  • the controlled current source 83 also has a comparator 833, 834, which compares the current measurement signal Vs2 with the threshold value Vth, and depending on this comparison result supplies the base current I831 supplied by the first current source 831 with a comparison-dependent part of that supplied by the second current source 832 Add current I832.
  • This comparator has two transistors 833, 834, of which a first 833 is driven by the current measurement signal Vs2 and of which a second 834 is driven by a voltage source 839 providing the threshold value Vth.
  • the load path of the first transistor 833 is in this case connected between the second current source 832 and a reference potential, while the load path of the second transistor 834 between the second current source 832 and the two transistors 835, 836 of the first current mirror common node is connected.
  • the two transistors 833, 834 of the comparator circuit are realized in the illustrated example as p-channel transistors. If the current measurement signal Vs2 is smaller than the threshold value Vth, the first transistor 833 of the comparator circuit conducts more than the second transistor 834, so that a substantial part of the second current I832 flows out via the first transistor 833. If the current measurement signal Vs2 exceeds the threshold value Vth, then a substantial part of the current I832 flows via the second transistor 834 and is thus fed into the first current mirror and thus contributes to an increase of the charging current I83.
  • a simple and inexpensive to implement comparative value generating circuit 7, which generates the comparison value V7 in the manner explained depending on the change value is in FIG. 15 shown.
  • the operation of this comparison value generation circuit 7 will be explained with reference to FIG FIG. 16 Exemplary illustrated time profiles of the current measurement signal Vs2 and the comparison value V7.
  • the comparison value generating circuit 7 has the already explained regulator 72 with an inverting input and a non-inverting input as well as an output at which comparison value V7 is available.
  • this regulator 72 has a control amplifier 721 and two capacitors 722, 723 which are connected in parallel between the inverting input and the output of the control amplifier 721. In series with a 723 of the two capacitors 722, 723, a switch 724 is connected. Between the non-inverting input of the control amplifier 721 and a reference potential GND, a voltage source 80 is connected, which provides a constant voltage and which serves to adjust the operating point of the controller 72.
  • the variable gain amplifier 721 is an operational amplifier is formed and is in this case connected to the capacitor 722 as an integrator, which integrates the charge available at its inverting input.
  • the comparison value generation circuit 7 also has a first capacitance 74 and a second capacitance 75, each having first and second terminals, and having their second terminals connected to a common circuit node.
  • This common circuit node is connected via a first switch 78 to the non-inverting input and via a second switch 79 to the inverting input of the regulator 72.
  • the first terminal of the first capacitor 74 can be connected via two further switches: a third switch 76 and a fourth switch 77 optionally to the reference voltage source 73 or reference potential GND providing the reference signal Vref.
  • the first terminal of the second capacitor 75, the current measurement signal Vs2 is supplied.
  • the comparison value generation circuit 7 has three different operating states designated A, B, and C.
  • the individual switches of the comparison value generating circuit 7 are turned on or off during these operating states.
  • FIG. 15 specified in addition to the respective switches the operating conditions during which the individual switches are controlled conductive.
  • a first operating state or a first operating phase A extends to the first evaluation time t1, which coincides, for example, with the zero-crossing time point.
  • the first switch 78 and the third switch 76 which connects the first capacitor 74 to the reference voltage source 73, are closed.
  • the first capacitor 74 is thereby charged to a voltage corresponding to the reference voltage Vref minus the operating point voltage V80 supplied by the voltage source 80.
  • the Second capacitor 75 is applied during this phase of operation, a voltage corresponding to the current measurement signal Vs2 minus the operating point voltage V80.
  • the second operating state or the second operating phase B begins with the first evaluation time t1 and ends with the second evaluation time t2.
  • the first switch 78 is opened and the second switch 79 is closed.
  • the third switch 76 connecting the first capacitance 74 to the reference voltage source 73 is opened, and the fourth switch 77 connecting the first capacitance 74 to the reference potential GND is closed.
  • the first evaluation time corresponds for example to the zero-crossing time, which is assumed for the following explanation.
  • the integrator 721, 722 integrates all charges which are fed to its inverting input. Shortly before the first sampling time t1, ie shortly before closing the second switch 79, the voltage across the second switch 79 is zero. This is due to the fact that the first switch 78 closed during the first operating phase forces the potential of the common node of the first and second capacitances 74 and 75 to the value of the operating point voltage V80 and that the differential input voltage of the closed-loop control amplifier 721 implemented as an operational amplifier Is zero.
  • the first switch 78 is opened at the first sampling time t1 and the second switch 79 is closed, no charge flows to or from this inverting input by this process alone.
  • the third switch 76 is opened and the fourth switch 77 is closed.
  • the potential at the common node of the first capacitance 74, and the first and second switches 76, 77 changes by a voltage corresponding to the reference voltage Vref.
  • the operational amplifier 721 restores the voltage balance at its inputs due to the closed loop, the potential at the node common to the first capacitor 74 and the second switch 79 is before the beginning of the second phase of operation, ie before the first sample time t1, and after a settling time has elapsed of the operational amplifier 721 after the beginning of the second phase of operation.
  • the electric charge stored in the first capacitance 74 thereby changes by a value which corresponds to the product of the capacitance value of this first capacitance and the reference voltage Vref.
  • This amount of charge flows in the course of the transient from the inverting input of the operational amplifier 721 and thus from the integrator input.
  • the voltage at the output of the integrator changes by a voltage difference which corresponds to the quotient of the amount of charge flowed off and the capacitance value of the capacitor 722 of the controller 7. This change is in accordance with the time course FIG. 16 as the increase of the comparison value V7 immediately after the first sampling time t1.
  • the current measurement signal Vs2 slowly increases further.
  • One terminal of the second capacitance 75 is fixed to the value of the current measuring signal Vs2, while the other terminal is connected via the second closed switch 79 to the integrator input, ie the non-inverting input of the control amplifier 721, and is at a constant potential, that of the operating point voltage V80 corresponds.
  • a change in the voltage across the second capacitance 75 corresponds in the further course of a temporal change of the current measurement signal Vs2.
  • a total of a charge flows to the integrator input, which corresponds to the voltage change of the current measurement signal Vs2 multiplied by a capacitance value C75 of the second capacitance 75 from time t1.
  • the second switch 79 is opened again and the first switch 78 is closed. From this point on, therefore, no further charge can flow from the second capacitor 75 to the integrator input or flow away from it, the integrator state is virtually frozen.
  • the voltage change at the integrator output from a time after the first sampling time t1 at which the operational amplifier 721 has settled to the second sampling time t2 corresponds to the voltage change of the current measuring signal Vs2 within that time negatively multiplied by the capacitance ratio C75 / C722 of the capacitance values C75 and C722 of the second capacitance 75 or the capacity 722 of the integrator.
  • Vref ⁇ C ⁇ 74 C ⁇ 75 the comparison value V7 with respect to the sampling times t1, t2 does not change.
  • the value given by Vref ⁇ C74 / C75 in this case represents a reference value, with which the change ⁇ V of the current measurement signal Vs2 for generating the comparison signal V7 is compared. If the change ⁇ V of the current measurement signal Vs2 is smaller than this reference value, then the comparison signal V7 increases in relation to the sampling instants; the time course for this case is in FIG. 16 shown as a dashed line. Accordingly, the comparison signal V7 becomes smaller with respect to the sampling timings when the change ⁇ V of the current measurement signal Vs2 is larger than this reference value; the time course for this case is in FIG. 17 shown as a solid line.
  • the comparison signal V7 available at the output of the integrator remains frozen after the end of the second operating phase during the third operating phase C until the switch-off time t7 and is used to generate the duty control signal S7 in accordance with the preceding explanations.
  • the third phase of operation may end at time t7 or later.
  • This third operating phase is followed by a new first operating phase A.
  • the operational phase transition from the third to the first phase is not relevant; it should be done during the off period of switch T12.
  • the operating phase A of the capacity 722 of the integrator another capacitor 723 is connected in parallel.
  • the capacitance value of this capacitance 723 is, for example, about 3 to 10 times the capacitance value of the capacitor 722.
  • This capacitance 723 is charged during the first operating phase A to a voltage value which is the difference between the comparison signal V7 at the output of the integrator and the operating point voltage V80 equivalent.
  • a voltage equal to the difference between corresponds to the "new" comparison signal V7 and the operating point voltage V80.
  • the voltages across both capacitances equalize to a value corresponding to an average of the voltage during the preceding phase of operation A and the immediately preceding phase of operation C, weighted by the capacity ratio of the capacitances 722 and 723.
  • the deviations of the temporal change ⁇ V of the current measuring signal from the reference value Vref * C74 / C75 are summed for all preceding cycles in the form of the charge of the capacitance 723.
  • the charge stored in this capacitance 723 thus represents the integral component (I component) of the signal present at the output of the regulator.
  • the pure I component can be tapped off during the operating phases A at the integrator output V7.
  • the capacitance 722 Because the charge of the capacitance 722 is reset to the I component during each phase of operation A, however, it additionally experiences a charge change proportional to the deviation of the time ⁇ V from the reference value Vref * C74 / C75 of the respective cycle of operation the capacitance 722 during the operating phase C is a charge which differs from the I-component by a proportional component (P-component).
  • the ratio of the I component and the P component can be selected by the capacity ratio of the capacitors 722 and 723.
  • the sum of I component and P component of the controller output voltage can be tapped off as comparison signal V7 during the third operating phases C.
  • the capacitance ratio of the capacitances is, in simple terms, a measure of how often the capacitor 722 must be charged to a different voltage from the capacitance 723 during the operating phase B and then discharged into the capacitance 723 during the operating phase A until the voltage across the capacitance 723 changes as much as the voltage of the capacitance 722 changes during each phase of operation B.
  • the comparison signal may be subject to considerable fluctuations, in particular during the second operating phase.
  • the comparison signal V7 is used to generate the duty control signal S7, however, the comparison signal V7 is subject to no fluctuations and has during this phase in particular the above-described desired dependence on the time change .DELTA.V of the current measurement signal Vs2 between the evaluation times t1, t2 ,
  • the control of the individual switches is performed by a flow control, not shown.
  • This sequence control is supplied, for example, information about the time of the zero crossing.
  • the sequencer also receives information about the turn-off time at which the second switch T12 is turned off, and is configured, for example, to the end of the third phase of operation - and thus the beginning of the subsequent first phase of operation - to be selected so that it is for a predetermined period of time the shutdown time is.
  • a lowering of the comparison voltage V7 causes a shortening of the maximum duty cycle, which can lead to an increase of the excitation frequency, in particular when the resonant circuit inductance is operated in the region of saturation, because the duty cycle of the lower switch T12 is shortened from the zero crossing , As a result, the oscillation amplitude of Vs2 decreases.
  • an increase in the comparison voltage V7 causes an extension of the maximum duty cycle Tmax, which can lead to a reduction of the excitation frequency and thus to an increase in the oscillation amplitude, as long as the oscillator is in saturation mode.
  • the excitation frequency and the oscillation amplitude are independent of the comparison voltage V7, since the end of the switch-on period of the second switch is already reached in this case, even before the oscillator is reset by the switch-on duration control signal S7.
  • the comparison signal V7 affects the switching frequency of the half-bridge only when the timing signal V8 reaches the value of the comparison signal V7 before the end of the duty of the second switch T12 predetermined by the fundamental frequency of the oscillator 6 is reached.
  • the comparison signal V7 is already provided during the time period during which the Frequency signal FS is lowered to ignite the lamp, so to produce that the predetermined by the duty control 9 duty cycle coincides approximately with the predetermined by the fundamental frequency of the oscillator 6 duty cycle.
  • comparison value signal V7 This is equivalent to generating the comparison signal V7 so that the timing signal V8 reaches this comparison signal V7 at the same time as the voltage across the capacitor 61 of the oscillator 6 reaches the upper comparison value V67.
  • the comparison value signal V7 initially has no influence on the drive frequency. However, as the resonant circuit inductance begins to saturate and the resonant circuit current rapidly increases, the comparison value V7 can be rapidly lowered further from the "settled value" which has previously set, thereby more effectively reducing the on-times of the two switches of the half-bridge to limit and thus raise the An Tavernfrequenz first again.
  • the frequency signal FS is generated by a central control circuit not shown in detail so that the frequency signal FS slowly approaches the resonant frequency.
  • such an approximation to the resonant frequency is effected by a stepwise (step-shaped) lowering of the frequency signal FS.
  • the maximum duty cycle Tmax determined by the duty cycle control circuit 9 from the current zero crossing is initially longer than the switch-on duration set by the oscillator 6, the excitation frequency thereby being dependent on the frequency signal FS and not on the comparison signal V7 during this operating phase.
  • the frequency f 1 / Tp decreases due to the lowering of the frequency signal FS. This frequency 1 / Tp is for example in the range of a few 10 kHz.
  • the amplitude of the current measuring signal Vs2 initially increases relatively slowly during the lowering of the frequency f.
  • the comparison signal V7 can be tracked during this phase so that the oscillator 6 is operated in the normal operating state, but at the limit to the saturation operating state.
  • the comparison signal V7 is thus set so that a signal pulse of the duty control signal S7 (see FIG. FIGS. 6 and 7 ) is generated at the same time or shortly after a time at which the oscillator 6 is reset due to the frequency signal FS anyway.
  • the comparison signal V7 increases slowly.
  • ts denotes in FIG. 17 a time when the resonant circuit inductance begins to saturate.
  • the amplitude of the current measurement signal Vs2 now increases much faster. An abrupt increase in the amplitude can thereby for example, by the basis of the Figures 9 and 14 be prevented measures in which the current measurement signal via a coupling capacitor 84 or a controlled current source 83 directly affects the generation of the duty control signal S7, which already a shortening of the duty cycle is achieved even before the comparison signal V7 a shortening of the duty cycle can be achieved.
  • the excitation frequency f increases due to the shortening of the switch-on durations.
  • This increased frequency is for example in the range of 50 kHz.
  • the oscillator now operates in the saturation operating state, ie the duty control signal S7 determines the excitation frequency and not the frequency signal FS.
  • This transition of the oscillator 6 in the saturation operating state is detected by the sequence control (not shown), which then does not lower the frequency signal further.
  • Such a detection of the saturation operation state can be made with reference to FIG FIG. 7 For example, by the fact that the timing of a reset pulse generated by the comparator 67 and a pulse of the duty control signal S7 are compared with each other. If the pulse of the duty control signal S7 during several consecutive drive cycles in time before the reset pulse of the comparator, it can be assumed that the oscillator 6 is in the saturation mode.
  • the previously explained control of the comparison signal V7 prevents an uncontrolled increase in the resonant circuit amplitude during this operating state.
  • An increase of the comparison signal V7 after the saturation time ts can be explained in the illustrated example in that the current increase speed or the determined time change ⁇ V of the current measurement signal Vs2 at this time is still below the Setpoint / reference value is.
  • the oscillation amplitude increases until a time tmax_am at which the time change ⁇ V of the current measurement signal Vs2 reaches the reference value, so that no further increase in the comparison value V7 occurs. If no readjustment of the comparison signal would occur at the boundary between the normal operating state and the saturated operating state, the comparison signal would be almost constant until the beginning of the saturation operating state.
  • ti denotes in FIG. 17 a time when the lamp ignites.
  • the active power absorbed by the lamp increases so much that the oscillation amplitude breaks down.
  • the controller 7 first tries to counteract and raises the comparison signal V7 on. Because of the lower oscillation amplitude and the resulting longer duty cycle, the excitation frequency decreases again.
  • tn denotes in FIG. 17 a time at which the comparison signal V7 has risen so far that the normal operating state of the oscillator 6 is reached again.
  • the sequencer detects this transition of the oscillator into the normal operating state further lowers the frequency signal FS after a short delay time to an operating frequency, which is for example in the range of 40 kHz.
  • the controller 72 of the evaluation circuit is dimensioned such that it can not react quickly enough to such a very rapid increase. In this case, there will be a shutdown due to overcurrent by a non-illustrated, in the half-bridge existing overcurrent protection circuit.
  • the course of the resonant circuit voltage changes from a sinusoidal course to a trapezoidal course.
  • the effective rms value for an ignition of the lamp is higher with the same amplitude with a trapezoidal voltage curve than with a sinusoidal voltage curve.
  • it is now provided to detect the saturation depth ie to detect how much the Oscillating circuit inductance is operated in saturation. This can be done, for example, by evaluating the peak current or the maximum value of the current measurement signal Vs2. The saturation depth is higher, the higher this maximum value is.

Landscapes

  • Circuit Arrangements For Discharge Lamps (AREA)
EP08009105A 2008-05-16 2008-05-16 Procédé de commande d'une lampe fluorescente et appareil de montage de lampes Active EP2124510B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP08009105A EP2124510B1 (fr) 2008-05-16 2008-05-16 Procédé de commande d'une lampe fluorescente et appareil de montage de lampes
US12/467,008 US8242702B2 (en) 2008-05-16 2009-05-15 Method for driving a fluorescent lamp, and lamp ballast

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EP08009105A EP2124510B1 (fr) 2008-05-16 2008-05-16 Procédé de commande d'une lampe fluorescente et appareil de montage de lampes

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EP2184956A2 (fr) * 2008-11-11 2010-05-12 HÜCO Lightronic GmbH Appareil de montage électronique, appareil d'éclairage et son procédé de fonctionnement

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DE102006061357B4 (de) * 2006-12-22 2017-09-14 Infineon Technologies Austria Ag Verfahren zur Ansteuerung einer Leuchtstofflampe

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WO1999034647A1 (fr) * 1997-12-23 1999-07-08 Tridonic Bauelemente Gmbh Procede et dispositif permettant de detecter l'effet redresseur apparaissant dans une lampe a decharge
EP1066739B1 (fr) 1997-12-23 2002-02-27 Tridonic Bauelemente GmbH Procede et dispositif permettant de detecter l'effet redresseur apparaissant dans une lampe a decharge
US6525492B2 (en) 2000-06-19 2003-02-25 International Rectifier Corporation Ballast control IC with minimal internal and external components
US6617805B2 (en) 2000-10-20 2003-09-09 International Rectifier Corporation Ballast control IC with power factor correction
EP1333707A1 (fr) 2002-02-01 2003-08-06 TridonicAtco GmbH & Co. KG Ballast électronique pour une lampe à décharge
EP1337133A2 (fr) 2002-02-13 2003-08-20 Patent-Treuhand-Gesellschaft für elektrische Glühlampen mbH Circuit pour alimenter une lampe à décharge à fréquence variable pendant l' amorçage
US20030227264A1 (en) * 2002-06-11 2003-12-11 Patent-Treuhand-Gesellschaft Fur Elektrisch Gluhlampen Mbh Discharge lamp operating circuit having a circuit for detecting the proximity to capacitive operation
US20070057639A1 (en) * 2003-06-10 2007-03-15 Koninklijke Philips Electronics N.V. Light output modulation for data transmission
WO2005101921A2 (fr) * 2004-04-08 2005-10-27 International Rectifier Corporation Ci a commande de ballast et pfc
WO2006003560A1 (fr) * 2004-06-28 2006-01-12 Koninklijke Philips Electronics N.V. Circuit d'attaque de lampe a tube fluorescent
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US20050218831A1 (en) * 2005-06-30 2005-10-06 Ahteshamul Haque Ballast with circuit for detecting and eliminating an arc condition
EP1776000A2 (fr) 2005-10-12 2007-04-18 International Rectifier Corporation Circuit intégré à 8 pattes pour un ballast électronique muni d' une correction du facteur de puissance
DE102006011970A1 (de) * 2006-03-15 2007-09-20 Patent-Treuhand-Gesellschaft für elektrische Glühlampen mbH Geregeltes Vorschaltgerät für eine Lampe
DE102006061357A1 (de) * 2006-12-22 2008-06-26 Infineon Technologies Austria Ag Verfahren zur Ansteuerung einer Leuchtstofflampe

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2184956A2 (fr) * 2008-11-11 2010-05-12 HÜCO Lightronic GmbH Appareil de montage électronique, appareil d'éclairage et son procédé de fonctionnement
EP2184956A3 (fr) * 2008-11-11 2011-09-21 BAG engineering GmbH Appareil de montage électronique, appareil d'éclairage et son procédé de fonctionnement

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US8242702B2 (en) 2012-08-14
US20090284162A1 (en) 2009-11-19

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