EP2124125A1

EP2124125A1 - Process and temperature compensation in CMOS circuits

Info

Publication number: EP2124125A1
Application number: EP08156699A
Authority: EP
Inventors: Molosz Sroka; Jose Luis Gonzalez Jimenez; Xavier Aragones; Diego Mateo Pena
Original assignee: Seiko Epson Corp
Current assignee: Seiko Epson Corp
Priority date: 2008-05-21
Filing date: 2008-05-21
Publication date: 2009-11-25

Abstract

A circuit arrangement using CMOS technology is described comprising at least a first circuit (10,20) and a second, compensation circuit (50) for adaptively generating a biasing parameter (Vbias) for counter-acting temperature and process variations in the first circuit (10,20). The second circuit (50) is based on a constant-g_m bias generator and comprises a NMOS transistor (NM_R) operating in ohmic region. The second circuit (50) comprises two stages (51,52) with a substantially identical structure.

Description

BACKGROUND OF THE INVENTION

Technical field

The present invention relates to a circuit arrangement using CMOS technology enabling process and temperature compensation.

Description of related art

Temperature is commonly considered as a major factor affecting the reliability of CMOS electronic circuitry. Devices may have temporarily performance malfunctions with non-typical temperatures, mainly due to threshold voltage drift and other transistor parameter fluctuations, and variability of passive components, especially resistors, which altogether drive circuits out of specifications. CMOS Integrated Circuits (IC) technology has become more and more advanced in order to achieve goals of low-power consumption, high-performance and extremely high integration. Consequently, fabrication process variations have increased and device parameters show ever higher variability as technology scales down. In order to design reliable circuits it is important to consider the possible variations that will affect their fabrication and working environment. Therefore, there is a need of sufficiently accurate statistical models to describe the behaviour of variability of device parameters. Available simulation models of' sensitive devices such as transistors, resistors, capacitors and inductors allow designing with proper techniques to maintain the performance of circuits with temperature and process variations. Usually, temperature and process variability are solved separately. On one hand, temperature variations are compensated using a constant biasing circuit that provides a nearly constant voltage inside the specified temperature range, or a bias current or transconductance (gm) independently of temperature. On the other hand, process variations usually require calibration and self tuning.
It is an object of the invention to provide a circuit arrangement, wherein the same circuit is used for reducing both the impact of temperature and process variations on performance characteristics.

SUMMARY OF THE INVENTION

Thereto, according to an aspect of the invention a circuit arrangement is provided according to independent claim 1. Favourable embodiments are defined in dependent claims 2-11. According to an aspect of the invention a circuit arrangement is provided using CMOS technology comprising at least a first circuit and a second, compensation circuit for adaptively generating a biasing parameter for counter-acting temperature and process variations in the first circuit. The compensation circuit according to the invention can be used to adaptively bias any type of first circuit, although is particularly suitable for the case that the first circuit is a RF Low Noise Amplifier or a double-balance Mixer with bleeding current sources. The compensation circuit generates adequate bias parameter (e.g. voltage) characteristics in temperature in order to achieve a stable voltage gain and maintain other parameters within the specified temperature range of -40°C to +80°C. Moreover, the biasing circuit is designed such that process variations affect it in a way that allows counteracting process variability of the first circuit. Therefore, both variations are compensated efficiently with the actuation on the bias voltage and without interfering in the circuitry the first circuit.
According to an embodiment the second circuit is based on a constant-g_m bias generator. Such a circuit is very suitable for temperature compensation purposes. Preferably, the second circuit comprises a NMOS transistor operating in ohmic region instead of an integrated resistor, because NMOS transistors have smaller variability with process than integrated resistors. The gate voltage of such NMOS resistor must be chosen for generating the appropriate characteristics, and it must be also independent of temperature. For this reason, the second circuit .preferably consists of a second stage combined with the first stage, the two stages having substantially the same structure. In this way, the final implementation of the second circuit consisting of two stages needs only a supply voltage and it is specifically sized and tuned to generate adequate bias voltage characteristics for the first circuit that has to be compensated for temperature and process variations. In a preferred embodiment, the second circuit is adapted for generating a biasing voltage that is inversely proportional to temperature in a temperature range of interest. In case that the first circuit is a Low Noise Amplifier, the bias voltage at the second circuit is generated at a gate of NMOS transistors. Good compensation of process variability is obtained if the second circuit is adapted for generating a biasing voltage for extreme fast and slow process corners with a voltage difference in relation to the biasing voltage for a typical process corner, that is larger than a threshold.
The value of this threshold may vary as a function of the first circuit and the used technology. In some exemplary embodiments the threshold should be at least 5% of the value of the biasing voltage for the typical process corner.
Good compensation of process variability is furthermore obtained in case that the second circuit is adapted for generating a biasing voltage for corners of slow NMOS type, which is larger than the biasing voltage for the typical corner and a biasing voltage for corners of fast NMOS type, which is smaller than the biasing voltage for the typical corner and in case that the second circuit is adapted for generating a biasing voltage for corners of one NMOS type and different PMOS types with a mutual voltage difference that is smaller than a threshold.
In case that the first circuit is a mixer, the bias voltage at the second circuit is generated at a gate of PMOS transistors. Good compensation of process variability is obtained if the second circuit is adapted for generating a biasing voltage for extreme fast and slow process corners with a voltage difference in relation to the biasing voltage for a typical process corner, that is larger than a threshold. Good compensation of process variability is furthermore obtained in case that the second circuit is adapted for generating a biasing voltage for corners of slow PMOS type, which is smaller than the biasing voltage for the typical corner and a biasing voltage for corners of fast PMOS type, which is larger than the biasing voltage for the typical corner.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be better understood and its numerous objects and advantages will become more apparent to those skilled in the art by reference to the following drawings, in conjunction with the accompanying specification, in which:

Figure 1 shows a Low Noise Amplifier (LNA) circuit that may be temperature and process compensated according to the present invention.
Figure 2 shows a double-balance Mixer circuit with bleeding current sources that may be temperature and process compensated according to the present invention.
Figure 3 shows a first example of a temperature compensation circuit for the LNA circuit shown in figure 1, based on a classical constant-g_m circuit.
Figure 4 shows a second example of a temperature compensation circuit for the LNA circuit shown in figure 1, based on a classical constant-g_m circuit.
Figure 5 shows a double stage process and temperature compensation circuit according to the present invention for the LNA circuit shown in figure 1.
Figure 6 shows the biasing voltage characteristics for the LNA circuit with temperature and five process corners.
Figure 7 shows a double stage process and temperature compensation circuit according to the present invention for the double-balance Mixer circuit shown in figure 2.
Figure 8 shows the biasing voltage of' the bleeding transistors of the double-balance mixer circuit with temperature and five process corners.
Figure 9 shows the gain curves as a function of frequency of the Low Noise Amplifier circuit shown in figure 1 with compensation circuit and without the compensation circuit.
Figure 10 shows the gain curves as a function of frequency of the double-balance Mixer circuit shown in figure 2 with compensation circuit and without the compensation circuit.

Throughout the figures like reference numerals refer to like elements.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

According to the present invention a simple circuit arrangement is provided consisting of a first circuit and a second, compensation circuit that allows compensating adaptively the effects of temperature and process variation of the first circuit. The proposed circuit technique can be used to adaptively bias any circuit. However, it is specially suited to generate the gate bias voltage of gain transistors in RF building blocks. The structure of the second, compensation circuit is derived from classic temperature compensation circuits and with proper redesign becomes also a compensation technique for process variations.
The first circuit of the circuit arrangement is for example an RF Low Noise Amplifier (LNA) 10 shown in figure 1 and/or a double-balance mixer 20 with bleeding current sources shown in figure 2. The LNA has a single ended topology with inductively degenerated source and cascode transistors NM. It comprises an input matching circuit 15 and an output matching circuit (not shown in the figure). The LNA and the mixer are part of a RF front-end for low-low power radios operating in the 2.5 GHz ISM band and were designed and implemented with a 2P6M 0.18µm RF-CMOS process. As discussed in more detail herein after, the compensation circuit (second circuit) generates adequate bias voltage characteristics as a function of temperature in order to achieve a stable voltage gain and maintain other parameters within the specified temperature range of - 40°C to +80°C. Moreover, the second circuit is designed such that process variations affect it in a way that allows counteracting process variability of the LNA 10 and Mixer devices 20. A compensation circuit designed to compensate only temperature variability in the LNA circuit and based on a classical constant-g_m circuit containing a self-biased quad of transistors and a resistor is shown in figure 3. Such a circuit establishes an inversely proportional relation between the temperature dependence of the transconductance g_m of transistor NM₁ and the resistor R. The slope of this characteristic with temperature depends on the size ratio between transistors NM₁ and NM₂, A stable behaviour of the transconductance can be achieved also on a slave transistor NM₃ (being part of the biased circuit, e.g. the LNA) as a consequence of adequate gate-source voltage characteristics with temperature. The classical constant-g_m circuit shown in figure 3 can be modified by replacing the circuit's resistor with a NMOS transistor NM_R operating in ohmic region, as shown in figure 4, since NMOS transistors have smaller variability with process than integrated resistors. The gate voltage of such NMOS resistor must be chosen for generating the appropriate characteristics, and it must be also independent of temperature. For this reason, the final implementation of the compensation circuit 50, which is shown in figure 5, comprises a first stage 51 and a second stage 52 having the same structure as the first stage and combined therewith. In this way, the final implementation consisting of two stages needs only a supply voltage and it is specifically sized and tuned to generate adequate bias voltage characteristics for the circuit that has to be compensated for temperature and process variations. The transistor sizes shown in figure 5 correspond to the final version of the circuit that compensates both temperature and process variations for the LNA, as explained herein after.
The generation of the desired bias voltage characteristic with temperature depends on the sizing of circuit elements: the NMOS transistors biased in ohmic region and the quad-transistor of the self-biased structure. Thus, adjustments allow obtaining adequate magnitude and slope. As already mentioned, the ratio between main transistors of the quad structure allows obtaining the desired behaviour of transconductance with temperature. On the other hand, the biasing characteristic depends strongly on the sizes of the NMOS resistors as these act as a control of the current on the branches of the circuit,
The compensation circuit shown in Fig. 5, although being designed for temperature compensation, offers also a variable biasing voltage that can be used for process variations compensation. Analyzing the structure of the compensation circuit it is possible to deduce that process variations on this circuit could behave in a way to counteract the variability of the LNA. Therefore, the variable biasing voltage could be adjusted to adaptively match the needs of the LNA when process variations affect both the LNA and the compensation circuit in a similar way. Consequently, this will allow maintaining stable performance of the LNA despite temperature and die-to-die process variations, without the need of calibration.
The original temperature compensation circuit offers several points for tuning the behaviour of the characteristics of the biasing voltage so as to deal with both temperature and process variations. The main ways for the readjustment of this circuit to provide also for process compensation are:

Adapting the size of the circuit elements to generate appropriate biasing voltages for extreme fast and slow process corners, while maintaining original biasing for the typical process corner.
Maintaining original biasing voltage characteristics with temperature for the typical corner and adjusting in the best possible way the characteristics with temperature for extreme corners.
Minimizing the impact of PMOS transistors on the biasing voltage characteristics with process variations, because in the LNA no PMOS transistors are used.

In order to achieve these objectives the compensation circuits have to be resized. The behaviour of the compensation circuit shows that for extreme corners the biasing voltage characteristics must have a sufficiently large voltage difference in relation to typical process corner. Additionally, the voltage difference between corners for one NMOS type (either fast or slow) and different PMOS types (fast and slow) has to be reduced as much as possible. The redesign process implies the following modifications:

Size adjustment of quad-transistor structures to increase biasing voltage difference between corners, especially of its right-most NMOS transistors.
Adjustment of the equivalent resistance of "NMOS resistors" in order to have appropriate characteristics with process corners but keeping the adequate behaviour with temperature.
The impact of PMOS transistors can be reduced by resizing quad-transistor structure and increasing the current in the branches.

Figure 6 shows a simplified plot of the LNA bias voltage characteristics with temperature and process corners of the compensation circuit depicted in figure 5. The voltage difference diff₁ between the voltage as a function of temperature of' the typical corner TT and the voltage as a function of temperature of the slow NMOS and PMOS corner SS is in this example 55 mV. The voltage difference diff₂ between the voltage as a function of temperature of the typical corner TT and the voltage as a function of temperature of the fast NMOS and PMOS corner (FF) is 60 mV. So, in the circuit arrangement according to the embodiment shown in figures 1-5 the voltage differences diff₁,diff₂ are over 5% of the value of the biasing voltage for the typical process corner. The voltage differences diff₃,diff₄ between the fast NMOS and fast PMOS corner FF and the fast NMOS and slow PMOS corner FS on one hand and the slow NMOS and slow PMOS corner SS and the slow NMOS and fast PMOS corner SF on the other hand are clearly smaller.
The double-balanced Mixer circuit shown in figure 2 requires many different biasing voltages, as well as a constant current source. The RF and LO ports as well as the bleeding PMOS transistors require DC bias voltages. Indeed, the strong influence of the bleeding current on the Mixer DC operating point and voltage gain can be used to generate an adaptive voltage that compensates for the effects of temperature and process variations on the Mixer devices. The other bias voltages are obtained from the power supply using voltage dividers by combining two types of resistor with opposite temperature coefficient: diffusion resistors and poly resistors. The same technique is used for the resistive loads of the Mixer that set the voltage gain. Figure 7 shows the biasing circuit used for the generation of' the adaptive bleeding bias voltage, which is based on the same topology as the circuit of Figure 5. In this case, the bias voltage is generated at the gate of the PMOS transistors since the bleeding current sources are implemented with PMOS transistors. The behaviour of this bias voltage with process corners, which is shown in figure 8, must be just the opposite than in the case of the LNA, and this is easily achieved with the circuit of figure 7.
Resuming, the sized of the components of the compensation circuit should be selected as follows in order to obtain an optimized compensation for temperature and process variations:
The specific width and length for any transistor should be chosen such that:

In the typical temperature and process cases, the nominal biasing voltage is obtained.
Then, the bias generator is sized such that, for the typical corner, the slope of the Vbias/Temp compensates temperature variations in the biased (first) circuit.
Next, for typical temperature and for the extreme corners (FF and SS) the biasing voltage change in comparison with the typical case should equal (or approach as much as possible) the change required in the biased circuit in order to have a nearly constant performance in all the corners. Normally, this implies simulating the biased circuit with varying bias voltage in all the corners and finding the optimum bias voltage for each corner. These bias voltages are the input specifications for the biasing generator circuit re-sizing.
In the process of sizing the bias generator, the change of the slope of the Vbias/Temp curves for the extreme corners should be minimized compared with the typical one. Since the slope is set with the size ratio between the transistors of the bias generator, these relative ratios should be maintained as close as possible to the original ones. Actually, there is a trade-off between preserving the slope in all corners and the achieved, specified offsets in the bias voltage in all corners.

Figure 9 shows the gain curves as a function of frequency of the Low Noise Amplifier circuit shown in figure 1 and figure 10 shows the gain curves as a function of frequency of the double-balance mixer circuit shown in figure 2 with compensation circuit (bottom) and without the compensation circuit (top). Process variations effects in the double-balance mixer circuit without compensation circuit are catastrophic, especially in the SS corner, as can be observed in figure 10. The compensation circuit effectively provides an adaptive voltage that reduces process variability to acceptable levels.
As will be recognized by those skilled in the art, the innovative concepts described in the present application can be modified and varied over a wide range of applications. Although the compensation technique according to the invention has been described applied to a Low Noise Amplifier and a double-balance mixer, it is in principle applicable for temperature and process compensation of any circuit in which a biasing voltage can be used to counter-act process and temperature variations. Furthermore, the compensation technique is also applicable to compensation circuits that generate an adaptive biasing current instead of a biasing voltage. In such circuits, the effects of varying temperature and process changes should be accounted for not only in the biased circuit but also in the transconductor, transforming the biasing voltage into current.
Accordingly, the scope of patented subject matter should not be limited to any of the specific exemplary teachings discussed, but is instead defined by the following claims. Any reference signs in the claims shall not be construed as limiting the scope thereof.

Claims

Circuit arrangement using CMOS technology comprising at least a first circuit (10,20) and a second, compensation circuit (50) for adaptively generating a biasing parameter (Vbias) for counter-acting temperature and process variations in the first circuit (10,20).
Circuit arrangement according to claim 1, wherein the second circuit (50) is based on a constant-g_m bias generator.
Circuit arrangement according to claim 2, wherein the second circuit (50) comprises a NMOS transistor (NM_R) operating in ohmic region.
Circuit arrangement according to any of the preceding claims, wherein the second circuit (50) comprises two stages (51,52) with a substantially identical structure.
Circuit arrangement according to any of the preceding claims, wherein the second circuit (50) is adapted for generating a biasing voltage (Vbias) that is inversely proportional to temperature in a temperature range of interest.
Circuit arrangement according to claim 5 wherein the first circuit is a Low Noise Amplifier (10) and wherein the bias voltage at the second circuit (50) is generated at a gate of NMOS transistors, wherein the second circuit is adapted for generating a biasing voltage (Vbias) for extreme fast and slow process corners with a voltage difference (diff1,diff2) in relation to the biasing voltage for a typical process corner (TT), that is larger than a threshold.
Circuit arrangement according to claim 6 wherein the second circuit (50) is adapted for generating a biasing voltage for corners of slow NMOS type (SS,SF), which is larger than the biasing voltage for the typical corner (TT) and a biasing voltage for corners of fast NMOS type (FF,FS), which is smaller than the biasing voltage for the typical corner (TT).
Circuit arrangement according to claim 7 wherein the second circuit is adapted for generating a biasing voltage for corners of one NMOS type and different PMOS types with a mutual voltage difference (diff3,diff4) that is smaller than a threshold.
Circuit arrangement according to claim 5 wherein the first circuit is a mixer (20) and wherein the bias voltage at the second circuit (70) is generated at a gate of PMOS transistors, wherein the second circuit is adapted for generating a biasing voltage for extreme fast (FF) and slow process corners (SS) with a voltage difference in relation to the biasing voltage for a typical process corner (TT), that is larger than a threshold.
Circuit arrangement according to claim 9 wherein the second circuit (70) is adapted for generating a biasing voltage for corners of slow PMOS type (SS,FS), which is smaller than the biasing voltage for the typical corner (TT) and a biasing voltage for corners of fast PMOS type (FF,SF), which is larger than the biasing voltage for the typical corner (TT).
Circuit arrangement according to claim 6 or 9 wherein the threshold is at least 5% of the value of the biasing voltage for the typical process corner.