EP2124125A1 - Verfahren und Temperaturausgleich in CMOS-Schaltungen - Google Patents

Verfahren und Temperaturausgleich in CMOS-Schaltungen Download PDF

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Publication number
EP2124125A1
EP2124125A1 EP08156699A EP08156699A EP2124125A1 EP 2124125 A1 EP2124125 A1 EP 2124125A1 EP 08156699 A EP08156699 A EP 08156699A EP 08156699 A EP08156699 A EP 08156699A EP 2124125 A1 EP2124125 A1 EP 2124125A1
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EP
European Patent Office
Prior art keywords
circuit
voltage
biasing voltage
corners
arrangement according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP08156699A
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English (en)
French (fr)
Inventor
Molosz Sroka
Jose Luis Gonzalez Jimenez
Xavier Aragones
Diego Mateo Pena
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
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Seiko Epson Corp
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Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to EP08156699A priority Critical patent/EP2124125A1/de
Publication of EP2124125A1 publication Critical patent/EP2124125A1/de
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors

Definitions

  • the present invention relates to a circuit arrangement using CMOS technology enabling process and temperature compensation.
  • CMOS Integrated Circuits technology has become more and more advanced in order to achieve goals of low-power consumption, high-performance and extremely high integration. Consequently, fabrication process variations have increased and device parameters show ever higher variability as technology scales down. In order to design reliable circuits it is important to consider the possible variations that will affect their fabrication and working environment. Therefore, there is a need of sufficiently accurate statistical models to describe the behaviour of variability of device parameters.
  • a circuit arrangement is provided according to independent claim 1. Favourable embodiments are defined in dependent claims 2-11.
  • a circuit arrangement is provided using CMOS technology comprising at least a first circuit and a second, compensation circuit for adaptively generating a biasing parameter for counter-acting temperature and process variations in the first circuit.
  • the compensation circuit according to the invention can be used to adaptively bias any type of first circuit, although is particularly suitable for the case that the first circuit is a RF Low Noise Amplifier or a double-balance Mixer with bleeding current sources.
  • the compensation circuit generates adequate bias parameter (e.g.
  • the biasing circuit is designed such that process variations affect it in a way that allows counteracting process variability of the first circuit. Therefore, both variations are compensated efficiently with the actuation on the bias voltage and without interfering in the circuitry the first circuit.
  • the second circuit is based on a constant-g m bias generator.
  • a constant-g m bias generator Such a circuit is very suitable for temperature compensation purposes.
  • the second circuit comprises a NMOS transistor operating in ohmic region instead of an integrated resistor, because NMOS transistors have smaller variability with process than integrated resistors.
  • the gate voltage of such NMOS resistor must be chosen for generating the appropriate characteristics, and it must be also independent of temperature.
  • the second circuit .preferably consists of a second stage combined with the first stage, the two stages having substantially the same structure. In this way, the final implementation of the second circuit consisting of two stages needs only a supply voltage and it is specifically sized and tuned to generate adequate bias voltage characteristics for the first circuit that has to be compensated for temperature and process variations.
  • the second circuit is adapted for generating a biasing voltage that is inversely proportional to temperature in a temperature range of interest.
  • the bias voltage at the second circuit is generated at a gate of NMOS transistors. Good compensation of process variability is obtained if the second circuit is adapted for generating a biasing voltage for extreme fast and slow process corners with a voltage difference in relation to the biasing voltage for a typical process corner, that is larger than a threshold.
  • this threshold may vary as a function of the first circuit and the used technology. In some exemplary embodiments the threshold should be at least 5% of the value of the biasing voltage for the typical process corner.
  • the second circuit is adapted for generating a biasing voltage for corners of slow NMOS type, which is larger than the biasing voltage for the typical corner and a biasing voltage for corners of fast NMOS type, which is smaller than the biasing voltage for the typical corner and in case that the second circuit is adapted for generating a biasing voltage for corners of one NMOS type and different PMOS types with a mutual voltage difference that is smaller than a threshold.
  • the bias voltage at the second circuit is generated at a gate of PMOS transistors.
  • Good compensation of process variability is obtained if the second circuit is adapted for generating a biasing voltage for extreme fast and slow process corners with a voltage difference in relation to the biasing voltage for a typical process corner, that is larger than a threshold.
  • Good compensation of process variability is furthermore obtained in case that the second circuit is adapted for generating a biasing voltage for corners of slow PMOS type, which is smaller than the biasing voltage for the typical corner and a biasing voltage for corners of fast PMOS type, which is larger than the biasing voltage for the typical corner.
  • a simple circuit arrangement consisting of a first circuit and a second, compensation circuit that allows compensating adaptively the effects of temperature and process variation of the first circuit.
  • the proposed circuit technique can be used to adaptively bias any circuit. However, it is specially suited to generate the gate bias voltage of gain transistors in RF building blocks.
  • the structure of the second, compensation circuit is derived from classic temperature compensation circuits and with proper redesign becomes also a compensation technique for process variations.
  • the first circuit of the circuit arrangement is for example an RF Low Noise Amplifier (LNA) 10 shown in figure 1 and/or a double-balance mixer 20 with bleeding current sources shown in figure 2 .
  • the LNA has a single ended topology with inductively degenerated source and cascode transistors NM. It comprises an input matching circuit 15 and an output matching circuit (not shown in the figure).
  • the LNA and the mixer are part of a RF front-end for low-low power radios operating in the 2.5 GHz ISM band and were designed and implemented with a 2P6M 0.18 ⁇ m RF-CMOS process.
  • the compensation circuit (second circuit) generates adequate bias voltage characteristics as a function of temperature in order to achieve a stable voltage gain and maintain other parameters within the specified temperature range of - 40°C to +80°C.
  • the second circuit is designed such that process variations affect it in a way that allows counteracting process variability of the LNA 10 and Mixer devices 20.
  • a compensation circuit designed to compensate only temperature variability in the LNA circuit and based on a classical constant-g m circuit containing a self-biased quad of transistors and a resistor is shown in figure 3 .
  • Such a circuit establishes an inversely proportional relation between the temperature dependence of the transconductance g m of transistor NM 1 and the resistor R.
  • the slope of this characteristic with temperature depends on the size ratio between transistors NM 1 and NM 2 .
  • a stable behaviour of the transconductance can be achieved also on a slave transistor NM 3 (being part of the biased circuit, e.g. the LNA) as a consequence of adequate gate-source voltage characteristics with temperature.
  • the classical constant-g m circuit shown in figure 3 can be modified by replacing the circuit's resistor with a NMOS transistor NM R operating in ohmic region, as shown in figure 4 , since NMOS transistors have smaller variability with process than integrated resistors.
  • the gate voltage of such NMOS resistor must be chosen for generating the appropriate characteristics, and it must be also independent of temperature.
  • the final implementation of the compensation circuit 50 which is shown in figure 5 , comprises a first stage 51 and a second stage 52 having the same structure as the first stage and combined therewith.
  • the final implementation consisting of two stages needs only a supply voltage and it is specifically sized and tuned to generate adequate bias voltage characteristics for the circuit that has to be compensated for temperature and process variations.
  • the transistor sizes shown in figure 5 correspond to the final version of the circuit that compensates both temperature and process variations for the LNA, as explained herein after.
  • the generation of the desired bias voltage characteristic with temperature depends on the sizing of circuit elements: the NMOS transistors biased in ohmic region and the quad-transistor of the self-biased structure. Thus, adjustments allow obtaining adequate magnitude and slope. As already mentioned, the ratio between main transistors of the quad structure allows obtaining the desired behaviour of transconductance with temperature. On the other hand, the biasing characteristic depends strongly on the sizes of the NMOS resistors as these act as a control of the current on the branches of the circuit,
  • the compensation circuit shown in Fig. 5 although being designed for temperature compensation, offers also a variable biasing voltage that can be used for process variations compensation. Analyzing the structure of the compensation circuit it is possible to deduce that process variations on this circuit could behave in a way to counteract the variability of the LNA. Therefore, the variable biasing voltage could be adjusted to adaptively match the needs of the LNA when process variations affect both the LNA and the compensation circuit in a similar way. Consequently, this will allow maintaining stable performance of the LNA despite temperature and die-to-die process variations, without the need of calibration.
  • the original temperature compensation circuit offers several points for tuning the behaviour of the characteristics of the biasing voltage so as to deal with both temperature and process variations.
  • the main ways for the readjustment of this circuit to provide also for process compensation are:
  • the compensation circuits have to be resized.
  • the behaviour of the compensation circuit shows that for extreme corners the biasing voltage characteristics must have a sufficiently large voltage difference in relation to typical process corner. Additionally, the voltage difference between corners for one NMOS type (either fast or slow) and different PMOS types (fast and slow) has to be reduced as much as possible.
  • the redesign process implies the following modifications:
  • FIG. 6 shows a simplified plot of the LNA bias voltage characteristics with temperature and process corners of the compensation circuit depicted in figure 5 .
  • the voltage difference diff 1 between the voltage as a function of temperature of' the typical corner TT and the voltage as a function of temperature of the slow NMOS and PMOS corner SS is in this example 55 mV.
  • the voltage difference diff 2 between the voltage as a function of temperature of the typical corner TT and the voltage as a function of temperature of the fast NMOS and PMOS corner (FF) is 60 mV. So, in the circuit arrangement according to the embodiment shown in figures 1-5 the voltage differences diff 1 ,diff 2 are over 5% of the value of the biasing voltage for the typical process corner.
  • the voltage differences diff 3 ,diff 4 between the fast NMOS and fast PMOS corner FF and the fast NMOS and slow PMOS corner FS on one hand and the slow NMOS and slow PMOS corner SS and the slow NMOS and fast PMOS corner SF on the other hand are clearly smaller.
  • the double-balanced Mixer circuit shown in figure 2 requires many different biasing voltages, as well as a constant current source.
  • the RF and LO ports as well as the bleeding PMOS transistors require DC bias voltages. Indeed, the strong influence of the bleeding current on the Mixer DC operating point and voltage gain can be used to generate an adaptive voltage that compensates for the effects of temperature and process variations on the Mixer devices.
  • the other bias voltages are obtained from the power supply using voltage dividers by combining two types of resistor with opposite temperature coefficient: diffusion resistors and poly resistors. The same technique is used for the resistive loads of the Mixer that set the voltage gain.
  • Figure 7 shows the biasing circuit used for the generation of' the adaptive bleeding bias voltage, which is based on the same topology as the circuit of Figure 5 .
  • the bias voltage is generated at the gate of the PMOS transistors since the bleeding current sources are implemented with PMOS transistors.
  • the behaviour of this bias voltage with process corners, which is shown in figure 8 must be just the opposite than in the case of the LNA, and this is easily achieved with the circuit of figure 7 .
  • the sized of the components of the compensation circuit should be selected as follows in order to obtain an optimized compensation for temperature and process variations:
  • Figure 9 shows the gain curves as a function of frequency of the Low Noise Amplifier circuit shown in figure 1 and figure 10 shows the gain curves as a function of frequency of the double-balance mixer circuit shown in figure 2 with compensation circuit (bottom) and without the compensation circuit (top).
  • Process variations effects in the double-balance mixer circuit without compensation circuit are catastrophic, especially in the SS corner, as can be observed in figure 10 .
  • the compensation circuit effectively provides an adaptive voltage that reduces process variability to acceptable levels.
  • the innovative concepts described in the present application can be modified and varied over a wide range of applications.
  • the compensation technique according to the invention has been described applied to a Low Noise Amplifier and a double-balance mixer, it is in principle applicable for temperature and process compensation of any circuit in which a biasing voltage can be used to counter-act process and temperature variations.
  • the compensation technique is also applicable to compensation circuits that generate an adaptive biasing current instead of a biasing voltage. In such circuits, the effects of varying temperature and process changes should be accounted for not only in the biased circuit but also in the transconductor, transforming the biasing voltage into current.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)
  • Logic Circuits (AREA)
EP08156699A 2008-05-21 2008-05-21 Verfahren und Temperaturausgleich in CMOS-Schaltungen Withdrawn EP2124125A1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP08156699A EP2124125A1 (de) 2008-05-21 2008-05-21 Verfahren und Temperaturausgleich in CMOS-Schaltungen

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP08156699A EP2124125A1 (de) 2008-05-21 2008-05-21 Verfahren und Temperaturausgleich in CMOS-Schaltungen

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017099926A1 (en) * 2015-12-11 2017-06-15 Sandisk Technologies Llc Voltage generator to compensate for process corner and temperature variations

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5532650A (en) * 1994-01-20 1996-07-02 Alps Electric Co., Ltd. High-frequency amplifier
EP0748044A2 (de) * 1995-06-09 1996-12-11 Analog Devices, Inc. Mischer mit variabler Verstärkung mit erhöhten linearität und geringer Schaltgeräusch
US6407623B1 (en) * 2001-01-31 2002-06-18 Qualcomm Incorporated Bias circuit for maintaining a constant value of transconductance divided by load capacitance
US6535068B1 (en) * 2001-02-17 2003-03-18 Microtune (Texas), L.P. System and method for temperature compensated IF amplifier
US20070075699A1 (en) * 2005-10-05 2007-04-05 Taiwan Semiconductor Manufacturing Co., Ltd. Sub-1V bandgap reference circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5532650A (en) * 1994-01-20 1996-07-02 Alps Electric Co., Ltd. High-frequency amplifier
EP0748044A2 (de) * 1995-06-09 1996-12-11 Analog Devices, Inc. Mischer mit variabler Verstärkung mit erhöhten linearität und geringer Schaltgeräusch
US6407623B1 (en) * 2001-01-31 2002-06-18 Qualcomm Incorporated Bias circuit for maintaining a constant value of transconductance divided by load capacitance
US6535068B1 (en) * 2001-02-17 2003-03-18 Microtune (Texas), L.P. System and method for temperature compensated IF amplifier
US20070075699A1 (en) * 2005-10-05 2007-04-05 Taiwan Semiconductor Manufacturing Co., Ltd. Sub-1V bandgap reference circuit

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
DAI Y ET AL: "Threshold voltage based CMOS voltage reference", IEE PROCEEDINGS: CIRCUITS DEVICES AND SYSTEMS, INSTITUTION OF ELECTRICAL ENGINEERS, STENVENAGE, GB, vol. 151, no. 1, 26 January 2004 (2004-01-26), pages 58 - 62, XP006021288, ISSN: 1350-2409 *
HENRI J OGUEY ET AL: "CMOS Current Reference Without Resistance", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 32, no. 7, 1 July 1997 (1997-07-01), XP011060518, ISSN: 0018-9200 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017099926A1 (en) * 2015-12-11 2017-06-15 Sandisk Technologies Llc Voltage generator to compensate for process corner and temperature variations
US9959915B2 (en) 2015-12-11 2018-05-01 Sandisk Technologies Llc Voltage generator to compensate for process corner and temperature variations

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