EP2013917A1 - Radiation-emitting semiconductor body with carrier substrate and method for the production thereof - Google Patents

Abstract

The invention relates to a radiation-emitting semiconductor body with carrier substrate and a method for the production thereof. The method involves producing a structured connection of a semiconductor layer sequence (2) to a carrier substrate wafer (1). The semiconductor layer sequence is subdivided into a plurality of semiconductor layer stacks (200) by means of cuts (6) through the semiconductor layer sequence and the carrier substrate wafer (1) is subdivided into a plurality of carrier substrates (100) by means of cuts (7) through the carrier substrate wafer (1). In this case, the structured connection is embodied in such a way that at least one semiconductor layer stack (200) is connected to precisely one associated carrier substrate (100). Moreover, at least one cut (7) through the carrier substrate wafer is lengthened by none of the cuts (6) through the semiconductor layer sequence in such a way that a rectilinear cut through the carrier substrate wafer and the semiconductor layer sequence results.

Description

Radiation-Halbleiterk ^'örper with supporting substrate and methods for producing such

The invention relates to a radiation-emitting semiconductor body with a carrier substrate and to a method for producing the same.

In conventional methods for producing semiconductor bodies with a carrier substrate, a carrier substrate wafer and a semiconductor layer sequence are connected to one another over the entire area. A subdivision into individual semiconductor bodies is then only possible through sections through the semiconductor layer sequence and through the semiconductor layer

Carrier substrate wafer possible, which run so that each of the sections through the semiconductor layer sequence and by the carrier substrate wafer, which limit the semiconductor body on one side, in a common plane or surface or, in other words, represent a single cut.

The mutually facing surfaces of the semiconductor layer stack and the associated carrier substrate then necessarily have the same dimensions are arranged flush. Such semiconductor bodies are usually electrically contacted with a bonding pad arranged on the radiation decoupling surface.

For example, in order to avoid shading of the bondpad, it may be desirable to arrange it not on the semiconductor layer stack, but on the carrier substrate. For this purpose, it is possible, for example, to produce semiconductor bodies in which the semiconductor layer stack comprises the Carrier substrate not completely covered. For example, the document DE 103 39 985 A1 specifies a semiconductor body in which a semiconductor layer stack is arranged on a carrier substrate which has a larger base area than the semiconductor layer stack. Such semiconductor bodies can not be produced in the wafer composite by conventional methods.

An object of the present invention is to provide a simplified and cost-effective method for producing radiation-emitting semiconductor bodies with a carrier substrate. A further object of the present invention is to provide a radiation-emitting semiconductor body with a carrier substrate, which has the largest possible radiation exit area and can be inexpensively manufactured and simply contacted.

These objects are achieved by a method having the steps of claim 1 and by a semiconductor body having the features of claim 27.

Advantageous embodiments and further developments of the method or of the semiconductor body are specified in the dependent claims.

The disclosure of the claims is hereby expressly incorporated by reference into the description.

A method according to the invention for producing a plurality of radiation-emitting semiconductor bodies with a carrier substrate comprises in particular the steps of: providing a carrier-substrate wafer; - forming a semiconductor layer sequence that is suitable ^"for generating electromagnetic radiation;

- Producing a structured connection of the semiconductor layer sequence with the carrier substrate wafer;

- dividing the semiconductor layer sequence into a plurality of semiconductor layer stacks by means of cuts through the semiconductor layer sequence;

- dividing the carrier substrate wafer into a plurality of carrier substrates having cuts in the carrier substrate wafer; and

- Separating the semiconductor layer stack with the associated carrier substrates to individual semiconductor bodies, wherein

- The structured connection is carried out such that at least one semiconductor layer stack is connected to exactly one associated carrier substrate; and

- At least one section through the carrier substrate wafer of any of the sections through the semiconductor layer sequence is extended such that there is a straight cut through the carrier substrate wafer and the semiconductor layer sequence.

The semiconductor layer sequence preferably comprises a pn junction, a double heterostructure, a single quantum well or more preferably a multiple quantum well structure (MQW) for generating radiation. The term quantum well structure does not contain any information about the dimensionality of the quantization. It thus includes quantum wells, quantum wires and quantum dots and any combination of these structures. Examples of MQW structures are described in the publications WO 01/39282, US 5,831,277, US 6,172,382 Bl and US 5,684,309, the disclosure content of which is hereby incorporated by reference. Preferably, the structured connection is carried out such that a plurality of semiconductor layer stacks is respectively connected to exactly one associated carrier substrate. Particularly preferably, each semiconductor layer stack is connected to exactly one associated carrier substrate.

When producing the structured connection, the semiconductor layer sequence does not have to be directly adjacent to the carrier substrate wafer. Rather, one or more further layers, for example a connection layer, can be arranged between the semiconductor layer sequence and the carrier substrate wafer.

The method makes use of the idea that a structured connection between a semiconductor layer sequence and a carrier substrate wafer can be produced. The composite comprising the semiconductor layer sequence and the carrier substrate wafer is subsequently structured to form individual semiconductor bodies, which each comprise a semiconductor layer stack and a carrier substrate. This can be done, for example, by cuts through the semiconductor layer sequence and by cuts through the carrier substrate wafer.

The production of a structured connection between the semiconductor layer sequence and the carrier substrate wafer advantageously makes it possible to cut through the

Semiconductor layer sequence and by the carrier substrate wafer offset from each other to perform. In other words, the projection of at least one section through the carrier substrate wafer into the connection plane contains the projection none of the cuts through the semiconductor layer sequence in this plane completely.

The connection plane is that plane which contains the connection surface or an area of the connection layer.

Sections through the semiconductor layer sequence do not need to cut through the carrier substrate wafer. Neither do cuts through the carrier substrate wafer need to sever the semiconductor layer sequence. Nevertheless, these sections produce individual semiconductor bodies in which the semiconductor layer stack and the associated carrier substrate are advantageously not arranged flush with one another. Rather, semiconductor bodies with a semiconductor layer stack and a carrier substrate can be produced in the wafer composite in which the semiconductor layer stack does not cover a connection region of the carrier substrate in a plan view of the front side of the semiconductor layer stack facing away from the carrier substrate and / or in which the carrier substrate is viewed in plan view from that of FIG

Semiconductor layer stack side facing away from the carrier substrate, a first portion of the semiconductor layer stack is not covered.

This is practically the complete

Semiconductor layer sequence used to produce semiconductor layer stack. Apart from the loss through the cuts and possibly. an edge of the semiconductor layer sequence which is eliminated due to geometric conditions - for example, in the production of semiconductor bodies having a rectangular base area of a semiconductor layer sequence with a circular base area - Preferably no material of the semiconductor layer sequence is lost.

In addition, the number of process and adjustment steps for producing a plurality of semiconductor bodies, in which a connection region of the carrier substrate is not covered by the semiconductor layer sequence, is particularly small.

Preferably, in at least one semiconductor body, but preferably in a plurality of semiconductor bodies, particularly preferably in all semiconductor bodies produced by the method, there is at least one offset direction contained in the connection plane. In the offset direction, adjacent sections are offset from one another by the semiconductor layer sequence and by the carrier substrate wafer. The side surfaces produced by the cuts, which delimit a semiconductor layer stack and the associated carrier substrate in plan view along this direction, are then shifted in the offset direction from one another. The projections of the offset sections or side surfaces in the connection plane then do not touch or intersect. The offset direction is parallel to the distance vector between the projections.

Alternatively or additionally, adjacent sections may be formed differently by the semiconductor layer sequence and by the carrier substrate wafer. For example, they can be curved differently and / or at least one of the cuts can be guided over the corner. Then, it may happen that the side surfaces of the semiconductor layer stack and the associated carrier substrate of a semiconductor body which delimits from these sections is shifted in places against each other and in places are flush.

As a rule, the growth of the semiconductor layer sequence takes place along the surface normal of the connection plane pointing to the front side of the semiconductor layer sequence facing away from the carrier substrate. This surface normal is called the "growth direction". However, due to certain process conditions, for example, there may be slight deviations from the direction designated as growth direction or variations in the direction of the actual layer growth.

Usually, the growth direction also corresponds to the main emission direction of the semiconductor bodies. However, it is also possible to connect the semiconductor layer sequence to the carrier substrate wafer such that the direction of the actual layer growth runs opposite to the direction designated as the "growth direction", which is predetermined by the surface normal of the connection plane facing the front side of the semiconductor layer sequence facing away from the carrier substrate. In particular, in this case, it can also be provided that the radiation generated by the semiconductor bodies during operation is coupled out through the carrier substrate wafer.

The sections are expediently guided in such a way that the semiconductor body has a step which is formed by the semiconductor layer stack and the carrier substrate. The semiconductor layer stack therefore covers the side of a first region of the carrier substrate facing it, while the surface facing the semiconductor layer stack covers a Terminal region of the carrier substrate is free from the semiconductor layer stack.

If there are at least two pairs of staggered sections through the semiconductor layer sequence and in the carrier substrate, then the semiconductor layer stack of at least one semiconductor body, preferably a plurality of semiconductor bodies, but more preferably all semiconductor bodies, may have a first partial area which, essentially parallel to the connection plane, transitions over protrudes the edge of the carrier substrate.

The semiconductor body then has a second step, which is formed by the semiconductor layer sequence and the carrier substrate, such that the first subregion of the semiconductor layer stack represents an overhang, which is located in an offset direction next to the carrier substrate.

In other words, the composite comprising the semiconductor layer sequence and the carrier substrate wafer is provided with at least one pair of mutually offset sections, which on the one hand faces away from the carrier substrate wafer side of the semiconductor layer sequence and on the other side facing away from the semiconductor layer sequence side of the carrier substrate wafer, preferably along and against Growth direction, led, subdivided. Only together with a region left free of the structured connection in the connection plane does this produce at least one coherent "cut" which, viewed from the side of the carrier substrate wafer facing away from the semiconductor layer sequence, first cuts through the carrier substrate wafer, then kinks and subsequently parallel to the connection plane along an offset direction, runs before it kinks again and, preferably in the growth direction, cuts through the semiconductor layer sequence.

There are for example, only an offset direction, then sections may be prepared by the semiconductor layer sequence and the carrier substrate, which extend parallel to the direction of displacement, ^• be arranged in a common plane, so that they together form a straight continuous section of the semiconductor layer sequence and the carrier substrate wafer.

Sections through the semiconductor layer sequence and through the carrier substrate wafer, which do not run parallel to the offset direction, may for example be offset from one another and / or have different curvatures, so that in at least one semiconductor body, the semiconductor layer stack does not cover a connection region of the associated carrier substrate, and preferably has a first subregion which protrudes beyond the edge of the carrier substrate in this direction. Particularly preferably, these sections are perpendicular to the offset direction.

However, it is also possible for there to be a first and a second offset direction, both lying in the connection plane and preferably perpendicular to one another. As a rule, at least one pair of sections is then offset from one another in the first offset direction by the semiconductor layer sequence and by the carrier substrate wafer, and at least one further pair of sections through the semiconductor layer sequence and through the carrier substrate wafer are offset from one another in the second offset direction. In at least one semiconductor body is in this case the Semiconductor layer stack shifted in the first and in the second offset direction against the associated carrier substrate. Preferably, the cuts are made such that none of the cuts through the semiconductor layer sequence is completely contained in one of the regions defined by the imaginary continuation of a cut in the carrier substrate to the front of the semiconductor layer sequence.

In a particularly preferred embodiment, there are a plurality of sections in the carrier substrate and through the semiconductor layer sequence, which run parallel to one another, and a second plurality of sections in the carrier substrate and through the semiconductor layer sequence which are parallel to one another and perpendicular to the first plurality.

If appropriate, the sections through the semiconductor layer sequence and / or through the carrier substrate wafer may also be used to subdivide the one, several or all of the further layers.

However, cuts through the cuts

Semiconductor layer sequence not the carrier substrate wafer and cuts through the carrier substrate wafer do not separate the semiconductor layer sequence unless they together form a straight line cut.

The cuts through the carrier substrate wafer and / or through the semiconductor layer sequence are preferably carried out by means of sawing and / or by means of other suitable mechanical (for example milling) or chemical (for example dry etching) material-removing processes. In an alternative expedient embodiment of the method the cuts are made by means of a material-removing laser process.

In the present context, the term "cut" covers all trenches which are produced before or after the connection of the semiconductor layer sequence and at least partially sever the semiconductor layer sequence or the carrier substrate wafer and thereby - optionally together with points not connected by the structured connection in the connection plane - in semiconductor layer stack or Subdivide carrier substrates.

In a preferred embodiment of the method, the production of the structured connection first comprises a full-area connection of the semiconductor layer sequence to the carrier substrate wafer. Subsequently, the full-surface connection is partially resolved again.

According to an advantageous embodiment of this embodiment, a sacrificial layer is produced. The sacrificial layer is preferably adjacent to the bonding layer or surface by means of which the full-area connection is made. The partial release of the connection between the carrier substrate wafer and the semiconductor layer sequence preferably takes place by partial damage or destruction of the sacrificial layer. A layer serving primarily for a different purpose may also be suitable as a sacrificial layer and identified and used as such.

Preferably, the partial release of the connection takes place by means of laser radiation. In this case, the sacrificial layer is expediently carried along by the carrier substrate wafer Laser radiation irradiated. Suitable materials for a sacrificial layer preferably have a suitable, in particular small, bandgap and / or low chemical stability and comprise, for example, GaN, InGaN or other nitride compound semiconductor materials.

A method for the full-surface separation of two material layers by means of irradiation with electromagnetic radiation is disclosed, for example, in the document WO 98/14986 A1, the disclosure content of which is hereby incorporated by reference.

In the present context, the irradiation takes place primarily at those points where the connection is to be released.

This is achieved, for example, by irradiation through a mask. The mask need not be connected to the carrier substrate wafer. Alternatively, however, it can also be applied to the carrier substrate wafer. The mask is irradiated areally or sequentially, for example by moving a line-shaped radiation source relative to it.

An alternative to radiation through a mask is to use at least one laser beam with a sufficiently small beam cross-section, which is moved relative to the carrier substrate and thereby decomposes the sacrificial layer according to the desired structure and in this way the not connected to the carrier substrate areas of the semiconductor layer sequence generated. In an alternative embodiment of the method according to the invention, no complete connection between the semiconductor layer sequence and the carrier substrate wafer is produced from the beginning. Instead, the semiconductor layer sequence and the carrier substrate wafer are connected to one another only in places, primarily only those regions in which the semiconductor layer stack and the carrier substrate overlap in the later semiconductor bodies.

The full area or in places connection between the carrier substrate wafer and the semiconductor layer sequence can be produced, for example, by means of a connection layer. This can be formed on the carrier substrate wafer or on the semiconductor layer sequence.

The connecting layer has, for example, a solder layer, which in particular comprises or consists of a solder such as Au, AuSn, Pd, In and / or Pt. Alternatively or additionally, an adhesive layer, for example based on an epoxy resin, is conceivable as a bonding layer.

As a further alternative, a connection layer can be provided which imparts the adhesion via a diffusion process. For example, germanium-gold layers, metal oxide or metal nitride layers and / or dielectric layers are suitable for this purpose. The latter may for example contain or consist of SiO, SiN and / or TiN.

In another embodiment, a fügeschichtlose connection, ie a connection to a Connecting surface but without a connection layer between the carrier substrate wafer and the semiconductor layer sequence, provided.

The adhesion between the carrier substrate wafer and the growth-adjacent surface is then mediated, for example, by electrostatic forces and / or by diffusion, which may, for example, result in the formation of a eutectic. To produce the connection, for example, an electrical voltage can be applied between the semiconductor layer sequence and the carrier substrate wafer, and / or heat can be supplied to the carrier substrate wafer and / or the semiconductor layer sequence.

If only a local connection between the semiconductor layer sequence and the carrier substrate wafer is produced from the beginning, the partial connection preferably takes place by means of a soldering process. For this purpose, in an expedient embodiment of the method, the solder layer according to the desired pattern of the connection layer is already structured on the main surface of the carrier substrate wafer to be connected to the semiconductor layer sequence or on the rear side of the semiconductor layer sequence facing the carrier substrate wafer.

The structuring is preferably achieved by means of a mask, through which the solder is applied, for example by vapor deposition or sputtering. In an alternative embodiment, the solder is applied over the entire surface and structured in a subsequent method step, which comprises, for example, a lithographic process. In addition, the production of a structured adhesive surface or the production of a structured, fichtgeschichtlosen connection, for example by anodic bonding, such as by anodic bonding of a patterned layer, in particular a structured electrically conductive layer such as a metal layer, is possible.

Subsections of the semiconductor layer sequence may arise in the method according to the invention, such as edge regions of the semiconductor layer sequence and / or regions between the semiconductor layer stacks provided for the semiconductor bodies, which are not part of the desired semiconductor bodies and in the present case are not referred to as semiconductor layer stacks. These are preferably not even connected to the carrier substrate wafer or, after bonding, for example, after a full-area connection of semiconductor layer sequence and carrier substrate wafer, released again from the carrier substrate wafer. After forming the cuts through the semiconductor layer sequence and through the carrier substrate wafer to define the

Semiconductor layer stack these subregions are then preferably removed. Alternatively, such regions of the semiconductor layer sequence can be connected to parts of the carrier substrate wafer that do not represent carrier substrates-for example with edge regions of the carrier substrate wafer.

However, the method is preferably carried out in this way, ie the semiconductor layer sequence is subdivided into sections such that the subareas of the semiconductor layer sequence not used for semiconductor bodies make up as small a proportion as possible of the entire semiconductor layer sequence. With the method according to the invention, semiconductor bodies in which in each case part of the surface of the carrier substrate facing the semiconductor layer stack is not covered by the semiconductor layer stack can advantageously be produced in the wafer composite. At the same time, the method advantageously allows a very good utilization of the available semiconductor layer sequence, whereby a cost-effective production of the semiconductor body can be ensured.

In a preferred embodiment of the method, a contact layer, preferably at least partially radiation-permeable, is applied to a semiconductor body, which at least partially covers a surface of its semiconductor layer stack facing away from the carrier substrate and at least part of the connection region of its carrier substrate, that is, the region not overlapping with the semiconductor layer stack , In any case, the contact layer preferably covers substantially the entire surface of the semiconductor layer stack facing away from the carrier substrate.

In a preferred embodiment, the contact layer is pulled from the front side of the semiconductor layer stack over at least one side surface onto the connection region of the carrier substrate. The contact layer thus preferably also covers at least one side surface of the semiconductor layer stack at least partially.

In particular, in this embodiment, it may be appropriate to produce the contact layer in several parts. For example, portions of the contact layer may be sequentially formed, for example, when applied to areas that are not parallel to one another. moreover For example, it is possible that a partial region of the contact layer, which is also formed in particular on the front side of the semiconductor layer stack, has a material which is at least partially permeable to electromagnetic radiation, while another partial region is substantially radiation-impermeable. Conveniently, subregions of the contact layer adjoin one another or overlap, so that they are electrically conductively connected.

The contact layer or a partial region of the contact layer preferably comprises or consists of a transparent conductive oxide (TCO), in particular indium tin oxide (ITO), and / or a conductive polymer.

The contact layer can be deposited, for example, directly on the semiconductor body. Alternatively, it may for example be applied to a carrier foil and subsequently laminated onto the semiconductor body. If the contact layer is, for example, a conductive polymer, the contact layer itself can be a film and in particular be laminated onto the semiconductor body. These process steps are described, for example, in the document DE 103 39 985 A1, the disclosure content of which is hereby incorporated by reference.

In an expedient embodiment, a first electrically insulating layer is applied to at least part of the connection region of the carrier substrate prior to the formation of the contact layer. This is especially true at an electrically conductive carrier substrate in order not to electrically short the semiconductor layer stack.

If the contact layer is pulled over a side surface of the semiconductor layer stack onto the connection region of the carrier substrate, then a second electrically insulating layer is applied to this side surface, preferably at least in the region of the contact layer.

The first and / or the second electrically insulating layer may, for example, comprise a silicon oxide and / or a silicon nitride, such as SiO ₂ , SiN or SiO _x N ₇ . It can also be a plastic or polymer layer. Preferably, it is then laminated or sprayed on. If the contact layer is applied to a carrier foil or if the contact layer is a foil, the first and / or the second electrically insulating layer can also be applied to these. Then, the first and / or second electrically insulating layer is preferably applied to the semiconductor body together with the contact layer, in particular laminated. These process steps are described for example in the document DE 103 39 985 A1, the disclosure content of which is hereby incorporated by reference.

The first and the second electrically insulating layer can be produced in one piece, for example, by pulling the second electrically insulating layer from a side surface of the semiconductor layer stack as a first electrically insulating layer onto the connection region of the carrier substrate. This is particularly useful if, for example, the contact layer is applied to a carrier foil or represents a foil. In a further embodiment, a first and / or a second electrical connection layer, for example a bonding pad, is formed on the connection region of the carrier substrate. In particular, the first and / or second electrical connection layer comprises a metal. For example, the first and / or second electrical connection layer comprises or consists of at least one of the following materials: AuSn, PdIn, Sn, Au, Al, Bi.

In this case, the first electrical connection layer is preferably arranged on the contact layer and is in this way electrically conductively connected to the front side of the semiconductor layer stack.

The second electrical connection layer is preferably electrically conductively connected to the rear side of the semiconductor layer stack facing the carrier substrate.

If the carrier substrate wafer is electrically sufficiently conductive, it can be arranged directly on the carrier substrate for this purpose and the carrier substrate can act as an electrical connection between the second connection layer and the back side of the semiconductor layer stack. The second connection layer can thereby on the

Semiconductor layer stack facing front or on the side facing away from the semiconductor layer stack rear side of the carrier substrate are applied.

In the case of a carrier substrate wafer which is not sufficiently electrically conductive, a sufficiently electrically conductive layer is preferably arranged between the latter and the semiconductor layer sequence, which layer forms the connection region of the Trägerubstratwafers at least partially covered and on which then the second connection layer is formed.

In this case, the electrically conductive layer is preferably applied before the connection of the semiconductor layer sequence to the carrier substrate wafer. It can be applied, for example, structured or structured after application.

If a structurally structured connection is produced in the method, the electrically conductive layer is expediently applied to the carrier substrate wafer.

If a full-surface connection is first produced, the electrically conductive layer can be applied both to the semiconductor layer sequence and to the carrier substrate wafer. Expediently, the part of the electrically conductive layer arranged on the connection region of the carrier substrate is uncovered when the connection between the semiconductor layer sequence and the carrier substrate wafer is partially released. If a sacrificial layer is present, the electrically conductive layer preferably adjoins it.

If the semiconductor layer stack has a first partial region which projects beyond the edge of the carrier substrate perpendicular to the growth direction, ie, does not overlap with the carrier substrate, the second electrical connection layer can alternatively be formed on the rear side of this first partial region of the semiconductor layer stack. In this case, for example, an electrically insulating or not sufficiently conductive Carrier substrate - extend the second electrical connection layer on the back of the carrier substrate and cover these partially or completely. Advantageously, the semiconductor body can thus be installed and contacted in conventional device housings in a simple manner, for example by means of conventional die-bonding methods, even in the case of an electrically insulating carrier substrate.

In one embodiment of the method, the semiconductor layer sequence comprises a growth substrate wafer. This may be, for example, a bulk substrate wafer (= wafer made of a uniform material, preferably a semiconductor material), or a quasi-substrate wafer, which comprises, for example, a carrier and a layer of a semiconductor material applied thereto. The remaining layers of the semiconductor layer sequence are preferably grown epitaxially on the growth substrate wafer. In an embodiment, it can be provided that the growth substrate wafer is thinned or removed before or after the connection of the semiconductor layer sequence with the carrier substrate wafer.

In one embodiment, the semiconductor layer sequence is based on a III / V compound semiconductor material, for example, a nitride compound semiconductor material or a phosphide compound semiconductor material. In another embodiment, the semiconductor layer sequence is based on a II / VI compound semiconductor material.

An IIl / V compound semiconductor material comprises at least one element of the third main group such as Al, Ga, In, and a fifth main group element such as for example, B, N, P, As. In particular, the term "III / V compound semiconductor material" means the group of binary, ternary or quaternary compounds containing at least one element from the third main group and at least one element from the fifth main group, in particular nitride and phosphide compound semiconductors. Such a binary, ternary or quaternary compound may additionally have, for example, one or more dopants and additional constituents.

Accordingly, an II / VI compound semiconductor material has at least one element of the second main group such as Be, Mg, Ca, Sr, and a sixth main group element such as O, S, Se. In particular, an IL / VI compound semiconductor material comprises a binary, ternary or quaternary compound comprising at least one element from the second main group and at least one element from the sixth main group. Such a binary, ternary or quaternary compound may additionally have, for example, one or more dopants and additional constituents. For example, the II / VI compound semiconductor materials include: ZnO, ZnMgO, CdS, ZnCdS, MgBeO.

"Based on nitride compound semiconductor material" in the present context means that the

Semiconductor layer sequence or at least a part thereof, more preferably at least the active zone and / or the growth substrate wafer, a nitride compound semiconductor material, preferably Al _n Ga _m In _{1 nm} N or consists of this, where 0 <n <1, O ≤ m ≤ l and n + m <1. In this case, this material does not necessarily have a mathematically exact composition according to the above formula exhibit. Rather, it may, for example, have one or more dopants and additional constituents. For the sake of simplicity, however, the above formula contains only the essential constituents of the crystal lattice (Al, Ga, In, N), even if these can be partially replaced and / or supplemented by small amounts of further substances.

"On phosphide compound semiconductor material based" in this context means that the semiconductor layer sequence or at least part thereof, particularly preferably at least the active zone and / or the growth substrate, preferably Al _n Ga _m ini- _n -MP or As _n Ga _m In _1-nm P, where O ≦ n ≦ l, O ≦ m ≦ l and n + m <1. In this case, this material does not necessarily have to have a mathematically exact composition according to the above formula, but rather one or more dopants and additional For the sake of simplicity, however, the above formula contains only the essential constituents of the crystal lattice (Al or As, Ga, In, P), even if these may be partially replaced by small amounts of other substances.

The carrier substrate wafer preferably comprises sapphire or is sapphire. But it can also be other materials, eg. For example, semiconductor wafers, which preferably comprise or consist of GaN or SiC, can be used as carrier substrate wafers. Metal, plastic or glass plates are also suitable as carrier substrate wafers.

Preferably, at least one section through the semiconductor layer sequence and an adjacent section through the carrier substrate wafer, which delimit the or the same semiconductor body, by 50 microns or more against each other added. More preferably, they are offset by 100 microns or more against each other. In other words, the projections of these sections in the connection plane of semiconductor layer sequence and carrier substrate wafer have a spacing of greater than or equal to 50 μm, preferably greater than or equal to 100 μm.

The semiconductor body bounded by the cuts then has a connection region of the carrier substrate and / or a first subregion of the semiconductor layer stack which has an extent of greater than or equal to 50 μm, preferably greater than or equal to 100 μm, along the first and / or second offset direction.

In an advantageous embodiment, the carrier substrate is placed on a stretchable pad and the stretchable pad is stretched, so that the distances between the semiconductor bodies are increased. In other words, the semiconductor bodies are pulled apart when the extensible pad is stretched.

For example, the stretchable pad is connected to the semiconductor layer sequence. The connection between a semiconductor body, in particular the

Semiconductor layer sequence, and the stretchable pad is suitably designed so that it does not dissolve completely when stretching the stretchable pad. In other words, the semiconductor body adheres to the stretchable backing during stretching. By way of example, the adhesion between the semiconductor layer sequence and the extensible support is mediated by means of adhesion, an adhesive layer and / or a lacquer layer. In another embodiment, the semiconductor layer sequence is clamped between two stretchable pads, for example, an expandable pad of the front and another of the back of the semiconductor layer sequence is adjacent.

The further processing of the semiconductor body is advantageously simplified in this way. At the same time, during the stretching of the extensible support, the second subregion of a semiconductor body, which may be covered by one or more semiconductor layer stacks of adjacent semiconductor bodies before the semiconductor bodies are pulled apart, is at least partially exposed. The semiconductor bodies can then be removed individually from the extensible support in a simple manner.

The stretching of the extensible pad takes place substantially parallel to the connection plane between the semiconductor layer sequence and the carrier substrate wafer.

Depending on the arrangement of the cuts through the

Semiconductor layer sequence and by the carrier substrate wafer, it may be sufficient to stretch the stretchable pad only in one direction. However, it may also be advantageous-in particular if the semiconductor layer stack of a semiconductor body protrudes beyond the respectively associated carrier substrate in more than one offset direction-to stretch the extensible underlay in several directions, for example in two mutually perpendicular directions. For example, the strain may be substantially isotropic in the main plane of extension of the stretchable pad.

In one embodiment, the stretchable pad comprises a film, such as polyethylene. In a variant is the film on its side facing the semiconductor layer sequence side coated with adhesive. In another embodiment, the stretchable pad has or consists of an expanded metal mesh.

In an expanded metal is usually a lattice-like material whose extensibility is particularly increased by the fact that meshes are formed. It may be an expanded metal to a metal ("expanded metal"), but it can for example also be made of a plastic. An expanded metal mesh can be formed for example by punching or staggered cuts in a material, wherein preferably no material loss occurs and the material is deformed stretching.

Advantageously, in addition to its extensibility, an expanded metal has a high dimensional stability, in particular in the direction perpendicular to the plane in which the expansion takes place. In addition, the extensibility of a stretched grid can be adjusted selectively by means of suitable design of the grid structure along specific spatial directions, so that the size and direction of the elongation can be adjusted in accordance with the sections through the semiconductor layer sequence and through the carrier substrate wafer.

A radiation-emitting semiconductor body according to the invention comprises a carrier substrate and a semiconductor layer stack which is suitable for generating electromagnetic radiation, wherein

- The semiconductor layer stack is at least partially disposed over a first region of the carrier substrate, such that a connection region of the carrier substrate free from the Semiconductor layer stack is; and

- In which a first portion of the semiconductor layer stack protrudes beyond the edge of the carrier substrate.

In other words, only a second subregion of the semiconductor layer stack overlaps with the carrier substrate. The first subregion of the semiconductor layer stack is arranged in a plan view of the semiconductor layer stack, that is to say on the surface of the semiconductor layer stack facing away from the carrier substrate, next to the carrier substrate. The first subregion of the semiconductor layer stack thus represents an overhang relative to the carrier substrate.

In a particularly preferred embodiment, those areas of the semiconductor layer stack and the carrier substrate which are substantially parallel to the connection plane have substantially the same extent.

The semiconductor layer stack and the carrier substrate thus preferably have the same edge lengths in the main extension plane. However, each adjacent side surfaces are not flush with each other in each case, but offset from each other. In other words, the semiconductor layer stack and the carrier substrate are not congruent in plan view of the surface of the semiconductor layer stack facing away from the carrier substrate. Instead, the semiconductor layer stack projects beyond at least one offset direction beyond at least one side surface of the carrier substrate, so that the first subregion of the semiconductor layer stack forms an overhang relative to the carrier substrate. In a preferred embodiment, a preferably at least partially radiation-permeable contact layer is applied to the semiconductor body, which covers at least in part a surface of the semiconductor layer stack facing away from the carrier substrate and at least a part of the connection region of the carrier substrate. In any case, the contact layer preferably covers substantially the entire surface of the semiconductor layer stack facing away from the carrier substrate.

In a preferred embodiment, the contact layer is drawn from the front side of the semiconductor layer stack over at least one side surface onto the connection region of the carrier substrate. The contact layer thus preferably also covers at least one side surface of the semiconductor layer stack at least partially.

The contact layer can be designed in several parts. For example, it is possible for a partial region of the contact layer, which is also arranged in particular on the front side of the semiconductor layer stack, to have a material that is at least partially transmissive to electromagnetic radiation, while another partial region is substantially radiopaque. Conveniently, subregions of the contact layer adjoin one another or overlap, so that they are electrically conductively connected.

The contact layer or a partial region of the contact layer preferably contains or consists of a transparent conductive oxide (TCO), for example indium tin oxide (ITO), and / or a conductive polymer, or consists of one of these materials. In a preferred embodiment, a first electrically insulating ^■ coating is applied to the connection region of the carrier substrate between the carrier substrate and the contact layer, which covers the connection region of the carrier substrate at least in places. The first electrically insulating layer may, for example, prevent a short circuit of the semiconductor layer stack via a conductive carrier substrate and the contact layer.

If the contact layer also extends over a side surface of the semiconductor layer stack, a second electrically insulating layer is preferably applied to the side surface of the semiconductor layer stack, covering the side surface partially or completely, in particular in the region of the contact layer. Particularly preferably, the first electrically insulating layer arranged on the carrier substrate wafer also extends as a second electrically insulating layer onto the side surface of the semiconductor layer stack.

A first electrical connection layer or the first and a second electrical connection layer can be arranged on the connection region of the carrier substrate. The first electrical connection layer is electrically conductively connected to the front side of the semiconductor layer stack and is preferably arranged on the contact layer. The second electrical connection layer is connected in an electrically conductive manner to the rear side of the semiconductor layer stack. For example, a connection wire may be fastened to the first and / or the second electrical connection layer via which the semiconductor body is supplied with the electrical current necessary for its operation. The arrangement of an electrical connection layer, such as a bond pad, on the front side of the semiconductor layer stack facing away from the carrier substrate is advantageously not necessary. Lead wires also do not need to be routed over the front of the semiconductor layer stack.

The surface through which radiation is coupled out of the semiconductor body is therefore advantageously not reduced by a radiation-absorbing connection layer. In addition, in the case of a semiconductor body according to the invention, an optical element arranged downstream of the front side of the semiconductor layer stack can be arranged particularly close to the front side, if no connection wire is guided over it.

The second electrical connection layer is preferably arranged on the rear side of the first subregion of the semiconductor layer stack facing the front side and particularly preferably also extends to the rear side of the carrier substrate facing away from the semiconductor layer stack, in particular if, for example, the carrier substrate is not sufficiently electrically conductive.

The semiconductor layer stack can thus be electrically contacted in a simple manner. For example, in this embodiment it is not necessary to structure the connection region of the carrier substrate in its main extension plane into a plurality of regions which are electrically separated from one another in order to apply the first and the second electrical contact surface. In an expedient embodiment of the semiconductor body, the semiconductor layer stack comprises a growth substrate on which the remaining layers of the semiconductor layer stack are preferably epitaxially grown.

The growth substrate may be a bulk substrate or a quasi-substrate. As a rule, a bulk substrate consists of a uniform material, for example a semiconductor material, which is well suited for growing a semiconductor layer sequence from the materials of the semiconductor layer stack. A quasi-substrate comprises, for example, a carrier and a thin layer of such material applied thereto.

The semiconductor layer stack is preferably based on a III / V compound semiconductor material, in particular a phosphide or nitride compound semiconductor material, or on an II / VI compound semiconductor material. The carrier substrate preferably comprises sapphire or is sapphire.

Preferably, the contact layer is at least partially transparent to the electromagnetic radiation generated by the semiconductor layer stack during operation. It may for example consist of a transparent, conductive oxide, in particular indium tin oxide (ITO), or comprise such a material.

In a particularly preferred embodiment, an edge of the connection region of the carrier substrate against an adjacent side surface of the semiconductor layer stack is in plan view of the front side of the semiconductor layer stack by 50 microns or more, more preferably by 100 microns or more, added.

In other words, the extent of the connection region of the carrier substrate in at least one offset direction is greater than or equal to 50 μm, in particular greater than or equal to 100 μm.

In another embodiment, a side surface of the first portion of the semiconductor layer stack and an adjacent edge of the carrier substrate offset by 50 microns or more against each other.

Analogously to the connection region of the carrier substrate, the first subregion of the semiconductor layer stack thus has an extension which is greater than or equal to 50 μm in at least one offset direction.

A cavity, which is delimited by the first subregion of the semiconductor layer stack, the carrier substrate and by a planar base, is at least partially filled with a filling material according to a further embodiment.

In other words, the space which is arranged under the overhang formed by the first subregion of the semiconductor layer stack is at least partially filled with a filling material. As a result, on the side of the carrier substrate which is remote from the semiconductor layer stack, an enlarged, essentially planar, positioning surface is advantageously formed by the carrier substrate and the filling material. Particularly preferably, the entire cavity is filled with filling material. In this way, on the one hand advantageously the mechanical stability and / or the stability of the semiconductor body is increased. On the other hand, such a filler material may optionally protect a second electrical connection layer applied on the rear side of the first subregion of the semiconductor layer stack and / or a connection wire fastened thereto from mechanical damage.

The filler material may be, for example, an epoxy resin, a polychlorinated biphenyl (PCB) or bis-benzo-cyclobutene (BCB). The filling material is particularly preferably thermally adapted to the expansion coefficient of the carrier substrate and / or the semiconductor layer stack.

Further advantages and advantageous embodiments and developments of the invention will become apparent from the embodiments described below in connection with Figures IA to 6E.

Show it:

Figures IA to IG ₇ are schematic sectional illustration of an optoelectronic semiconductor body at different stages of the first embodiment of a method according to the invention,

FIGS. 2A and 2B show schematic top views of a plurality of optoelectronic semiconductor bodies in the stages of the method illustrated in FIGS. FIGS. 3A and 3B show schematic sectional representations of an optoelectronic semiconductor body at various stages of the second exemplary embodiment of a method according to the invention,

FIGS. 4A and 4B show a schematic sectional representation and a schematic plan view, respectively, of an optoelectronic semiconductor body according to the invention, which is produced according to a third exemplary embodiment of a method according to the invention,

FIG. 5, a schematic plan view of an optoelectronic semiconductor body according to the invention, which is produced according to a fourth exemplary embodiment of a method according to the invention,

Figures 6A to 6E, schematic plan views of differently designed embodiments of optoelectronic semiconductor bodies according to the invention.

In the exemplary embodiments and figures, identical or identically acting components are each provided with the same reference numerals. The elements shown and their proportions with each other are basically not to be regarded as true to scale, but individual elements such. As layers, for better presentation and / or better understanding to be shown exaggerated.

In the exemplary embodiment of the method according to the invention illustrated in FIGS. 1A to 1C for producing a plurality of radiation-emitting semiconductor bodies, a semiconductor layer sequence 2 is formed which generates electromagnetic radiation during operation (see Fig. IA).

The semiconductor layer sequence 2 is based for example on GaN or another nitride compound semiconductor material and comprises a growth substrate wafer 3, on which the remaining layers of the semiconductor layer sequence 2 are epitaxially deposited. The epitaxial deposition takes place for example by means of chemical vapor deposition (CVD) or physical vapor deposition (PVD) or other suitable epitaxial deposition methods.

In the present case, the semiconductor layer sequence 2 is suitable for emitting light and preferably comprises a pn junction, a double heterostructure, a single quantum well or particularly preferably a multiple quantum well structure (MQW) for generating radiation. The term quantum well structure does not contain any information about the dimensionality of the quantization. It thus includes u. a. Quantum wells, quantum wires and quantum dots and any combination of these structures. Examples of MQW structures are described in the publications WO 01/39282, US 5,831,277, US 6,172,382 Bl and US 5,684,309, the disclosure content of which is hereby incorporated by reference.

The decoupling of the radiation generated during operation of the semiconductor body takes place in the present case essentially through the front 201 of the semiconductor layer sequence 2 facing away from the carrier substrate wafer 1 into the overlying half space, so that the main emission direction 21 indicated by an arrow in FIG. On the surface 302 of the growth substrate wafer 3 facing away from the remaining layers of the semiconductor layer sequence 2, a sacrificial layer 4, for example of InGaN, is applied, which is partially destroyed in a later process step.

Furthermore, a carrier substrate wafer 1 is provided, which in the present case consists of sapphire. A support substrate wafer 1 made of sapphire has the advantage for the present embodiment that it is at least partially permeable to electromagnetic radiation and has a similar thermal expansion coefficient as the semiconductor layer sequence 2.

A connection between the semiconductor layer sequence 2 and the carrier substrate wafer 1 is produced by means of a connection layer 5. In the present case, the connection layer 5 is formed on the carrier substrate wafer 1. Subsequently, the growth substrate wafer 3 on the side 302 facing away from the semiconductor layer sequence 2, which is covered by the sacrificial layer 4, is connected to the connection layer 5 formed on the carrier substrate wafer 1.

In order to possibly counteract absorption in the growth substrate wafer 3 or other disadvantages of the material of the growth substrate wafer, the growth substrate wafer 3 may be thinned or completely removed before or after the connection of the semiconductor layer sequence 2 to the carrier substrate wafer 1. In particular, when the growth substrate wafer 3 is thinned or completely removed after the semiconductor layer sequence 2 has been joined to the carrier substrate wafer 1, the connection preferably takes place in such a way that the side of the semiconductor layer sequence 2 facing away from the growth substrate wafer 3 is connected to the carrier substrate wafer 1. In particular, in this case, the radiation generated by the semiconductor bodies during operation can be coupled out by the carrier substrate wafer.

The connection layer 5 in the present case consists of silicon oxide and / or silicon nitride and the connection can be made by conventional methods for connecting two wafers. However, it is also possible to use an adhesive, for example an epoxy resin, or a solder, for example a solder such as Au, AuSn, Pd, In, PdIn or Pt.

Subsequently, the semiconductor layer sequence 2 is subdivided into individual semiconductor layer stacks 200 by cuts 6 from their front side 201 facing away from the carrier substrate wafer 1 (compare FIG. 1B). The cuts 6 in the present case also sever the growth substrate wafer 3 and the sacrificial layer 4.

In the present case, the bonding layer 5 is not severed by the cuts 6 through the semiconductor layer sequence. In an expedient embodiment of the exemplary embodiment, the connection layer 5 is likewise severed by the sections 6 through the semiconductor layer sequence 2. This can bring about advantages, for example, in the subsequent partial release of the connection between growth substrate wafer 3 and carrier substrate wafer 1. Depending on the depth of the cuts 6 through the

Semiconductor layer sequence 2, in alternative embodiments of the method, can produce trenches in the connection layer 5 or in the carrier substrate wafer 1, without, however, completely cutting through the carrier substrate wafer 1.

The carrier substrate wafer 1 is produced by its rear side 101 facing away from the semiconductor layer sequence 2 by the sections 6 through the

Semiconductor layer sequence 2 staggered sections 7 divided into individual carrier substrates 100.

A plurality of cuts 6, 7 through the

The semiconductor layer sequence or through the carrier substrate wafer runs outside the cutting plane shown in FIG. 1B and perpendicular to the sections 6, 7 shown in FIG. 1B (see FIG. 2A), so that carrier substrates and semiconductor layer stacks with a rectangular, preferably square, base surface are formed in the present case. However, the cuts do not have to be perpendicular to one another, but can also run obliquely with respect to one another at a different angle, so that, for example, semiconductor layer stacks and / or carrier substrates can be produced which have a triangular or parallelogram-like base surface.

Adjacent sections 6 through the semiconductor layer sequence and adjacent sections 7 through the carrier substrate wafer have the same spacing according to this embodiment, so that the edge lengths of the carrier substrates 100 and the semiconductor layer stack 200 in the main extension plane are identical. If semiconductor bodies with different dimensions are to be produced, then the intersection distances over the wafer can also vary.

In the present case, the cuts 7 through the carrier substrate wafer 1 also sever the connecting layer 5, but not the sacrificial layer 4. In an expedient embodiment of the exemplary embodiment, the sacrificial layer 4 is also severed by the cuts 7 through the carrier substrate wafer 1. This can bring advantages, for example, in the subsequent partial decomposition of the sacrificial layer 4.

Depending on the depth of the cuts 7 through the carrier substrate wafer 1, in alternative embodiments of the method, they can form trenches in the sacrificial layer 4 or, with the sacrificial layer 4 being severed, in the growth substrate wafer 3, or by severing the sacrificial layer 4 and

Create growth substrate wafer 3, in one of the remaining layers of the semiconductor layer sequence 2, but without completely cut through the semiconductor layer sequence 2.

In the present case, the cuts 6 through the semiconductor layer sequence and the cuts 7 through the carrier substrate wafer 1 are arranged so that none of the regions which would be occupied by an imaginary continuation of a cut 7 through the carrier substrate wafer 1 to the front side 201 of the semiconductor layer sequence 2, one of the cuts 6th completely contained by the semiconductor layer sequence 2.

In other words, none of the cuts 6 through the semiconductor layer sequence 2 represents the extension of a cut 7 by the carrier substrate wafer 1 Positions at which a section 7 intersects through the carrier substrate wafer 1 and a section 6 through the semiconductor layer sequence 2, which are not arranged parallel to one another, results in a quasi one-dimensional region 24 (see FIG. 2A) in which both the semiconductor layer sequence 2 as well as the carrier substrate wafer 1 are severed.

As illustrated in FIG. 1C, the sacrificial layer 4 is subsequently irradiated with laser radiation (indicated by the arrows 9) through a mask 8, the carrier substrate wafer 1 and the connection layer 5. The irradiation may alternatively be before dividing the

Semiconductor layer sequence 2 and / or the carrier substrate wafer 1 done.

The mask 8 is chosen so that at each

Semiconductor layer stack 200, a first portion 210, which is to be detached from the carrier substrate wafer 1, is irradiated, while a second portion 220 is shaded. The second subareas 220 not provided for irradiation are selected such that each of the carrier substrates 100 is still connected to exactly one of the semiconductor layer stacks 200 after the region-wise release of the connection between semiconductor layer stack 200 and carrier substrates 100.

The sacrificial layer 4 absorbs part of the laser radiation 9 and is decomposed at the irradiated sites. Such a laser separation method is described for example in the document WO 98/14986 A1, the disclosure content of which is hereby incorporated by reference. After irradiation with the laser radiation 9, in each case one semiconductor layer stack 200 is connected to exactly one carrier substrate 100. The connection of a semiconductor layer stack 200 with one or more further carrier substrates 100, which are arranged at least partially below the semiconductor layer stack 200, is achieved by the destruction of the sacrificial layer 4. A semiconductor layer stack 200 and its associated carrier substrate 100 together form a semiconductor body 10.

Areas 20 of the carrier substrate wafer 1 and regions of the semiconductor layer sequence 2 including growth substrate wafer 3, etc., which are not part of semiconductor bodies 10 after the cuts 6 and 7 have been produced, can be easily removed in a further method step.

Before the final singulation of the composite of semiconductor layer sequence 2, growth substrate wafer 3 and carrier substrate wafer 1, the carrier substrate wafer 1 subdivided into individual carrier substrates 100 is connected to an extensible support 11 (see FIG. ID). For example, the stretchable pad 11 is a film comprising or consisting of polyethylene or composed of another suitable material. Alternatively, a stretched mesh is used as the stretchable backing 11.

The connection between the extensible pad 11 and the carrier substrate wafer 1 is performed so mechanically stable that it remains at least so far during the subsequent stretching of the pad that the semiconductor body 10 remain connected to the stretchable pad 11. The connection of the carrier substrates 100 with the stretchable pad 11 dissolves so at least not completely, if the latter is stretched. For example, an adhesive or varnish layer is disposed between the semiconductor bodies 10 and the stretchable pad 11 which provides adhesion therebetween.

In the method according to this exemplary embodiment, the carrier substrate wafer 1 is preferably applied to the stretchable underlay 11 already after being subdivided into carrier substrates 100 and before the cuts 6 are carried out by the semiconductor layer sequence 2. It is also conceivable that this takes place only after the formation of the cuts 6 through the semiconductor layer sequence 2.

By stretching the extensible support 11 in its main extension plane, the semiconductor bodies 10 are pulled apart so far apart (compare FIG. IE) that adjacent semiconductor bodies 10 no longer overlap and can therefore be removed individually from the extensible support 11.

In an alternative embodiment of this embodiment, the stretchable pad 11 is bonded to the front side 201 of the semiconductor layer sequence 2 and subsequently the cuts 7 are made through the carrier substrate wafer 1 before the stretchable pad 11 is then pulled apart.

By pulling apart the semiconductor bodies 10, the terminal regions 120 of the carrier substrates 100, which are no longer connected to the semiconductor layer stack 200 of the semiconductor body 10, are exposed. These terminal areas 120 overlap before being pulled apart the semiconductor body 10 with semiconductor layer stacks 200, which belong to adjacent semiconductor bodies 10.

At the same time, back sides 212 of the first partial regions 210 of the semiconductor layer stacks 200 are exposed. The back 212 of the first portion 210 of a

Semiconductor layer stack 200 forms an overhang with respect to the associated carrier substrate 100 and, together with this and the expandable support 11, defines a cavity 12.

After the stretchable pad 11 has been pulled apart, the semiconductor bodies 10 are removed from the stretchable pad 11 in a simple manner and in any order for further method steps. However, they can also remain on the extensible support for further process steps, such as coating with a material containing phosphor and / or diffuser particles.

FIGS. 2A and 2B show the semiconductor bodies 10 arranged on the extensible support 11 before or after the separation and pulling apart of the extensible support 11 in plan view.

FIG. 2B clearly shows how a first region 110 of each carrier substrate 100 belonging to a semiconductor body 10 overlaps with the associated semiconductor layer stack 200, while a connection region 120 of the carrier substrate 100 comes to lie next to the associated semiconductor layer stack 200.

A first subregion 210 of each semiconductor layer stack 200 protrudes in a first offset direction 22 and in a second offset direction 23 beyond the associated carrier substrate 100 addition. A second subregion 220 of the semiconductor layer stack 200 overlaps with the first region 110 of the carrier substrate 100.

After the extensible support 11 has been pulled apart, a first electrically insulating layer 13a is applied to at least part of the connection region 120 of the carrier substrate 100 of the semiconductor body 10, which also extends over a side surface 221 of the semiconductor layer stack 200 as a second electrically insulating layer 13b (compare FIG FIG. IF). In the present case, the first and second electrically insulating layers 13a, 13b are made of silicon dioxide.

Subsequently, a contact layer 14, which consists for example of indium tin oxide (ITO), is applied to the front side 201 of the semiconductor layer stack 2OO, which extends on the electrically insulating layer 13b and 13a at least to a part of the connection region 120 of the carrier substrate 100 ( compare Figure IF). The first and second passivation layers 13 a, 13 b prevent a short circuit of the semiconductor layer stack 200 by the contact layer 14.

Subsequently, a first electrical connection layer 15, for example a metal layer, which has in particular AuSn, is applied to the part of the contact layer 14 formed on the connection region 120 of the carrier substrate 100. A second electrical connection layer 16, for example likewise a metal layer, which in particular comprises AuSn, is applied to the rear side 212 of the first subregion 210 of the semiconductor layer stack 200 and to the rear side 101 of the carrier substrate 100 after the semiconductor body has been removed from the expandable substrate has been. The semiconductor body can thus advantageously be installed in conventional component packages by means of conventional die-bonding methods.

Via the first electrical connection layer 15 and the second electrical connection layer 16, an electrical current can be impressed into the semiconductor body 10. For this purpose, for example, a connection wire 17 can be attached to the first electrical connection layer 15, via which the semiconductor body operating current can be supplied (see Figure IG).

The cavity 12 under the overhang 210 may, for example, be at least partially filled with a filling compound 18 such as an epoxy resin or BCB. In the present case, this space 12 is practically completely filled with filling compound 18 so that its underside facing away from the semiconductor layer stack 200 together with the rear side 101 of the carrier substrate 100 or together with the second electrical connection layer 16 arranged thereon forms a positioning surface of the semiconductor body 10. The stability of the semiconductor body 10 can be increased.

According to the exemplary embodiment illustrated in FIGS. 3A and 3B, a carrier substrate wafer 1 and a semiconductor layer sequence 2, which generates electromagnetic radiation during operation and which comprises a growth substrate wafer 3 onto which the remaining layers of the semiconductor layer sequence 2, are analogously to the exemplary embodiment according to FIGS epitaxially grown. Subsequently, a structured connection layer 5 is applied to the carrier substrate wafer 1. Through a mask, a solder such as Au, AuSn, -Pd, In, PdIn or Pt is applied as a structured compound layer 5.

Alternatively, the connecting layer 5 can be applied to the rear side 302 of the composite of growth substrate 3 opposite the front side 201, the remaining layers of the semiconductor layer sequence 2 and optionally. be applied to further layers.

It is also possible to apply an unstructured connection layer 5, which is subsequently structured, for example by means of an etching process.

The rear side 302 and the carrier substrate wafer 1 are subsequently brought together and heated so that the solder melts and the solder layer produces a structured, mechanically stable connection between the carrier substrate wafer 1 and the semiconductor layer sequence 2.

Instead of a soldering metal, it is also possible to use an adhesive, for example an epoxy resin, for producing the structured bonding layer 5. Depending on its properties, heating of the bonding layer 5 can optionally be omitted or replaced or supplemented by another process step, for example for hardening.

Subsequently, similar to the embodiment described above first, sections 6 are performed by the semiconductor layer sequence 2 and sections 7 by the carrier substrate wafer 1. These cuts 6, 7 subdivide the semiconductor layer sequence 2 into individual semiconductor layer stacks 200 and the carrier substrate wafer 1 into individual carrier substrates 100 (compare FIG. 3B ^' ).

The structured connection layer 5 is designed such that each semiconductor layer stack 200 is connected to exactly one carrier substrate 100, so that individual semiconductor bodies 10 are formed. After the subdivision into individual carrier substrates 100, the carrier substrate wafer 1 is arranged on a stretchable base 11, preferably before the subdivision of the semiconductor layer sequence by the cuts 6. This and the further method steps are analogous to the exemplary embodiment according to FIGS.

In an optoelectronic semiconductor body produced according to the third exemplary embodiment of the method (compare FIG. 4A), the second electrical contact surface 16 is not arranged on the rear side 212 of a first region 210 of the semiconductor layer stack 200, as in the embodiment shown in FIGS. Instead, between the growth substrate 3 and the carrier substrate 100, an electrically conductive layer 19 is arranged, which covers a part of the connection region 120 of the carrier substrate 100, which is free of the semiconductor layer stack 200. On this conductive layer 19, a second electrical connection layer 16 is applied.

On the other hand, the contact layer 14 is formed according to the first-described embodiment according to FIGS. IF and IG.

In the present case, it is an electrically non-conductive carrier substrate 100, for example of sapphire. Therefore, the contact layer 14 is applied directly to the connection region 120 of the carrier substrate 100, without a first between them

Passivation layer 13a is located. On a side surface 221 of the semiconductor layer stack 200, a second passivation layer 13 b is arranged in order to avoid an electrical short circuit of the semiconductor layer stack through the contact layer 14.

The first and second electrical connection layers 15, 16 do not need to be arranged on different sides of the semiconductor layer stack 200, as shown in FIGS. 4A and 4B. An arrangement according to the semiconductor body according to FIG. 5, in which both electrical connection layers 15, 16 are adjacent to one another next to the same side surface 221 of the semiconductor layer stack 200, is particularly expedient and advantageous if the semiconductor layer stack 200 is over the edge on the side opposite the side surface 221 of the carrier substrate 100 projects and has an overhang 210 with respect to the adjacent end face of the carrier substrate.

If the carrier substrate 100 and the growth substrate 3 are electrically conductive, the second electrical connection layer 16 can be applied directly to the carrier substrate 100; otherwise, a conductive layer 19 similar to the embodiment shown in FIG. 4A may be provided, which is disposed between the semiconductor layer stack 200 and the carrier substrate 100 and pulled onto the connection region 120 of the carrier substrate 100 so that the second electrical connection layer 16 can be placed thereon , If the carrier substrate 100 is electrically conductive or should the contact layer 14 also be applied to the conductive layer 19, analogously to the exemplary embodiment of FIG. IF, it must be between the contact layer 14 and the conductive layer 19 or the conductive carrier substrate

100 a first electrically insulating layer 13a are arranged.

FIGS. 6A to 6E show various examples of the arrangement of the semiconductor layer stack 200 on the carrier substrate 100.

According to the exemplary embodiment according to FIG. 6A, the semiconductor layer stack 200 and the carrier substrate 100 have a plan view of the front side 201 of FIG

Semiconductor layer stack 200 has a rectangular shape with side lengths Ii and I ₂ or I ₃ and I ₄ . The side lengths of the semiconductor layer stack 200 and the carrier substrate 100 are practically the same in the present case, ie Ii = l3 and I ₂ = I ₄ .

The short sides 211 and 221 of the semiconductor layer stack 200 are parallel to the short sides 111, 121 of the carrier substrate 100, that is arranged offset. On the other hand, the two adjacent long sides of semiconductor layer stack 200 and carrier substrate 100 each lie in a common plane. The semiconductor layer stack 200 consequently projects beyond a side 111 of the carrier substrate 100 on a short side of the semiconductor body 10 (in the offset direction 22).

The side surface 211 of the first portion 210 of the semiconductor layer stack 200, which projects beyond the carrier substrate 100, thereby has from the adjacent side surface 111 of the first region 110 of the carrier substrate 100, which is covered by the semiconductor layer stack 200, a distance d, which is greater than 50 microns in the present case.

Correspondingly, the side surface 121 of the connection region 120 of the carrier substrate 100 has a distance a from the adjacent side surface 221 of the semiconductor layer stack 200 which in the present case assumes the same value as the abovementioned distance d.

The side surfaces of the semiconductor layer stack 200 and the carrier substrate 100, which are parallel to the plane defined by the offset direction 22 and the growth direction 21, ie, the sides having the lengths I ₁ and I ₃ , are not offset from each other.

In the method according to the invention for producing a plurality of radiation-emitting semiconductor bodies, therefore, one section 6 is not offset from one another by the semiconductor layer sequence 2 and a section 7 passes through the carrier substrate wafer 7, which run parallel to this plane, and form a common section through the semiconductor body 10. This completely cuts through the semiconductor body 10 along the growth direction 21.

According to the exemplary embodiment of FIG. 6B, the semiconductor layer stack 200 does not protrude beyond a lateral surface of the carrier substrate 100 in a first offset direction 22. Rather, the semiconductor layer stack is shifted diagonally relative to the carrier substrate 100. In the present case, the distance d between each side face 211 of the first subregion 210 of the semiconductor layer stack 200 is from the respectively adjacent one Side surface 111 of the first portion 110 of the support substrate 100 of the same size. Alternatively, the distance d along the first offset direction 22 may be larger or smaller than the distance along the second offset direction 23. There is then no exact diagonal offset.

As in the exemplary embodiment according to FIG. 6A, the distance a of a side surface 121 of the connection region 120 of the carrier substrate 100 from the respectively adjacent side surface 221 of the second subregion 220 of the semiconductor layer stack 200 corresponds to the above-mentioned distance d.

The semiconductor layer stack 200 and the carrier substrate 100 need not have the same dimensions along the main extension directions of the carrier substrate. The exemplary embodiment of FIG. 6C shows an example of a semiconductor layer stack 200, which has a smaller length I ₁ than the associated carrier substrate 100, which has a length I ₃ > Ii. In the present exemplary embodiment, the semiconductor layer stack 200 has a width I ₂ which is greater than the width I _{4 of} the associated carrier substrate 100.

The semiconductor layer stack 200 is arranged so that the centers of the semiconductor layer stack 200 and the carrier substrate 100, in plan view of the

Semiconductor layer stack 200 seen, are stacked. The connection region 120 of the carrier substrate 100 projects longitudinally beyond the semiconductor layer stack 200. The electrical connection layers 15 and 16 can then be arranged as shown in FIGS. 4A and 4B, respectively. Along the width, the first portion 210 of the semiconductor layer stack 200 protrudes beyond the carrier substrate and represents an overhang 210. Alternatively, one or two side surfaces of the semiconductor layer stack 200 and the carrier substrate 100 may be arranged flush with each other.

According to the exemplary embodiment illustrated in FIG. 6D, the semiconductor layer sequence 200, viewed in plan view of the semiconductor layer stack 200, has a circular cross section. It is arranged on a square carrier substrate 100 and offset along an edge of this carrier substrate 100 such that it has a first subregion 210 whose side surface 211 has a maximum distance d from the adjacent side surface 111 of the carrier substrate 100. With such a semiconductor body, improved light extraction can be achieved.

During the production of such semiconductor bodies, parts of the semiconductor layer sequence 2 remain as a waste between the semiconductor layer stacks 200, which are expediently removed.

The side surfaces of the carrier substrate 100 in the case of the semiconductor body according to the exemplary embodiment of FIG. 6E have, for example, recesses 12 on two opposite sides 111. These recesses 12 extend over the entire thickness of the carrier substrate 100 and have, for example, a width which corresponds to approximately half the side length. In the region of these recesses 12, a first subregion 210 of the semiconductor layer stack projects beyond the adjacent edge of the carrier substrate and in each case represents an overhang 210, which is predetermined by the shape of the recesses 12 and has a depth d. In the present case, the recesses 12 have a rectangular Cross-section. But they can also be formed with a semicircular, triangular or Trapezartigem cross-section.

The remaining side surfaces of the carrier substrate have, with respect to the semiconductor layer stack 200, protrusions 120 which preferably have the same dimensions as the recesses 12. If the protrusions 120 and the recesses 12 have the same dimensions, the cuts 6, 7 can be produced in the production of a plurality of such semiconductor bodies 10 be guided so that the projections 120 of a semiconductor body 10 in the recesses 12 of adjacent semiconductor body 10 are located. Adjacent carrier substrates 100 then engage in one another similar to puzzle pieces, and between adjacent semiconductor layer stacks 200 there advantageously does not arise a waste of the semiconductor layer sequence.

The projections 120 each have a depth a and represent the connection region 120 of the carrier substrate 100, which is free of the semiconductor layer stack 200 and can be arranged on the electrical electrical contact surfaces 15, 16. The arrangement can take place, for example, as shown in FIGS. 4A and 4B. An arrangement of the second electrical contact surface 16 on the rear side 212 of the semiconductor layer stack 200 in the region of one of the overhangs 210, as shown in the illustrations IF and IG, is alternatively also possible.

In the case of the semiconductor body 10 according to the exemplary embodiment of FIG. 6E, there is no edge of the carrier substrate 100, beyond which the semiconductor layer stack 200 protrudes at all points. The semiconductor body 10 therefore advantageously has a high stability. Nevertheless, a plurality of such semiconductor bodies 10 can be produced according to one of the methods according to the invention without parts of the semiconductor layer sequence 2 or of the carrier substrate wafer 1 remaining unused and having to be removed between the semiconductor bodies 10.

The invention is not limited by the description based on the embodiments of these. Rather, the invention encompasses any novel feature as well as any combination of features, including in particular any combination of features in the claims, even if this feature or combination itself is not explicitly stated in the patent claims or exemplary embodiments.

This patent application claims the priorities of German patent applications 102006020537.5 and 102006033502.3, the disclosure of which is hereby incorporated by reference.

Claims

claims

1. A method for producing a plurality of radiation-emitting semiconductor bodies with carrier substrate, comprising the steps:

- providing a carrier substrate wafer (1);

- Producing a semiconductor layer sequence (2), which is adapted to generate electromagnetic radiation;

- Producing a structured connection of the semiconductor layer sequence with the carrier substrate wafer;

- dividing the semiconductor layer sequence (2) into a plurality of semiconductor layer stacks (200) by means of cuts (6) through the semiconductor layer sequence (2);

- dividing the carrier substrate wafer (1) into a plurality of carrier substrates (100) with cuts (7) through the carrier substrate wafer (1); and

- Separating the semiconductor layer stack (200) with the associated carrier substrates (100) to individual semiconductor bodies (10), wherein

- The structured connection is carried out such that at least one semiconductor layer stack (200) is connected to exactly one associated carrier substrate (100); and

at least one section through the carrier substrate wafer of any of the cuts through the

Semiconductor layer sequence is extended such that there is a straight cut through the carrier substrate wafer and the semiconductor layer sequence.

2. A method for producing a plurality of radiation-emitting semiconductor bodies according to claim 1, wherein the production of the structured connection comprises the formation of a full-surface connection between the carrier substrate wafer (1) and the semiconductor layer sequence (2) and a subsequent, location-wise release of the full-surface connection comprises.

3. A method for producing a plurality of radiation-emitting semiconductor bodies according to claim 2, wherein a sacrificial layer (4) is generated or identified, along which the local release of the compound takes place.

4. A method for producing a plurality of radiation-emitting semiconductor bodies according to one of claims 2 to 3, wherein the localized release of the compound by means of laser radiation (9).

5. A method for producing a plurality of radiation-emitting semiconductor bodies according to claim 1, wherein the production of the structured connection takes place in that the semiconductor layer sequence (2) is connected only in places to the carrier substrate wafer (1).

6. A method for producing a plurality of radiation-emitting semiconductor bodies according to one of the preceding claims, wherein the production of the structured connection between the carrier substrate wafer (1) and the semiconductor layer sequence (2) by means of a connection layer (5).

7. A method for producing a plurality of radiation-emitting semiconductor bodies according to claim 6, wherein in addition to the semiconductor layer sequence (2) and / or the carrier substrate wafer (1) and the connecting layer (5) is divided.

8. A method for producing a plurality of radiation-emitting semiconductor bodies according to claim 6, wherein the manufacturing of the structured connection comprises a soldering process.

9. A method for producing a plurality of radiation-emitting semiconductor bodies according to one of the preceding claims, wherein the cuts (7) through the carrier substrate wafer (1) and / or the cuts (6) through the semiconductor layer sequence (2) by a mechanical method, in particular by Sawing, or done by laser radiation.

10. A method for producing a plurality of radiation-emitting semiconductor bodies according to one of the preceding claims, in which at least one semiconductor body (10) a contact layer (14) is applied, at least partially facing away from the carrier substrate (100) front side (201) of its Semiconductor layer stack (200) and at least a portion of the terminal region (120) of the associated carrier substrate (100), which is not covered by the semiconductor layer stack (200) is covered.

11. A method for producing a plurality of radiation-emitting semiconductor bodies according to claim 10, in which the contact layer (14) also extends over at least one side face (221) of the semiconductor layer stack (200) and covers it at least partially.

12. A method for producing a plurality of radiation-emitting semiconductor bodies according to one of claims 10 to 11, wherein at least a portion of the contact layer is at least partially radiation-transmissive.

13. A method for producing a plurality of radiation-emitting Hälbleiterkörpern according to one of the preceding claims, wherein the contact layer (14) based on a transparent, conductive oxide, in particular indium tin oxide (ITO) is prepared.

14. A method for producing a plurality of radiation-emitting semiconductor bodies according to one of the preceding claims, wherein at least one semiconductor body (10) prior to forming the contact layer (14) at least on a part of the connection region (120) of the associated carrier substrate

(100) a first electrically insulating layer (13a) is applied.

15. A method for producing a plurality of radiation-emitting semiconductor bodies according to one of the preceding claims, wherein at least one semiconductor body (10) a second electrically insulating layer (13b) is applied, the at least one side surface (221) of the semiconductor layer stack (200) at least partially covered.

16. A method for producing a plurality of radiation-emitting semiconductor bodies according to one of the preceding claims, wherein at least one section (6) through the semiconductor layer sequence (2) and an adjacent section (7) through the carrier substrate wafer (1) in plan view of the front side of the semiconductor layer stack by 50 microns or more, in particular by lOOμm or more, are offset from each other.

17. A method for producing a plurality of radiation-emitting semiconductor bodies according to one of the preceding claims, wherein a first electrical connection layer (15) which is electrically conductive with the front side (201) of the

Semiconductor layer stack (200) is connected, on the connection region (120) of the carrier substrate (100) at least one semiconductor body (10), in particular on the contact layer (14) is formed.

18. A method for producing a plurality of radiation-emitting semiconductor bodies according to one of the preceding claims, in which a second electrical connection layer (16) which is electrically conductively connected to the front side (201) opposite rear side (302) of the semiconductor layer stack (200) is connected the connection region (120) of the carrier substrate (100) of at least one semiconductor body

(10) is formed.

19. A method for producing a plurality of radiation-emitting semiconductor bodies according to one of the preceding claims, wherein in at least one semiconductor body (10), the second electrical connection layer (16) on the back (212) of a first portion (210) of the semiconductor layer stack, via the Edge (111) of the associated carrier substrate (100) protrudes, is formed.

20. A method for producing a plurality of radiation-emitting semiconductor bodies according to one of the preceding claims, in which the semiconductor layer sequence (2) comprises a growth substrate wafer

(3).

21. A method for producing a plurality of radiation-emitting semiconductor bodies according to one of the preceding claims, wherein the semiconductor layer sequence (2) on a III / V compound semiconductor material, in particular a Nitride compound semiconductor material or a phosphide compound semiconductor material, or based on an II / VI compound semiconductor material.

22. A method for producing a plurality of radiation-emitting semiconductor bodies according to one of the preceding claims, in which a carrier substrate wafer (1) is provided which comprises sapphire.

23. A method for producing a plurality of radiation-emitting semiconductor bodies according to one of the preceding claims, with the steps:

- placing the carrier substrate (1) on a stretchable pad (11); and

- Stretching the stretchable pad (11), so that the semiconductor body (10) are pulled apart.

24. A method for producing a plurality of radiation-emitting semiconductor bodies according to claim 23, wherein the stretchable pad (11) comprises a film which in particular comprises polyethylene.

25. A method for producing a plurality of radiation-emitting semiconductor bodies according to claim 23 or 24, wherein the stretchable pad (11) comprises a stretched grid.

26. A method for producing a plurality of radiation-emitting semiconductor bodies according to one of the preceding claims, wherein in at least one semiconductor body (10) one of the first portion (210) of the semiconductor layer stack (200), the carrier substrate (100) and a flat base limited cavity (12) is at least partially filled with a filler material (18).

27. A radiation-emitting semiconductor body (10), comprising a carrier substrate (100) and a semiconductor layer stack (200), which is suitable for generating electromagnetic radiation, wherein

- The semiconductor layer stack (200) is arranged on the carrier substrate (100), that at least a portion of the carrier substrate (100) facing back of the semiconductor layer stack the the

Semiconductor layer stack facing surface of a first region (110) of the carrier substrate (100) covered and the semiconductor layer stack facing surface of a terminal region (120) of the carrier substrate (100) is free from the semiconductor layer stack (100); and

a first subarea (210) of the

Semiconductor layer stack (200) beyond ^" the edge (111) of the carrier substrate (100) protrudes.

28. The radiation-emitting semiconductor body according to claim 27, wherein a contact layer (14) is applied to the semiconductor body which covers at least part of the front side (201) of the semiconductor layer stack (200) and at least part of the connection region (120) of the carrier substrate (100) ,

29, radiation-emitting semiconductor body according to one of the preceding claims, wherein at least on a part of the connection region (120) of the carrier substrate (100), a first electrically insulating layer (13a) is applied.

30. A radiation-emitting semiconductor body according to one of the preceding claims, in which at least one of the side surfaces (221) of the semiconductor layer stack (200) a second electrically insulating layer (13b) is applied, which covers the side surface at least partially.

31. A radiation-emitting semiconductor body according to one of the preceding claims, wherein on the connection region (120) of the carrier substrate (100), in particular on the contact layer (14), a first electrical connection layer (15) is arranged, which is electrically conductive with that of the carrier substrate (100) facing away from the front side (201) of the semiconductor layer stack (200) is connected.

32. A radiation-emitting semiconductor body according to one of the preceding claims, in which a second electrical connection layer (16) is arranged on the connection region (120) of the carrier substrate (100) which is electrically conductive with the rear side (302) of the semiconductor layer stack facing the front side (201) (200) is connected.

33. The radiation-emitting semiconductor body according to claim 1, wherein the second electrical contact surface is arranged on the rear side of the first partial region of the semiconductor layer stack.

34. The radiation-emitting semiconductor body according to one of the preceding claims, wherein the

Semiconductor layer stack (200) comprises a growth substrate (3).

35. A radiation-emitting semiconductor body according to one of the preceding claims, in which a cavity (12) delimited by the first subregion (210) of the semiconductor layer stack (200), the carrier substrate (100) and a planar base is at least partially filled with a filling material (18) ,

36. Radiation-finishing semiconductor body according to one of the preceding claims, wherein the contact layer

(14) is at least partially transparent to the electromagnetic radiation generated by the semiconductor layer stack (200) during operation.

37. The radiation-emitting semiconductor body according to one of the preceding claims, wherein the contact layer

(14) has a transparent, conductive oxide, in particular indium tin oxide (ITO).

38. The radiation-emitting semiconductor body according to claim 1, wherein the semiconductor layer stack is based on a III / V compound semiconductor material, in particular a nitride compound semiconductor material or phosphide compound semiconductor material, or on an II / VI compound semiconductor material.

39. The radiation-emitting semiconductor body according to one of the preceding claims, wherein the carrier substrate (100) comprises sapphire.

40. The radiation-emitting semiconductor body according to claim 27, wherein the mutually facing surfaces of the semiconductor layer stack (200) and of the carrier substrate (100) have equal side lengths (I _x , I ₃ , I ₂ , I ₄ ).

41. The radiation-emitting semiconductor body according to claim 1, wherein an edge (121) of the connection region (120) of the carrier substrate (100) and an adjacent side surface (221) of the semiconductor layer stack (200) in plan view of the front side of the semiconductor layer stack by 50 μm or more, in particular by lOOμm or more, are offset from each other.

42. Radiation-correcting semiconductor body according to one of the preceding claims, wherein a one side surface

(211) of the first portion (210) of the semiconductor layer stack (200) and an adjacent edge

(111) of the support substrate (100) are offset in plan view of the front side of the Halbleitschichtstapeis by 50 microns or more.