WO2014095353A1

WO2014095353A1 - Method for producing an optoelectronic semiconductor chip, and optoelectronic semiconductor chip

Info

Publication number: WO2014095353A1
Application number: PCT/EP2013/075399
Authority: WO
Inventors: Korbinian Perzlmaier; Sebastian Taeger
Original assignee: Osram Opto Semiconductors Gmbh
Priority date: 2012-12-20
Filing date: 2013-12-03
Publication date: 2014-06-26
Also published as: DE102012112771A1; TW201431118A

Abstract

In at least one embodiment, the method is designed for producing an optoelectronic semiconductor chip (1) and comprises the following steps: A) epitaxially growing a semiconductor layer sequence (3) on a growth substrate (2), B) applying a current spreading layer (4) composed of a transparent conductive oxide to the semiconductor layer sequence (3), C) applying an etching mask (6) to the current spreading layer (4), D) patterning the current spreading layer (4) and the semiconductor layer sequence (3) by etching with the aid of the same etching mask (6), wherein a distance between an edge of the semiconductor layer sequence (3) and an edge of the current spreading layer (4) is at most 3 µm.

Description

description

Process for producing an optoelectronic

Semiconductor chips and optoelectronic semiconductor chip

There will be a method of making a

optoelectronic semiconductor chip specified. In addition, a so produced semiconductor chip is specified. One problem to be solved is a method

specify with the optoelectronic efficient

Semiconductor chips can be produced.

This object is achieved inter alia by a method and by a semiconductor chip with the features of the independent claims. Preferred developments are

Subject of the dependent claims.

In accordance with at least one embodiment, the method comprises the step of epitaxially growing a

Semiconductor layer sequence on. The semiconductor layer sequence is grown on a growth substrate. In which

Growth substrate is, for example, a

Sapphire substrate or a SiC substrate.

According to at least one embodiment, the

Semiconductor layer sequence one or more active zones for generating radiation. The at least one active zone extends in a plane perpendicular to one

Growth direction of the semiconductor layer sequence, preferably continuously and completely over the semiconductor layer sequence. The semiconductor layer sequence is preferably based on a III-V compound semiconductor material. In the semiconductor material is, for example, a nitride compound semiconductor material such as Al _n _In] __ _n _ _m Ga _m N or a phosphide compound semiconductor material such as Al _n _In] __ _n _ _m Ga _m P or an arsenide compound semiconductor material such as Al _n In _] __ _n _ _m Ga _m As, where each 0 ^ n <1, 0 ^ m <1 and n + m -S 1. In this case, the semiconductor layer sequence may have dopants and additional constituents. For the sake of simplicity, however, only the essential constituents of the crystal lattice of the semiconductor layer sequence, ie Al, As, Ga, In, N or P, are given, even if these can be partially replaced and / or supplemented by small amounts of further substances.

For example, during operation of the finished semiconductor chip, an ultraviolet radiation, visible light and / or near-infrared radiation is emitted. In particular, the active zone is designed to produce blue light, for example in the spectral range between 430 nm and 485 nm inclusive.

In accordance with at least one embodiment, the method comprises the step of applying a current spreading layer to the semiconductor layer sequence. The current spreading layer is preferably applied to a side of the semiconductor layer sequence facing away from the growth substrate. It comprises the current spreading layer of one or more transparent, conductive oxides or the current spreading layer consists of one or more such oxides. In this case, the current spreading layer may additionally have a doping.

According to at least one embodiment, the

Semiconductor layer sequence directly on the growth substrate applied. The semiconductor layer sequence and the growth substrate then preferably touch over the whole area. It is possible that the growth substrate is attached to one of the

Semiconductor layer sequence facing side one

Has structuring. The growth substrate may be a so-called structured sapphire substrate, English patterned sapphire substrate or PSS for short.

According to at least one embodiment, the

Current spreading layer at least in places in direct contact with the semiconductor layer sequence. This means,

In places, the current spreading layer touches the

Semiconductor layer sequence. In particular, is one

Area fraction of the current spreading layer in which the

Current spreading layer, the semiconductor layer sequence touches, seen in plan view, at least 70% or 80% or 90% of an area of the semiconductor layer sequence.

In accordance with at least one embodiment, the method comprises the step of applying an etching mask to the

Current spreading layer. The etch mask is configured to provide the current spreading layer and the

Structure semiconductor layer sequence. For example, the etching mask is formed by a photoresist.

In accordance with at least one embodiment, the method comprises the step of structuring the current spreading layer. The structuring is preferably carried out by etching, the structuring being predetermined by the etching mask. After structuring, the etching mask is preferably removed, in particular removed completely and without residue. In accordance with at least one embodiment, the current spreading layer and the semiconductor layer sequence are patterned using the same etching mask. By exactly one etching mask, the structure of the current spreading layer and the semiconductor layer sequence are predetermined.

In accordance with at least one embodiment, a distance or a mean distance of an edge is

Semiconductor layer sequence to an edge of

Stromaufweitungsschicht, along a lateral direction perpendicular to the growth direction, in places or around at most 3 μιη or 2.5 μιη or 2 μιη or 1.5 μιη. Alternatively or additionally, the distance or the mean distance is at most a twenty-fold, a tenfold, a fivefold or twice a mean layer thickness of

Current spreading layer. In other words, the edge of the current spreading layer is approximately

congruent to the edge of the semiconductor layer sequence. In at least one embodiment, the method is for producing an optoelectronic semiconductor chip,

in particular for the production of a light-emitting diode. The method comprises at least the following steps: A) Epitaxial growth of a semiconductor layer sequence on a growth substrate, wherein the semiconductor layer sequence has at least one active zone for generating radiation,

B) applying a current spreading layer of a

transparent, conductive oxide on a side facing away from the growth substrate side of the semiconductor layer sequence, wherein the current spreading layer is at least in places in direct contact with the semiconductor layer sequence, C) applying an etching mask to the current spreading layer,

D) structuring the current spreading layer and the

Semiconductor layer sequence by etching using the same

An etching mask, wherein a distance or an average distance of an edge of the semiconductor layer sequence to an edge of

Current spreading layer, in a direction perpendicular to a growth direction of the semiconductor layer sequence, at most 3 μιη. The abovementioned process steps are preferably carried out in the order indicated. In this case, it is possible that further, not enumerated process steps are carried out between individual process steps or that the process steps mentioned occur exactly in the order given without intermediate steps.

In the specified method, therefore, the structuring of the current spreading layer and the semiconductor layer sequence takes place with the same etching mask. It's about structuring the

Semiconductor layer sequence and the current spreading layer thus only a single photo level required. This is accompanied by a cost reduction and an increase in efficiency, by maximizing a radiation-active surface. A semiconductor layer sequence is often in a first

Textured layer and a current spreading layer of a transparent conductive oxide, short TCO, is structured in a later photo level. Such a separation in photo planes is particularly necessary if the

Semiconductor layer sequence is scribed approximately by means of laser radiation. In such a laser scribing arise comparatively large amounts of slag, which is why in such a

Laserritzen the semiconductor layer sequence with a Sacrificial layer, such as silicon dioxide, is to be covered. To avoid damage to the current spreading layer, such laser scribing is usually to be performed prior to applying the current spreading layer.

In accordance with at least one embodiment, the step of structuring the current spreading layer comprises the sub-step of wet-chemical etching of the current spreading layer. In this wet-chemical etching, preferably no material of the semiconductor layer sequence is removed or it becomes the

Semiconductor layer sequence is not significantly affected by the etching. The wet chemical etching can therefore on the

Stromaufweitungsschicht be limited.

In accordance with at least one embodiment, the step of structuring comprises the substep of the dry chemical etching of the semiconductor layer sequence. This substep is performed after the current spreading layer for

Example wet-chemically removed in places. In the dry-chemical etching, preferably only one material of the semiconductor layer sequence is removed and not or not significantly a material of the

Current spreading layer. As a result, the active zone is at edges of the semiconductor layer sequence of a contamination with electrically conductive material from the

Current spreading layer protectable.

According to at least one embodiment, the

Current spreading layer tin and / or zinc. For example, the current spreading layer is a layer of indium tin oxide or zinc oxide. Also a

Multilayer structure of the current spreading layer of layers of different TCOs is possible. According to at least one embodiment, this remains

Growth substrate on the semiconductor layer sequence. The semiconductor layer sequence is then not on one of the

Aufwachssubstrat different carrier substrate transposed. The growth substrate is finished in the finished

Semiconductor chip thus available.

According to at least one embodiment, the distance or the average distance between the edges of the

Semiconductor layer sequence and the current spreading layer at least 100 nm or 200 nm or 300 nm or 500 nm

and / or at least 50% or 100% of a mean

Layer thickness of the current spreading layer, seen in plan view. By such a distance, the edges of the semiconductor layer sequence and the current spreading layer, for example by light microscopy or

Electron microscopy, distinguishable from each other. In accordance with at least one embodiment, in the step of wet-chemical etching of the current spreading layer, the

Etched mask undercut. This means that the etching mask projects beyond the current spreading layer. The current spreading layer is then completely covered by the etching mask and the

Etch mask has a larger area than the

Current spreading layer, seen in plan view.

According to at least one embodiment, the

Stromaufweitungsschicht and the semiconductor layer sequence dry chemically etched. Likewise, dry chemical etching can be Chemical Dry Etching, or CDE for short, or Reactive Ion Etching, or RIE for short. It can several dry etching steps are combined or only a single dry etching step can be used.

Be the StromaufLeitungsschicht and the

Semiconductor layer sequence etched dry chemically, so is a distance between the edges of the

Current spreading layer and the semiconductor layer sequence preferably at most 200 nm or 100 nm or 50 nm. It can also overlap the edges congruent.

In accordance with at least one embodiment, the method comprises a step E) which follows step D). In step E), a distance of the edges of the current spreading layer and the semiconductor layer sequence from each other is changed. This alteration is preferably carried out by etching, in particular by wet-chemical etching, of the current spreading layer.

In accordance with at least one embodiment, the method comprises a step F). Step F) follows step D). In the step F), the growth substrate and the

Semiconductor layer sequence to the semiconductor chips isolated. The separation is preferably done partially or completely by laser radiation. In particular, the singulation can be a so-called stealth dicing. This is by

Nonlinear absorption of a focused, pulsed

Laser beam with a wavelength for which the

Growth substrate is transparent at moderate intensities, generated within the carrier composite a damaged area in the material.

In accordance with at least one embodiment, the singulation takes place by means of laser radiation, the laser radiation being directed into the rear side facing away from the semiconductor layer sequence by a laser radiation Wax substrate is irradiated. This is a

Slag formation on the semiconductor layer sequence too

prevent. By the laser radiation predetermined breaking points in the growth substrate and / or in the

Semiconductor layer sequence can be generated. After generating the predetermined breaking points, for example, a break occurs to the individual semiconductor chips.

According to at least one embodiment, the

Semiconductor layer sequence has a thickness of at least 2.5 μιη or 3 μιη. Alternatively or additionally, the thickness of the semiconductor layer sequence is at most 15 μιη or 12 μιη or 9 μιη. According to at least one embodiment, a thickness of the growth substrate is at least 50 μιη or 75 μιη or 100 μιη. The thickness of the growth substrate may be alternatively or additionally at most 3 mm or 1.5 mm or 500 μιη or 400 μιη or 300 μιη. After a growth of

Semiconductor layer sequence, the growth substrate can be thinned.

In accordance with at least one embodiment, the current spreading layer extends continuously across the

Semiconductor layer sequence. It is thus possible that no recesses or holes are formed in the current spreading layer.

According to at least one embodiment, the

Current spreading layer over the semiconductor layer sequence across a constant thickness. Constant thickness can

mean that a variation in thickness of at most 30% or 20% or 15% or 10% or 5% of an average thickness of Semiconductor layer sequence is, over the semiconductor chip away.

According to at least one embodiment, the

Current spreading layer after step D) flanks, which are lateral boundary surfaces of the current spreading layer. An angle of these flanks, relative to one

Growth direction of the semiconductor layer sequence is, for example, at least 15 ° or 30 ° and / or at most 60 ° or 75 °. For example, a width of the flanks, in plan view, is at most 1.0 ym or 0.5 ym. This is the case in particular when the current spreading layer is structured dry chemically. Likewise, the flanks seen in plan view of the Stromaufweitungsschicht, at least in places sawtooth or frayed limit the Stromaufweitungsschicht, so that an edge of the

Stromübungsungsschicht comparatively strongly serrated, viewed in plan view, with an average depth of such peaks, in the direction perpendicular to the direction of growth,

for example, at least 100 nm or 250 nm or the average thickness of the current spreading layer and / or at most 600 nm or 400 nm. The latter is especially the case when the current spreading layer is structured wet-chemically.

According to at least one embodiment is on one of

Semiconductor layer sequence facing away from the

Current spreading layer at least one metal contact

applied. The metal contact is formed from one or more metals or metal alloys. In particular, the metal contact is a bonding pad. The

Current spreading layer can be continuous and

extend continuously under the metal contact. According to at least one embodiment, an electrically insulating insulating layer is located between the semiconductor layer sequence and the current spreading layer in a region covered by the metal contact. The

Insulation layer may have the same basic shape and surface area as the metal contact, in particular with a

Tolerance of at most a factor of 5 or 3 or 2.

Preferably, the insulating layer is larger than that

Metal contact, seen in plan view, and dominates the

Metal contact all around. It exists because of

Insulation layer in particular no direct current path from the metal contact to the semiconductor layer sequence. Alternatively, in a region in which a bonding wire is applied to the metal contact, the metal contact

touch in places the semiconductor layer sequence to achieve a better adhesion, wherein at such locations, the semiconductor layer sequence can be electrically non-conductive. The insulation layer can be transparent to radiation,

have a reflective or light-scattering effect.

According to at least one embodiment, the

Isolation layer structured and thus only locally

applied. There is no full-surface application of the insulation layer. As a result, a subsequent removal of material from the insulation layer can be omitted.

In accordance with at least one embodiment, the invention is based on a

Growth substrate facing away from the

Semiconductor layer sequence and / or the Stromaufweitungsschicht an electrically insulating, radiation-transmissive

Applied passivation layer. Preferably, the

Passivation layer a closed layer that the Semiconductor layer sequence continuously covered, wherein areas in which the at least one metal contact is applied, are preferably free of the passivation layer. According to at least one embodiment, the

Passivierungsschicht partly on a side facing away from the growth substrate side of the at least one metal contact over the semiconductor layer sequence. It is then the

Metal contact partly between the passivation layer and the current spreading layer. Preferably, the metal contact is covered to at most 10% or 20% of the passivation layer, seen in plan view.

According to at least one embodiment, the

Current spreading layer has a thickness of at least 30 nm or 50 nm or 70 nm or 100 nm. Alternatively or additionally, the current spreading layer has a thickness of at most 500 nm or 300 nm or 220 nm. According to at least one embodiment, the

Semiconductor layer sequence and / or the finished semiconductor chip, seen in plan view, a mean lateral dimension of at least 200 μιη or 300 μιη or 450 μιη on. The mean lateral dimension may be a mean edge length of the semiconductor chip and / or the

Semiconductor layer sequence act. Alternatively or additionally, the average lateral dimension is at most 2 mm or 1, 5 mm or 1 mm. According to at least one embodiment, the distance

between the edges of the semiconductor layer sequence and the current spreading layer, seen in plan view, the same around the semiconductor layer sequence. Consistent may mean that the respective local distance from an average distance of at most 50% or 30% or 15% or twice the mean thickness of

Current spreading layer and / or deviates by at most 600 nm or 500 nm or 400 nm or 300 nm.

According to at least one embodiment, one of the

Semiconductor layer sequence facing away from the

Current spreading layer has an average roughness of at most 10 nm or 5 nm. In other words, then

Stream spreading layer smooth. A corresponding roughness may alternatively or additionally apply to a side of the semiconductor layer sequence facing away from the growth substrate and / or the passivation layer and / or the insulation layer.

According to at least one embodiment, the

Current spreading layer on a granular or granular structure. An average particle size here is, for example, at least 10 nm or 30 nm or 50 nm and / or at most 300 nm or 200 nm or 150 nm. By this granular structure, a side facing away from the semiconductor layer sequence of the current spreading layer has an average roughness of at least 10 nm or 30 nm or 50 nm and / or of at most 200 nm or 100 nm or 50 nm. By such a comparatively rough current spreading layer, a

Lichtauskoppeleffizienz be increased.

According to at least one embodiment, in the finished semiconductor chip, a current widening is given exclusively by the current spreading layer. A current spreading in the lateral direction, in the direction away from the metal contact, can thus take place exclusively through the current spreading layer. It is thus possible that none on a metal based, especially translucent and thin

Metal layer is used for current expansion. Specifically, then the semiconductor chip does not comprise a continuous or lattice-shaped metal electrode having a thickness of at most 15 nm or 20 nm, and the

Semiconductor layer sequence, seen in plan view, in

Essentially completely covered.

According to at least one embodiment, the

Semiconductor layer sequence after step D) flanks. Flanks are in particular such boundary surfaces of

Semiconductor layer sequence, which are oriented transversely to a substrate top of the growth substrate. According to at least one embodiment, an angle of the flanks of the semiconductor layer sequence, relative to the

Growth direction of the semiconductor layer sequence, at most 30 ° or 15 ° or 10 ° or 5 °. That is, the flanks of the semiconductor layer sequence run parallel or in the

Essentially parallel to the growth direction. Alternatively or additionally, it is possible that this angle is at least 30 ° or 35 ° or 40 ° and / or at most 75 ° or 60 ° or 55 ° or 50 °. In addition, an optoelectronic semiconductor chip is specified. The semiconductor chip is made as in

Connection with one or more of the above

Embodiments described. Features of the method are therefore also for the optoelectronic semiconductor chip

revealed and vice versa.

In at least one embodiment, the

Semiconductor chip, a growth substrate, on the directly one Semiconductor layer sequence is deposited epitaxially. The semiconductor layer sequence comprises at least one active zone for generating a radiation. At a side facing away from the growth substrate is at least in places on the

Semiconductor layer sequence immediately one

Current spreading layer applied. The

Current spreading layer is made of a transparent,

conductive oxide formed or based on such an oxide. A distance of an edge of the semiconductor layer sequence to an edge of the current spreading layer, in the direction perpendicular to a growth direction of the semiconductor layer sequence, is at most 1.0 μιη.

Hereinafter, a method described herein and an optoelectronic semiconductor chip described herein below

Referring to the drawing with reference to embodiments explained in more detail. The same reference numerals indicate the same elements in the individual figures. However, there are no scale relationships shown, but individual elements can be shown exaggerated for better understanding.

FIGS. 1 to 3 are schematic sectional views of FIG

Embodiments of described here

Method for the production of optoelectronic semiconductor chips described here, and Figure 4 is schematic sectional views of a modification of a method. FIG. 1 schematically illustrates a production method for an optoelectronic semiconductor chip 1. According to FIG. 1A, a semiconductor layer sequence 3 is formed on a growth substrate 2, preferably a sapphire substrate

epitaxially deposited. The semiconductor layer sequence 3 is preferably based on InAlGaN.

The semiconductor layer sequence 3 is deposited directly on a substrate top side 20 of the growth substrate 2. Other than illustrated, the substrate top 20 may

Have structuring. Immediately to the

Substrate top 20 is an n-side 31 of

Semiconductor layer sequence 3 grown from an n-type material. Deviating from the illustration according to FIG. 1A, further layers of the semiconductor layer sequence 3 may be located between the substrate top side 20 and the n side 31, for example buffer layers, masking layers and / or growth layers. In the direction away from the growth substrate 2, the n-side follows at least one active zone 32. The active zone 32 comprises at least one pn junction and / or at least one quantum well structure.

Toward the growth substrate 2, the active region 32 is formed from a p-side 33 of a p-type material, for example, GaN-doped GaN.

Deviating from the illustration, it is possible that the n-side and the p-side are reversed. In this case

the p-side is closer to the growth substrate 2. According to FIG. 1B, the growth substrate 2 is deposited on the growth substrate 2

remote side of the semiconductor layer sequence 3 in direct contact locally an optional, electrical insulation layer 5 applied. The insulation layer 5 is for example off Made of silicon oxide, silicon nitride or a silicon oxynitride. A thickness of the insulating layer 5 is located

For example, at least 20 nm or 50 nm and / or at most 200 nm or 120 nm. Seen in plan view, the insulating layer 5, the semiconductor layer sequence 3 preferably at most 20% or 10%.

Characterized in that the insulating layer 5 is applied only locally, a small step in the p-side at an edge of the insulating layer 5 is avoidable. Such a step may result from a subsequent etching of the insulating layer 5. As a result of such subsequent etching, a greater roughness can alternatively or additionally arise in regions of the p-side which are not covered by the insulation layer 5.

In the method step, as shown in FIG. 1C, the entire surface of the semiconductor layer sequence 3 becomes a

Current spreading layer 4 applied. The

Current spreading layer 4 is formed, for example, indium tin oxide, ITO short. It overmoulds and covers the

Current spreading layer 4, the insulating layer. 5

As shown in FIG. 1D, an etching mask 6 is applied to the current spreading layer 4. The etching mask 6 is preferably formed from a photoresist and is patterned in particular by means of a photographic technique. In the etching mask 6 a plurality of recesses are formed, in which the

Stromaufweitungsschicht 4 may be exposed. During the method step, as shown in FIG. 1C, the current spreading layer 4 is removed wet-chemically in the recesses of the etching mask 6. Unlike shown, it is possible that the etching mask 6 is not undercut, but instead the current spreading layer 4 is flush with the etching mask 6, in a direction perpendicular to one

Growth direction G of the semiconductor layer sequence 3. Preferably, however, is a supernatant of the etching mask 6 over the

Current spreading layer 4 at least 50 nm or 200 nm.

According to FIG. 1F, the current spreading layer 4 and the semiconductor layer sequence 3 are structured. The structuring of the semiconductor layer sequence 3 is preferably carried out by dry chemical etching. After the dry-chemical etching of the semiconductor layer sequence 3, the etching mask 6 is removed.

Optionally, the semiconductor layer sequence 3 seen in cross-section on a plurality of sub-areas, which extend over the

Raise growth substrate 2. These sections of the

Semiconductor layer sequence 3 are separated from one another by constrictions of the semiconductor layer sequence 3. It is possible that the subregions located next to the central subregion with the insulation layer 5 are each free of the insulation layer 5. These marginal

Subareas can also be omitted.

In FIG. 1G, an edge of the semiconductor layer sequence 3, which is formed by the etching, is shown in more detail. The flank 35 has, for example, an angle to the growth direction G of about 45 °. A distance D between an edge of the semiconductor layer sequence 3 and the current spreading layer 4 is about 1 μιη. Such a small distance D can be realized by patterning the current spreading layer 4 and the semiconductor layer sequence 3 with the same etching mask 6. In the process step according to FIG. 1H, metal contacts 7 are applied to the current spreading layer 4, in particular applied in a structured manner. Preferably, the insulating layer 5 is located between the metal contact 7 of the central portion and the semiconductor layer sequence 3. The insulating layer 5 is only partially covered by the central metal contact 7 and has a larger footprint than the metal contact 7. In the marginal

Subareas of the semiconductor layer sequence 4, it is possible that between the semiconductor layer sequence 3 and the

Metal contact 7 only the current spreading layer 4 is located. Unlike illustrated, the metal contacts 7 may comprise a plurality of different metal layers.

FIG. 2 shows that a passivation layer 8 is applied to the sides of the semiconductor layer sequence 3 and to the current spreading layer 4 which are opposite to the growth substrate 2. For example, the passivation layer 8 is formed of an electrically insulating oxide or nitride.

Optionally, it is possible that the passivation layer 8, the metal contacts 7 partially covered, seen in plan view. Alternatively, the passivation layer 8 also in the direction transverse to the direction of growth G of the

Be metal contacts 7 spaced and the metal contacts 7 do not touch.

FIG. 1J shows the step of uniting with the individual semiconductor chips 1. In FIG. 1J, in particular the insulation layer, the passivation layer and the metal contacts are not drawn. For singling, a side of the growth substrate 2 facing away from the semiconductor layer sequence 3 becomes one

Laser radiation R irradiated in the growth substrate 2.

By means of the laser radiation R 2 predetermined breaking points 25 are created in the growth substrate. At these predetermined breaking points 25, a complete separation can then take place, for example, by breaking.

Notwithstanding the illustration in FIG. 1J, it is alternatively possible for the laser radiation R to be irradiated from the side on which the semiconductor layer sequence 2 is applied. In this case, the semiconductor layer sequence 2 is preferably completely removed from the growth substrate 2 at those points at which the laser radiation R is irradiated. This allows a slag formation

prevent or reduce.

In Figure 2 is an alternative manufacturing method

shown. FIGS. 2A and 2B correspond to FIGS. 1D to 1F. The further method steps are not shown in FIG. 2 and can be carried out analogously to FIG.

According to FIG. 2B, the current spreading layer 4 and the semiconductor layer sequence 3 are etched dry chemically using the common etching mask 6 previously produced in FIG. 2A. The semiconductor layer sequence 3 and the current spreading layer 4 can therefore be patterned in the same etching step. This makes it possible that a projection between the edges of the semiconductor layer sequence 3 and the Stromaufweitungsschicht 4 disappears and is almost zero or zero. The semiconductor layer sequence 3 and the

Current spreading layer 4 can be flush. Another variant of the manufacturing process is shown in FIG. According to FIG. 3A, both the semiconductor layer sequence 3 and the current spreading layer 4 are etched through the recesses in the etching mask 6. The etching is preferably dry chemical. In this case, it is possible for a projection of the current spreading layer 4 to result over the semiconductor layer sequence 3.

According to FIG. 3B, it is possible for this projection of the current spreading layer 4 to be removed via the semiconductor layer sequence 3, for example by means of a further wet chemical etching step. This subsequent etching is preferably carried out as long as the etching mask 6 is not yet removed.

Deviating from the illustration, it is possible that the etching mask 6 and the current spreading layer 4 are flush in FIG. 3A. In Figure 3B, it is different from the

Representation also possible that the semiconductor layer sequence 3, the current spreading layer 4 projects beyond.

In conjunction with Figure 4 is a modification of

Manufacturing process shown. According to FIG. 4A, the

Insulation layer 5 applied to the semiconductor layer sequence 3 over the entire surface and subsequently structured to form a first etching mask 6a formed from S1O2. Subsequently, see FIG. 4B, the semiconductor layer sequence 3 is patterned on the basis of the first etching mask 6a.

Subsequently, see FIG. 4C, the current spreading layer 4 is applied. Based on a formed from a photoresist second, not shown, the etching mask, the

Current spreading layer 4 structured. This results in a comparatively large and irregular distance between the edge of the current spreading layer 4 and the edge of the semiconductor layer sequence 3.

By the method described in connection with Figures 1 to 3, the distance between the edges of the

Current spreading layer 4 and the semiconductor layer sequence 3 reduced. As a result, a larger radiating surface of the semiconductor chip 1 can be achieved. Also, the distance around the semiconductor layer sequence 3 can be made very uniform. In the method, as shown in FIG. 4, larger variations in the distance between the edges of the semiconductor layer sequence 3 and the current spreading layer 4 can occur, since an exact adjustment of the different etching masks is difficult.

The invention described here is not by the

Description limited to the embodiments.

Rather, the invention encompasses any novel feature as well as any combination of features, including in particular any combination of features in the claims, even if this feature or combination itself is not explicitly stated in the patent claims or exemplary embodiments. This patent application claims the priority of German Patent Application 10 2012 112 771.9, the disclosure of which is hereby incorporated by reference. Reference sign list

1 optoelectronic semiconductor chip

2 growth substrate

20 substrate top

25 predetermined breaking point

3 semiconductor layer sequence

30 main radiation side

31 n page

32 active zone

33 p-side

4 current spreading layer

5 insulation layer

6 etching mask

7 metal contact

8 passivation layer

D distance

G grows

R radiation α angle

Claims

Method for producing an optoelectronic semiconductor chip (1) with the steps:

A) Epitaxial growth of a semiconductor layer sequence (3) on a growth substrate (2), wherein the

Semiconductor layer sequence (3) has at least one active zone for generating radiation,

B) applying a current spreading layer (4) made of a transparent, conductive oxide on a the growth substrate (2) facing away from the

Semiconductor layer sequence (3), wherein the

Current spreading layer (4) at least in places in direct contact with the semiconductor layer sequence (3),

C) applying an etching mask (6) on the

Current spreading layer (4),

D) structuring the current spreading layer (4) and the semiconductor layer sequence (3) by etching using the same etching mask (6),

wherein the method steps in the specified

Order to be performed, and

wherein a distance (D) of an edge of

Semiconductor layer sequence (3) to an edge of

Current spreading layer (4), in one direction

perpendicular to a growth direction (G) of

Semiconductor layer sequence (3), at most 3 ym.

Method according to the preceding claim,

wherein step D) comprises the following substeps in the order given:

Dl) wet-chemical etching only the

Current spreading layer (4), as well D2) dry chemical etching of

Semiconductor layer sequence (3),

wherein the semiconductor layer sequence (3) on

Al _n In _] __ _n _ _m Ga _m N with 0 <n <1, 0 <m <1 and n + m <1 based, the current spreading layer (4) Sn and / or Zn includes and the growth substrate (2) comprises a sapphire Substrate is,

wherein the growth substrate (2) on the

Semiconductor layer sequence (3) remains, and

wherein the distance (D) is at most 1.5 ym and at least 50% of an average thickness of the current spreading layer (4).

Method according to the preceding claim,

in which the etching mask (6) is undercut in step D1), so that the etching mask (6) before step D2)

Stromaufweitungsschicht (4) surmounted.

Method according to claim 1,

in which the current spreading layer (4) and the semiconductor layer sequence (3) are dry-chemically etched in step D),

wherein the distance (D) is between 0 and 200 nm inclusive.

Method according to one of claims 2 to 4,

in step E) corresponding to step D)

follows, the distance (D) is changed by a wet-chemical etching of the current spreading layer (4).

Method according to one of the preceding claims, in which in a step F), after the step D), the growth substrate (2) and the semiconductor layer sequence (3) are separated into the semiconductor chips (1), wherein the singulation is carried out at least partially by means of laser radiation, which is irradiated on a side facing away from the semiconductor layer sequence (3) in the growth substrate (2).

A method according to any one of the preceding claims, wherein the current spreading layer (4) is

continuous and in constant thickness over the

Semiconductor layer sequence (3) extends,

wherein on one of the semiconductor layer sequence (3) facing away from the StromaufWeitungsschicht (4) at least one metal contact (7).

Method according to the preceding claim,

in which between the semiconductor layer sequence (3) and the current spreading layer (4) in one of the

Metal contact (7) covered area an electrically insulating insulating layer (5),

wherein the insulating layer (5) projects beyond the metal contact, seen in plan view.

Method according to the preceding claim,

in which the insulation layer (5) structured only applied locally and subsequently no removal of material from the insulating layer (5).

Method according to one of the preceding claims, in which, on a side facing away from the growth substrate (2), the semiconductor layer sequence (3) and the

Stromaufweitungsschicht (4) each an electrically insulating, radiation-transmissive

Passivation layer (8) is applied,

wherein the passivation layer (8) partially on a side facing away from the growth substrate (2) of the metal contact (7).

Method according to one of the preceding claims, in which

the current spreading layer (4) has a thickness of between 50 nm and 300 nm inclusive,

a thickness of the semiconductor layer sequence (3) is between 2.5 μm and 12 μm, inclusive,

- The finished semiconductor chip (1) has a mean lateral dimension, seen in plan view, between

including 200 ym and 1500 ym, and

- The distance (D), seen in plan view, around the semiconductor layer sequence (3) is constant, with a tolerance of at most 500 nm. 12. The method according to any one of the preceding claims,

in which the current spreading layer (4) has a granular structure and a side of the current spreading layer (4) facing away from the semiconductor layer sequence (3) has an average roughness of at least 30 nm, wherein in the finished semiconductor chip (1)

Current expansion exclusively by the

Current spreading layer (4) made of the transparent, conductive oxide.

Method according to one of the preceding claims, wherein the current spreading layer (4) after the

Step D) has flanks,

an angle of these flanks, relative to a

Growth direction (G) of the semiconductor layer sequence (3), between 15 ° and 75 ° inclusive and / or these flanks, in plan view of the

Stromaufweitungsschicht (4) seen, at least Jagged in places laterally limit the current spreading layer (4).

Optoelectronic semiconductor chip (1) produced by a method according to one of the preceding claims,

wherein the distance (D) is at most 1.0 ym.