TW201431118A - Method for producing an optoelectronic semiconductor chip and optoelectronic semiconductor chip - Google Patents

Abstract

In at least one embodiment, the method is designed for producing an optoelectronic semiconductor chip (1) and comprises the following steps: A) epitaxially growing a semiconductor layer sequence (3) on a growth substrate (2), B) applying a current spreading layer (4) composed of a transparent conductive oxide to the semiconductor layer sequence (3), C) applying an etching mask (6) to the current spreading layer (4), D) patterning the current spreading layer (4) and the semiconductor layer sequence (3) by etching with the aid of the same etching mask (6), wherein a distance between an edge of the semiconductor layer sequence (3) and an edge of the current spreading layer (4) is at most 3 [mu]m.

Description

Method for manufacturing optoelectronic semiconductor wafer and optoelectronic semiconductor wafer

The present invention provides a method of fabricating an optoelectronic semiconductor wafer. Further, the present invention provides a semiconductor wafer fabricated by this method.

It is an object of the present invention to provide a method of efficiently manufacturing an optoelectronic semiconductor wafer.

Moreover, the above object is achieved by a method having the features of the individual terms of the claim and an optoelectronic semiconductor wafer. Other preferred forms are described in the sub-items of the request.

According to at least one embodiment, the method involves the step of epitaxial growth of a sequence of semiconductor layers. The semiconductor layer sequence is grown on a growth substrate. The growth substrate is, for example, a sapphire-substrate or a SiC-substrate.

According to at least one embodiment, the semiconductor layer sequence has one or more active regions for generating radiation. At least one active region is preferably continuous and absent in a growth direction perpendicular to the sequence of the semiconductor layer The voids extend through the sequence of semiconductor layers.

The semiconductor layer sequence is preferably a III-V-compound semiconductor material. The semiconductor material is, for example, a nitride-compound semiconductor material (for example, Al _n In _1-nm Ga _m N) or a phosphide-compound semiconductor material (for example, Al _n In _1-nm Ga _m P) or an arsenide-compound semiconductor. A material (for example, Al _n In _1-nm Ga _m As), where 0 ≦ n ≦ 1, 0 ≦ m ≦ 1 and n + m ≦ 1. Thus, the semiconductor layer sequence can have dopant species as well as other components. However, for the sake of simplicity, only the main components of the crystal lattice of the semiconductor layer sequence, ie, Al, As, Ga, In, N or P, are set, and one of these main components may be replaced by a small amount of other substances. / or add.

For example, emitting violet in the operation of the fabricated semiconductor wafer Radiation from outside, visible light and/or radiation in the vicinity of infrared rays. In particular, the active region is used to generate blue light, and its spectral region is approximately between 430 nm and 485 nm.

According to at least one embodiment, the method includes an The step of applying a current spreading layer on the semiconductor layer sequence. The current spreading layer is preferably applied to one side of the semiconductor layer sequence away from the growth substrate. The current spreading layer comprises one or more transparent conductive oxides or the current expanding layer is composed of one or more of the oxides. Therefore, the current spreading layer may additionally have a doping.

According to at least one embodiment, the semiconductor layer sequence is directly Applied on the growth substrate. Preferably, the semiconductor layer sequence and the growth substrate are in contact with each other over the entire surface. The growth substrate may also have a structure on one side facing the semiconductor layer sequence. The growth substrate can be a type of It is a structured sapphire-substrate (PSS, patterned sapphire substrate).

According to at least one embodiment, the current expansion layer is at least partially The portion is in direct contact with the semiconductor layer sequence. That is, the current spreading layer is partially in contact with the semiconductor layer sequence. In particular, the area fraction of the current spreading layer in contact with the semiconductor layer sequence is at least 70% or 80% or 90% of the area of the semiconductor layer sequence when viewed in plan view.

According to at least one embodiment, the method includes an etch A step of applying a reticle to the current spreading layer. Thus, the etch mask is used to structure the current spreading layer and the semiconductor layer sequence. For example, the etch mask is formed by varnish.

According to at least one embodiment, the method has a The step of structuring the current expansion layer. The structuring is preferably achieved by etching, wherein the structuring is predetermined by the etch mask. After the structuring, the etch mask is preferably removed, in particular completely and without residue.

According to at least one embodiment, the current spreading layer and the half The conductor layer sequence is structured according to the same etch mask. The structure of the current spreading layer and the semiconductor layer sequence can be predetermined by etching the mask.

According to at least one embodiment, one of the semiconductor layer sequences The distance or average distance from the edge to one of the edges of the current spreading layer is at most 3 microns or 2.5 microns or 2 microns or 1.5 microns along a portion or periphery of the transverse direction perpendicular to the growth direction. Or, the distance or the average distance is at most 20 times, 10 times, and 5 times the average layer thickness of the current expansion layer. Double or double. In other words, the edge of the current spreading layer extends approximately superposed with respect to the edge of the semiconductor layer sequence.

In at least one embodiment, the method is used to fabricate an optoelectronic semiconductor wafer, in particular to fabricate a light emitting diode. The method comprises at least the following steps: A) epitaxially growing a semiconductor layer sequence on a growth substrate, wherein the semiconductor layer sequence has at least one active region for generating radiation, and B) is remote from the growth substrate in the semiconductor layer sequence Applying a current spreading layer composed of a transparent conductive oxide on one side, wherein the current expanding layer is at least partially in direct contact with the semiconductor layer sequence, C) applying an etching mask on the current expanding layer, D) structuring the current spreading layer and the semiconductor layer sequence by etching according to the same etching mask, wherein a distance or an average distance from one edge of the semiconductor layer sequence to one edge of the current expanding layer is perpendicular to the The viewing direction of the semiconductor layer sequence is at most 3 microns when viewed.

The above steps of the method are preferably carried out in a set order. Here, other steps not counted may be performed between the respective steps or the above steps may be performed precisely in a set order without an intermediate step.

In the method that has been set, the structuring of the current spreading layer and the semiconductor layer sequence is performed with the same etch mask. Therefore, in order to structure the current spreading layer and the semiconductor layer sequence, only a single light plane is required. In this way, by maximizing the radiation active surface This decreases and the efficiency is improved.

The semiconductor layer sequence is typically structured in the first plane of light The current spreading layer consisting of a transparent conductive oxide (TCO for short) is only structured in the later light plane. If the semiconductor layer sequence is substantially divided by a laser beam, it is particularly necessary to divide into a plurality of light planes in the manner described above. Larger residues are produced in such laser divisions. Therefore, in such laser division, the semiconductor layer sequence must be covered by a sacrificial layer consisting essentially of cerium oxide. In order to prevent damage on the current spreading layer, such laser division is typically performed prior to application of the current spreading layer.

According to at least one embodiment, the structure of the current expansion layer The partial step included in the step of the step is a wet chemical etching of the current spreading layer. In such wet chemical etching, it is preferred that the material of the semiconductor layer sequence is not ablated or the semiconductor layer sequence is not significantly affected by etching. The wet chemical etch can thus be confined to the current spreading layer.

According to at least one embodiment, the step of structuring is included A partial step is a dry chemical etching of the semiconductor layer sequence. This partial step is carried out after the current expansion layer has been partially removed, for example, in a wet chemical manner. In such dry etching, it is preferred that only the material of the semiconductor layer sequence is ablated and the material of the current spreading layer is not ablated or not extensively ablated. Thus, the active region on the side of the semiconductor layer sequence can be protected from contamination by the conductive material from the current spreading layer.

According to at least one embodiment, the current spreading layer comprises tin And / or zinc. For example, the current spreading layer is a layer composed of indium-tin-oxide or zinc oxide. The multilayer structure of the current spreading layer can also be composed of layers of different TCOs.

According to at least one embodiment, the growth substrate remains in the On the semiconductor layer sequence. Then, the semiconductor layer sequence is not bonded to a different carrier substrate than the growth substrate. The growth substrate is therefore still present in the finished semiconductor wafer.

According to at least one embodiment, the side of the semiconductor layer sequence The distance or average distance between the edge and the edge of the current spreading layer is at least 100 nanometers or 200 nanometers or 300 nanometers or 500 nanometers and/or at least the average layer thickness of the current spreading layer when viewed in plan view. 50% or 100%. By such a distance, the edge of the semiconductor layer sequence and the edge of the current spreading layer can be distinguished from one another by, for example, a light microscope or an electron microscope.

According to at least one embodiment, the current expansion layer is wet In the step of chemical etching, the etch mask is under-etched. This means that the etch mask is located on the current spreading layer. The current spreading layer is thus completely covered by the etch mask and has an area greater than the area of the current spreading layer when viewed in plan view.

According to at least one embodiment, the current spreading layer and the half The conductor layer sequence is subjected to dry chemical etching. As usual, dry chemical etching is a chemical dry etch (referred to as CDE) or reactive ion etch (abbreviated as RIE). A variety of dry etching steps can be combined with each other or only a single dry etching step can be used.

If the current expansion layer and the semiconductor layer sequence are respectively received For dry chemical etching, the distance between the edge of the current spreading layer and the edge of the semiconductor layer sequence is preferably at most 200 nm or 100 nm or 50 nm. The edges can also be in a superposed condition with each other.

According to at least one embodiment, the method comprises the step E), It is carried out after step D). In step E), the distance between the edge of the current spreading layer and the edge of the semiconductor layer sequence changes. This change is preferably achieved by etching of the current spreading layer, in particular by wet chemical etching.

According to at least one embodiment, the method comprises a step F). Step F) is carried out after step D). In step F), the growth substrate and the semiconductor layer sequence are divided into semiconductor wafers. This division is preferably achieved in part or in whole by a laser beam. This division can in particular be a so-called stealth dicing. Thus, by non-linear absorption of a focused pulsed laser beam, wherein the growth substrate is permeable to the wavelength of the laser beam at an appropriate intensity, then within the carrier composite A damaged area is created in the material.

According to at least one embodiment, the division is by means of a laser beam The process is performed in which the laser beam is incident into the growth substrate via a back surface away from the semiconductor layer sequence. Thus, formation of slag on the semiconductor layer sequence can be prevented. By means of the laser beam, a nominal fracture zone can be produced in the growth substrate and/or in the semiconductor layer sequence. After the generation of the nominal fracture zone, for example (in the growth substrate and/or semiconductor layer sequence) a break is made into individual semiconductor wafers.

According to at least one embodiment, the semiconductor layer sequence has A thickness of at least 2.5 microns or 3 microns. Alternatively, the semiconductor layer sequence has a thickness of at most 15 microns or 12 microns or 9 microns.

According to at least one embodiment, the thickness of the growth substrate is up to Less is 50 microns or 75 microns or 100 microns. Alternatively, the thickness of the growth substrate is at most 3 mm or 1.5 mm or 500 microns or 400 microns or 300 microns. After growing the semiconductor layer sequence, the growth substrate can be thinned.

According to at least one embodiment, the current spreading layer is continuously Extending over the sequence of the semiconductor layer. Therefore, no notches or holes may be formed in the current expansion layer.

According to at least one embodiment, the semiconductor layer sequence is crossed The current spreading layer has a fixed thickness. The meaning of the fixed thickness may mean that the variation in thickness in the range over the semiconductor wafer is at most 30% or 20% or 15% or 10% or 5% of the average thickness of the semiconductor layer sequence.

According to at least one embodiment, the current spreading layer is in the step D) is followed by a plurality of sides which are the boundary faces of the sides of the current spreading layer. The angle of the sides relative to the direction of growth of the semiconductor layer sequence is, for example, at least 15 or 30 degrees and/or at most 60 or 75 degrees. The width of these sides is, for example, at most 1.0 microns or 0.5 microns when viewed in plan view. This is particularly the case when the current spreading layer is structured by dry chemical etching. Similarly, each of the sides abuts the current spreading layer at least partially in the form of a zigzag or a scattered line when viewed in a plan view of the current spreading layer, such that one of the edges of the current expanding layer is more woven into a plan view. Jagged, in which the serration The average depth in the direction perpendicular to the growth direction is, for example, at least 100 nm or 250 nm or the average thickness of the current expansion layer and/or at most 600 nm or 400 nm. This is especially the case when the current spreading layer is structured in a wet chemical manner.

According to at least one embodiment, at least one metal contact layer is applied on the side of the current spreading layer which is remote from the semiconductor layer sequence. This metal contact layer is formed of one or more metals or formed of a metal alloy. This metal contact layer is in particular a bond pad. The current spreading layer may also extend continuously below the metal contact layer without interruption.

According to at least one embodiment, an isolating layer for electrical isolation is present between the semiconductor layer sequence and the current spreading layer in a region covered by the metal contact layer. This spacer layer may have the same basic form and base as the metal contact layer, in particular having a tolerance of at most 5 or 3 or 2 times. The spacer layer is preferably larger than the metal contact layer and protrudes around the metal contact layer when viewed in plan view. Due to the isolation layer, in particular, a direct current path from the metal contact layer to the semiconductor layer sequence is not formed. Or, in a region (on which a bonding wire is applied on the metal contact layer), the metal contact layer partially contacts the semiconductor layer sequence to achieve a better bonding, in which case the semiconductor layer sequence may not Conductive. The barrier layer can pass radiation, reflect radiation or scatter light.

According to at least one embodiment, the separating layer is structured and thus only partially present. The barrier layer is applied incompletely. Therefore, it is not necessary to remove the material of the separator afterwards.

According to at least one embodiment, in the semiconductor layer sequence and / Or a radiation permeable passivation layer for electrical isolation is applied to a side of the current expansion layer away from the growth substrate. The passivation layer is preferably a closed layer that continuously covers the semiconductor layer sequence, and a plurality of regions to which at least one metal contact layer is applied preferably do not have the passivation layer.

According to at least one embodiment, a part of the passivation layer is The side of the at least one metal contact layer extending away from the side of the growth substrate extends over the semiconductor layer sequence. A portion of the metal contact layer is thus located between the passivation layer and the current spreading layer. The metal contact layer preferably covers up to 10% or 20% of the passivation layer when viewed in plan view.

According to at least one embodiment, the current spreading layer has Less than 30 nm or 50 nm or 70 nm or 100 nm thickness. Alternatively, the current spreading layer has a thickness of at most 500 nm or 300 nm or 220 nm.

According to at least one embodiment, the semiconductor layer sequence and/or Or the fabricated semiconductor wafer has an average lateral dimension of at least 200 microns or 300 microns or 450 microns when viewed in plan view. The average lateral dimension may be the average side length of the semiconductor wafer and/or the semiconductor layer sequence. Alternatively, the average lateral dimension is at most 2 mm or 1.5 mm or 1 mm.

According to at least one embodiment, the side of the semiconductor layer sequence The distance between the edge and the edge of the current spreading layer remains the same around the sequence of semiconductor layers as viewed in plan view. By maintaining the same meaning, it is meant that the distances that are still locally present are locally offset by an average distance by up to 50% or 30% or 15% or from twice the average thickness of the current expansion layer and/or by a deviation of up to 600 nm or 500. Nano or 400 nm or 300 nm.

According to at least one embodiment, the current spreading layer is far away One side of the semiconductor layer sequence has an average roughness of at most 10 nm or 5 nm. In other words, the current spreading layer is smooth. Alternatively, a suitable roughness may be applied to the semiconductor layer sequence and/or the passivation layer and/or the isolation layer away from the side of the growth substrate.

According to at least one embodiment, the current spreading layer has Granular or granular structure. The average particle size is, for example, at least 10 nm or 30 nm or 50 nm and/or at most 300 nm or 200 nm or 150 nm. With such a granular structure, the current-expanding layer has an average roughness of at least 10 nm or 30 nm or 50 nm away from one side of the semiconductor layer sequence and/or at most 200 nm or 100 nm. Average roughness of meters or 50 nm. With such a coarse current spreading layer, the optical coupling efficiency can be improved.

According to at least one embodiment, the finished semiconductor crystal The current expansion property is set only by the current expansion layer in the sheet. The current expandability in the lateral direction (the direction in which the metal contact layer leaves) can thus be achieved only by the current spreading layer. Thus, a thin metal layer that is not primarily metal, especially light transmissive, can be used to expand the current. The semiconductor wafer comprises, in particular, a metal electrode in the form of a discontinuous or grid, having a thickness of at most 15 nm or 20 nm and substantially completely covering the semiconductor layer sequence when viewed in plan view.

According to at least one embodiment, the semiconductor layer sequence has a plurality of sides after step D). These sides, in particular the boundary faces of the semiconductor layer sequence, are oriented transverse to the upper side of the substrate of the growth substrate.

According to at least one embodiment, the side of the semiconductor layer sequence The angle formed by the side with respect to the growth direction of the semiconductor layer sequence is at most 30 degrees or 15 degrees or 10 degrees or 5 degrees. That is, the sides of the semiconductor layer sequence extend parallel or substantially parallel to the growth direction. Alternatively, the angle may be at least 30 degrees or 35 degrees or 40 degrees and/or at most 75 degrees or 60 degrees or 55 degrees or 50 degrees.

Further, the present invention provides an optoelectronic semiconductor wafer. The semiconductor wafer is fabricated in accordance with one or more of the methods described in the above embodiments. The features of the method are therefore also disclosed in the optoelectronic semiconductor wafer and vice versa.

In at least one embodiment, the semiconductor wafer includes a growth substrate on which a semiconductor layer sequence is deposited directly in an epitaxial manner. The semiconductor layer sequence includes at least one active region for generating radiation. On the side remote from the growth substrate, a current spreading layer is applied at least partially directly over the semiconductor layer sequence. The current spreading layer is formed of a transparent conductive oxide or is mainly composed of such an oxide. The distance from the edge of the semiconductor layer sequence to the edge of the current spreading layer is at most 1.0 micrometer when viewed in a direction perpendicular to the growth direction of the semiconductor layer sequence.

Hereinafter, the above method and optoelectronic semiconductor wafer will be described in detail in accordance with various embodiments and with reference to the drawings. The same reference symbols in the various drawings represent the same elements. However, the size ratio between the various elements is not necessarily drawn to scale. Conversely, for ease of understanding, the individual components have been shown enlarged.

1‧‧‧Optoelectronic semiconductor wafer

2‧‧‧ Growth substrate

20‧‧‧Upper side of the substrate

25‧‧‧rated fault zone

3‧‧‧Semiconductor layer sequence

30‧‧‧Main side of radiation

31‧‧‧n-side

32‧‧‧Active area

33‧‧‧p-side

35‧‧‧ side

4‧‧‧current expansion layer

5‧‧‧Isolation

6‧‧‧ etching mask

7‧‧‧Metal contact layer

8‧‧‧ Passivation layer

D‧‧‧Distance

G‧‧‧Growth direction

R‧‧‧Laser beam

‧‧‧‧ angle

Figures 1 to 3 show the use of the optoelectronic semiconductor crystal here for fabrication A cross-sectional view of an embodiment of a method of sheet.

Figure 4 shows a cross-sectional view of the different ways of the method.

The method for manufacturing the optoelectronic semiconductor wafer 1 of the present invention is shown in Fig. 1. According to FIG. 1A, a semiconductor layer sequence 3 is epitaxially deposited on a growth substrate 2, preferably a sapphire-substrate. This semiconductor layer sequence 3 is preferably mainly InAlGaN.

The semiconductor layer sequence 3 is deposited directly on the substrate upper side 20 of the growth substrate 2. Unlike the drawings, the upper side 20 of the substrate can have a structure. The n-side 31 of the semiconductor layer sequence 3 is grown directly on the substrate upper side 20 from an n-conductive material. Unlike the pattern of FIG. 1A, there are other layers of the semiconductor layer sequence 3 between the upper side 20 and the n-side 31 of the substrate, for example, a passivation layer, a photomask layer, and/or a growth layer. In the direction away from the growth substrate 2, at least one active region 32 follows the n-side. The active region 32 includes at least one pn junction and/or at least one quantum well structure.

In the direction away from the growth substrate 2, the active region 32 of the p-side 33 is formed of a p-conductive material (for example, GaN doped with magnesium). Unlike the drawings, the n-side and the p-side are also interchangeable. In this case, the p-side is closer to the growth substrate 2.

According to FIG. 1B, an optional electrically isolating layer 5 is applied locally in direct contact with one side of the semiconductor layer sequence 3 remote from the growth substrate 2. This spacer layer 5 is made of, for example, hafnium oxide, tantalum nitride or hafnium oxynitride. The thickness of this barrier layer 5 is, for example, at least 20 nm or 50 nm and/or at most 200 nm or 120 nm. The spacer layer 5 preferably covers at most the semiconductor when viewed in a top view. 20% or 10% of the layer sequence 3.

Since the isolation layer 5 is only applied locally, it can be separated Avoiding the formation of small steps in the p-side is avoided on one of the edges of the layer 5. Such a step can be derived from the subsequent etching of the isolation layer 5. Alternatively, due to such post-etching, a large roughness can be formed in the region of the p-side which is not covered by the spacer layer 5.

In the step shown in FIG. 1C, in the semiconductor sequence A current spreading layer 4 is applied to the entire surface of column 3. This current expansion layer 4 is formed, for example, of indium-tin-oxide (abbreviated as ITO). The current spreading layer 4 is formed excessively and covers the isolation layer 5.

As shown in FIG. 1D, a current is applied to the current expansion layer 4. The reticle 6 is etched. The etch mask 6 is preferably formed of a lacquer and is specifically structured by optical techniques. A plurality of recesses are formed in the etch mask 6, and the current spreading layer 4 is exposed in the recess.

In the step shown in Figure 1E, wet chemical etching The current spreading layer 4 is removed in the recess of the etch mask 6. Different from the drawing, the etching mask 6 may not be under-etched, but the current expanding layer 4 and the etching mask may be formed in a direction perpendicular to the growth direction G of the semiconductor layer sequence 3. 6 flush. However, the protrusion of the etch mask 6 on the current spreading layer 4 is preferably at least 50 nm or 200 nm.

According to the 1F map, the current expansion layer 4 and the semiconductor The layer sequence 3 is structured. The structuring of the semiconductor layer sequence 3 is preferably carried out by dry chemical etching. After the dry chemical etching of the semiconductor layer sequence 3, the etch mask 6 is removed.

The semiconductor layer sequence 3 is optional when viewed in a cross section The ground has a plurality of partial regions which protrude from the growth substrate 2. These partial regions of the semiconductor layer sequence 3 are separated from each other by the tightening action of the semiconductor layer sequence 3. A plurality of partial regions located beside the central portion of the isolation layer 5 may not have the isolation layer 5. These partial areas on the edge can also be omitted.

The side of the semiconductor layer sequence 3 is shown in detail in FIG. 1G. The edge is formed by etching. This side 35 has, for example, an angle a of approximately 45 degrees with respect to the growth direction G. The distance D between the edge of the semiconductor layer sequence 3 and the edge of the current spreading layer 4 is about 1 micrometer. Such a small distance D can be achieved by "the current spreading layer 4 and the semiconductor layer sequence 3 are structured by the same etching mask 6".

In the step of Figure 1H, a plurality of metal contact layers 7 are applied to the current spreading layer 4, in particular in a structured manner. The spacer layer 5 is preferably between the metal contact layer 7 in the central portion and the semiconductor layer sequence 3. The spacer layer 5 is only partially covered by the central metal contact layer 7 and has a base surface larger than the base surface of the metal contact layer 7. In a partial region of the semiconductor layer sequence 4 situated at the edge, the current spreading layer 4 can be situated only between the semiconductor layer sequence 3 and the metal contact layer 7. Unlike the drawings, each metal contact layer 7 can have a plurality of different metal layers.

It is shown in FIG. 1I that a passivation layer 8 is applied on the side of the semiconductor layer sequence 3 remote from the growth substrate 2 and on the current expansion layer 4, respectively. For example, the passivation layer 8 is formed of an oxide or nitride for electrical isolation.

The passivation layer 8 is optionally made when viewed in a top view The metal contact layer 7 is covered in a regional manner. Alternatively, the passivation layer 8 may be spaced apart from the metal contact layer 7 in a direction transverse to the growth direction G and not in contact with the metal contact layer 7.

Figure 1J shows the division into individual semiconductor wafers 1 A step of. In particular, the spacer layer, the passivation layer, and the metal contact layers are not shown in FIG. 1J.

For the division, the growth substrate 2 is away from the half One side of the conductor layer sequence 3 enters the laser beam R into the growth substrate 2. The rated fracture region 25 is set in the growth substrate 2 by the laser beam R. The complete division can then be carried out on each of the rated breaking zones 25, for example by breaking.

Or, unlike the pattern of Figure 1J, the laser beam R is also It can be incident on the side to which the semiconductor layer sequence 2 is applied. In this case, the semiconductor layer sequence 2 is preferably completely removed by the growth substrate 2 at such a position where the laser beam R is incident. Thus, the formation of slag can be prevented or the form of slag can be reduced.

Figure 2 shows another manufacturing method. Figure 2A and The 2B map corresponds to the 1D to 1F maps. Other steps are not shown in Fig. 2 and can be performed in a manner similar to Fig. 1.

According to FIG. 2B, the current spreading layer 4 and the semiconductor layer sequence 3 are etched in a dry chemical etching manner in accordance with the common etching mask 6 which has been produced in the previous FIG. 2A. Therefore, the structuring of the semiconductor layer sequence 3 and the current spreading layer 4 can be performed in the same etching step. Thus, the edge of the semiconductor layer sequence 3 and the edge of the current expansion layer 4 can be made The protrusion between the edges disappears and is almost zero or zero. The semiconductor layer sequence 3 and the current spreading layer 4 may be flush.

Another form of the manufacturing method is shown in Fig. 3. according to According to FIG. 3A, the semiconductor layer sequence 3 and the current spreading layer 4 are etched through the recesses in the etch mask 6. This etching is preferably carried out by dry chemical etching. Thus, a protrusion of the current spreading layer 4 on the semiconductor layer sequence 3 may be caused.

According to FIG. 3B, the current spreading layer 4 is in the semiconductor The protrusions on layer sequence 3 can be substantially removed by an additional wet chemical etching step. As long as the etching mask 6 has not been removed, such subsequent etching can be preferentially performed.

Unlike the drawing, the etching mask 6 and the electricity in FIG. 3A The flow expansion layer 4 can be flush. In Fig. 3B, the semiconductor layer sequence 3 can also be placed on the current spreading layer 4, similarly to the drawing.

Another mode of the above manufacturing method is shown in Fig. 4. According to Fig. 4A, the spacer layer 5 is applied over the semiconductor layer sequence 3 in a full-face manner and subsequently structured into a first etch mask 6a formed of SiO ₂ . Then, referring to FIG. 4B, the semiconductor layer sequence 3 is structured in accordance with the first etch mask 6a.

Then, referring to FIG. 4C, the current expanding layer 4 is applied. The current spreading layer 4 is structured according to a second etching mask not shown which is formed of a varnish. Thus, an irregularly large distance is created between the edge of the current spreading layer 4 and the edge of the semiconductor layer sequence 3.

The electricity can be made by the method shown in Figures 1 to 3. The distance between the edge of the flow expansion layer 4 and the edge of the semiconductor layer sequence 3 is reduced. Therefore, the semiconductor wafer 1 can be made to have a large radiation area. It is also possible to form the distance around the semiconductor layer sequence 3 very uniformly. In the method shown in FIG. 4, the distance between the edge of the current spreading layer 4 and the edge of the semiconductor layer sequence 3 can be greatly changed, because it is difficult to accurately calibrate different etching masks. .

The invention is of course not limited to the description made in accordance with the various embodiments. Rather, the invention encompasses each novel feature and each combination of features, and in particular each of the features of the inventions. The invention is also in the middle or in the examples.

The present patent application claims the priority of the German Patent Application No. 10 2012 112 77, the entire disclosure of which is hereby incorporated by reference.

2‧‧‧ Growth substrate

3‧‧‧Semiconductor layer sequence

4‧‧‧current expansion layer

5‧‧‧Isolation

30‧‧‧Main side of radiation

35‧‧‧ side

Claims (14)

A method of fabricating an optoelectronic semiconductor wafer (1) comprising the steps of: A) epitaxially growing a semiconductor layer sequence (3) on a growth substrate (2), wherein the semiconductor layer sequence (3) has at least one for generating radiation Active region, B) applying a current expansion layer (4) composed of a transparent conductive oxide on a side of the semiconductor layer sequence (3) remote from the growth substrate (2), wherein the current expansion layer (4) At least partially in direct contact with the semiconductor layer sequence (3), C) applying an etch mask (6) on the current spreading layer (4), D) by means of the same etch mask (6) Etching structuring the current spreading layer (4) and the semiconductor layer sequence (3), wherein the steps are performed in a given order, and one edge of the semiconductor layer sequence (3) is to the current expanding layer (4) The distance (D) of an edge is at most 3 micrometers when viewed in a direction perpendicular to the growth direction (G) of the semiconductor layer sequence (3). The method of claim 1, wherein the step D) comprises the following steps of the set sequence: D1) wet chemical etching only the current expansion layer (4), and D2) the semiconductor layer sequence (3) Performing a dry chemical etching, wherein the semiconductor layer sequence (3) is dominated by Al _n In _1-nm Ga _m N, wherein 0≦n≦1, 0≦m≦1 and n+m≦1, the current expansion The layer (4) comprises tin and/or zinc and the growth substrate (2) is a sapphire substrate, wherein the growth substrate (2) remains on the semiconductor layer sequence (3), the distance (D) being at most 1.5 microns and at least It is 50% of the average thickness of the current expanding layer (4). The method of claim 1 or 2, wherein the etching mask (6) is under-etched in the step D1) such that the etching mask (6) is located on the current spreading layer (4) before the step D2) . The method of claim 1, wherein the current expanding layer (4) and the semiconductor layer sequence (3) are etched by dry chemical etching in step D), wherein the distance (D) is between 0 nm (inclusive) And between 200 nm. The method of any one of claims 2 to 4, wherein the distance (D) is changed by wet chemical etching of the current spreading layer (4) in step E) performed after step D). The method of any one of claims 1 to 5, wherein after step D), the growth substrate (2) and the semiconductor layer sequence (3) are divided into semiconductor wafers (1) in step F), wherein At least part of the division is carried out by means of a laser beam which is incident on the growth substrate (2) on a side remote from the semiconductor layer sequence (3). The method of any one of claims 1 to 6, wherein the current spreading layer (4) continuously extends over the semiconductor layer sequence (3) with a fixed thickness, and away from the current spreading layer (4) At least one metal contact layer (7) is present on one side of the semiconductor layer sequence (3). The method of any one of claims 1 to 7, wherein an electrical property exists between the semiconductor layer sequence (3) and the current spreading layer (4) in a region covered by the metal contact layer (7) An isolating layer (5) for isolation, the spacer layer (5) protruding around the metal contact layer when viewed in plan view. The method of any one of claims 1 to 8, wherein the barrier layer (5) is applied structurally only partially and the material of the barrier layer (5) is not subsequently removed. The method of any one of claims 1 to 9, wherein an electrical isolation is applied to one side of the semiconductor layer sequence (3) remote from the growth substrate (2) and the current expansion layer (4). The radiation passivation layer (8), wherein at least a portion of the passivation layer (8) extends on a side of the metal contact layer (7) away from the growth substrate (2). The method of any one of claims 1 to 10, wherein - the current expansion layer (4) has a thickness of between 50 nm and 300 nm, - the semiconductor layer sequence (3) The thickness is between 2.5 micrometers (inclusive) and 12 micrometers, - the fabricated semiconductor wafer (1) has an average lateral dimension between 200 micrometers (inclusive) and 1500 micrometers when viewed in plan view, and - The distance (D) remains the same around the sequence of semiconductor layers (3) when viewed in plan view, the tolerance of the distance (D) being at most 500 nm. The method of any one of claims 1 to 11, wherein the current expansion layer (4) has a granular structure and the current expansion layer (4) has at least 30 nanometers away from one side of the semiconductor layer sequence (3) The average roughness of the rice in which the current expansion in the fabricated semiconductor wafer (1) is achieved only by the current expansion layer (4) composed of a transparent conductive oxide. The method of any one of claims 1 to 12, wherein the current expansion The layer (4) has a side after step D), the angle formed by the side relative to the growth direction (G) of the semiconductor layer sequence (3) is between 15 degrees (inclusive) and 75 degrees and The side edge abuts the current spreading layer (4) in a lateral direction at least partially in a zigzag manner when viewed in a plan view of the current spreading layer (4). An optoelectronic semiconductor wafer (1) made by the method of any one of claims 1 to 13, wherein the distance (D) is at most 1.0 micron.