EP1987642A2

EP1987642A2 - Gateway for the automatic routing of messages between buses

Info

Publication number: EP1987642A2
Application number: EP07704434A
Authority: EP
Inventors: Markus Ihle; Jan Taube; Tobias Lorenz
Original assignee: Robert Bosch GmbH
Current assignee: Robert Bosch GmbH
Priority date: 2006-02-14
Filing date: 2007-02-07
Publication date: 2008-11-05
Anticipated expiration: 2027-02-07
Also published as: WO2007093546A2; DE102007001137B4; US20090225766A1; RU2008136752A; US7907623B2; JP4612094B2; DE102007001137A1; EP1987642B1; CN101385296A; CN101385296B; ES2392549T3; RU2415511C2; JP2009527168A; WO2007093546A3

Abstract

The invention discloses a gateway (1) for the automatic routing of messages between buses (3), said gateway being connected to several communication components (2) for temporarily storing and transmitting messages (N) via said buses and a gateway control unit, which is connected to the communication components (2) via a system bus in order to exchange messages (N) and which receives notification in the form of an external event (EVext) from each communication component (2) of the occurrence of a message (N) to be routed in said component. The gateway control unit has a vector memory (VRAM) comprising a first memory area for storing communication component vectors (KBV), a communication component vector (KBV) being provided for each message group of a communication component (2) and said vector indicating the time point (ZP) of the next expected internal event (EVint) for a message (N) that is stored in the communication component (2) and a vector jump address to a message vector (NV), which is stored in a second memory area of the vector memory (VRAM). A corresponding message vector (NV) is stored for each message (N) that has been temporarily stored in the communication component (KB), said vector indicating a configurable time point (ZP) of an internal event (EVint) that is triggered by the associated message (N), in addition to a command jump address. The gateway control unit also contains a command memory (IRAM) for storing commands that can be addressed by the command jump address indicated in the message vector (NV) and a control structure (FSM), which reads the communication component vector (KBV) associated with the respective communication component (2) from the first memory area of the vector memory (VRAM), if an internal event (EVint) occurs, whose time point (ZP) is indicated in a message vector (NV) of a message (N) that is temporarily stored in a communication component (KB), or if said control structure (FSM) is notified of the occurrence of an external event (EVext) by a communication component (2). The control structure uses the vector jump address contained in the communication component vector to read the command jump address of the addressed message vector (NV) from the second memory area of the vector memory (VRAM) and then reads and executes at least one command from the command memory (IRAM) using the read command jump address. The time points (ZP) indicated in the vectors (NV, KBV) are then updated.

Description

description

title

Gateway for automatically routing messages between buses

The present invention relates to a gateway for automatically routing messages between buses, especially between serial buses and field buses.

The networking of control devices, sensors and actuators using a network or communication system consisting of a communication link, in particular a bus, and corresponding communication modules, has in recent years in the construction of modern motor vehicles or in mechanical engineering, especially in the machine tool sector and in automation drastically increased. Synergy effects through the distribution of functions to multiple subscribers, in particular ECUs, can be achieved. This is called distributed systems. Such distributed systems or networks thus consist of the subscribers and the bus system connecting these subscribers or several connecting bus systems. The communication between different stations or subscribers thus takes place more and more via such a communication system, bus system or network, via which the data to be transmitted are transmitted in messages. This communication traffic on the bus system, access and reception mechanisms and error handling are regulated by a corresponding protocol, the name of the respective protocol is often and thus also used here as a synonym for the networks or the bus system itself.

As a protocol, for example, the CAN bus (Controller Area Network) has established itself in the automotive sector. This is an event-driven protocol, that is, protocol activities such as sending a message are initiated by events that originate outside the communication system. The clear access to the communication system or bus system is solved by a priority-based bit arithmetic. A prerequisite for this is that the data to be transmitted and thus each message is assigned a priority. The CAN protocol is very flexible; Adding additional participants and messages is thus easily possible, as long as there are still free priorities (Message Identifier). The collection of all messages to be sent in the network with priorities and their sending the or receiving participants or the corresponding communication blocks are stored in a list, the so-called communication matrix.

An alternative approach to event-driven, spontaneous communication is the purely time-driven approach. All communication activities on the bus are strictly periodic. Protocol activities such as the sending of a message are triggered only by updating a time valid for the entire bus system. Access to this medium is based on the allocation of time ranges in which a broadcaster has exclusive broadcasting rights. As a rule, the message order is to be set prior to startup. Thus, a roadmap is created that meets the requirements of the messages in terms of repetition rate, redundancy, deadlines, etc. One speaks of the so-called bus schedule. Such a bus system is for example the TTP / C.

The advantages of both types of bus mentioned are combined in the solution of the time-controlled CAN, the so-called TTCAN (Time Triggered Controller Area Network). This satisfies the above outlined demands for timed communication as well as the demands for a certain degree of flexibility. The TTCAN accomplishes this by setting up the communication cycle in so-called exclusive time slots for periodic messages of certain communication users and in so-called arbitrating time windows for spontaneous messages from multiple communication users. TTCAN is essentially based on time-controlled, periodic communication which is clocked by a main-time-generating subscriber or communication module, the so-called time master, with the aid of a time reference message.

Another option for connecting different types of transmission is provided by the FlexRay protocol, which describes a fast, deterministic and fault-tolerant bus system, especially for use in a motor vehicle. This protocol operates according to the method of Time Division Multiple Access (TDMA), whereby the participants or the messages to be transmitted are assigned fixed time slots in which they have exclusive access to the communication link, the bus. The time slots are repeated in a defined cycle, so that the time at which a message is transmitted over the bus, can be predicted exactly and the bus access is deterministic. To optimally use the bandwidth for message transmission on the bus system, the cycle is divided into a static and a dynamic part. The fixed time slots are located in the static part at the beginning of a bus cycle. In the dynamic part, the time slots are allocated dynamically according to the method of the Flexible Time Division Multiple Access (FTDMA). This is now the exclusive bus access only possible for a short time. If there is no access, the access for the next participant is released. This period of time is referred to as a minislot, in which the access of the first participant is waited.

As just described, there are a variety of different transmission technologies and thus types of bus systems or networks. It is often the case that several bus systems of the same or different type must be connected to one another. This is served by a bus interface unit, a so-called gateway. A gateway is thus an interface between different buses, which may be the same or different in nature, with the gateway relaying messages from a bus to one or more other buses. Known gateways consist of several independent communication modules, the exchange of messages taking place via the processor interface (CPU interface) of the respective subscriber or the corresponding interface module of the respective communication module. In this case, this CPU interface is heavily burdened by this data exchange and other applicative functions in addition to the participants themselves to be transmitted messages, which together with the resulting transmission structure results in a relatively low data rate or on the other hand, a high clock frequency with high power consumption. Furthermore, there are integrated communication controllers or communication modules which share a common message memory, the so-called message memory or message RAM, in order to compensate for the structural disadvantages. However, such integrated communication modules are therefore very inflexible with respect to the data transmission and in particular fixed to a certain number of bus connections and usually also to the same bus system.

Figure 1 shows a conventional communication module or communication controller CC for a conventional gateway, as shown in Figure 2. The communication module CC has an interface for an internal peripheral bus or system bus of the gateway and a further interface for an external serial bus. The system bus comprises an address bus, a data bus and a control bus and serves for internal data transmission within the gateway. In addition to the communication module, a host CPU with a data memory RAM and further optional components, eg DMA controllers, are connected to the system bus. The host CPU is used for internal data processing and controls the internal data transfer from one communication component CC to another communication component CC. The communication modules CC communicate with the host CPU according to the master / slave principle, wherein communication modules represent slave units and the host CPU forms a master unit. As can be seen from FIG. 1, the internal interface of the communication module CC to the system bus is formed by a two-layered interface, namely by a customer interface and a generic interface. The customer interface connects the system bus to the generic interface, whereby the customer interface is vendor-specific and easily replaceable. The generic interface can be connected via the customer interface to a large number of customer-specific system busses. The communication module CC according to the prior art and as shown in Figure 1, further includes buffer memory for buffering data to be transferred. The buffer memories are formed, for example, by RAM or data registers. The communication module CC also contains a message forwarding unit or a message handler for forwarding messages from at least one message memory and a communication protocol unit, as well as buffer memories. The message store or the message RAM stores the message objects to be transferred as well as configuration and status information data. The message forwarding unit handles the control of the data flow between all the buffers, the communication protocol unit and the message buffer. The communication protocol unit (PRT) of the conventional communication module CC shown in FIG. 1 implements the communication according to the data transmission protocol used. In this case, the communication protocol unit PRT assumes the conversion or conversion between the data format of the data packets DP transmitted via the external serial bus and the messages or messages MSG used within the communication module. The forwarded by the message forwarding unit or the message handler messages MSG consist of at least one data word DW, wherein the word length or the number of bits of the data word DW preferably corresponds to the bus width of the internal intended data bus of the gateway. For example, if the system bus has a 32-bit internal data bus, the data word DW also includes 32 bits. A message or message MSG can consist of a predetermined number of data words DW. The storage capacity of a buffer memory corresponds, for example, to the data volume of a message or a message which comprises a predefined number of data words DW. The arbitration of the data flow is carried out by the message forwarding unit or the message handler.

In particular, in vehicles today several serial buses and field buses, such as serial field buses such as a CAN bus, a FlexRay bus, a MOST bus or a LIN bus are used. During operation, data is exchanged between these serial buses, which may form part of a network, via a gateway GW. Depending on the vehicle and the functions performed, the data volume in the central gateway GW, as shown in FIG. 2, can be very high. This data traffic causes a high CPU load, ie the CPU is burdened with routing data from one serial bus to one or more other serial buses. Furthermore, the CPU load is increased by operations needed to reduce bandwidth on individual networks or serial buses, for example, combining the data contents of multiple messages into a new message.

In many cases, it is necessary to periodically send messages to meet security requirements in a given time frame. For high-priority messages, it may be necessary to send the message immediately without timeout or out of the time frame. The check whether a message should be sent again or a message because of an error occurred, such as a missed message, may no longer be sent, is also done by the CPU of the gateway GW and consumes CPU power.

In many cases, the CPU performs other functions in parallel through d. h., running on the CPU parallel processing processes that adversely affect each other and delay the transmission or forwarding of a message. As a result of these parallel processes, the jitter and the latency times for the transmission of the messages increase, since an interruption of the parallel processes is in many cases not possible.

It is therefore the object of the present invention to provide a gateway for automatically routing messages between buses, which forwards messages without affecting the CPU and independently of a CPU load.

This object is achieved by a gateway with the features specified in claim 1.

The invention provides a gateway for automatically routing messages between buses using:

a plurality of communication modules for buffering and transmitting messages N via the buses; and with

a gateway control unit, which is connected to the communication modules via a system bus for exchanging messages N, and that of each communication module. stone receives the occurrence of a message N to be routed there as an external event EV _ext ,

wherein the gateway control unit comprises:

a vector memory VRAM having a first memory area for storing communication block vectors KBV, wherein a communication block vector KBV is provided for each communication block which determines the time ZP of a next expected internal event _EVmt for a message _buffered in the communication block N and a vector jump address to a message vector NV, which is stored in a second memory area of the vector memory VRAM, wherein for each in the communication block cached relevant message N, a corresponding message vector NV is stored, the one configurable time ZP to be triggered by the associated message N. internal event EV _{ιnt indicating} a command _{jump address} , as well as other configuration and control data;

a command memory IRAM for storing commands addressable by the command hop address specified in the message vector NV; and

a status register SR which temporarily stores the time for the next expected event of all expected internal events for all messages N buffered in the communication blocks.

a sequence control FSM, which is temporarily stored in a status register SR for all messages N stored in the communication blocks when an internal event _{EVmt occurs} , or when an external event EV _{ext occurs} , which is indicated to the sequence control FSM by a communication block , reads out the communication memory vector KBV belonging to the respective communication module from the first memory area of the vector memory VRAM and reads out the instruction jump address of the addressed message vector NV from the second memory area of the vector memory VRAM by means of the vector jump address contained therein and then by means of the read command jump address at least one command from the Reads and executes instruction memory IRAM, wherein the time points ZP indicated in the vectors NV, KBV are updated. In one embodiment of the gateway according to the invention this has at least one further processor, which is connected via a second separate system bus with the communication modules.

In one embodiment of the gateway according to the invention, the control unit of the gateway control unit has an event FS M, which evaluates the stored in the vector memory VRAM vectors KBV, NV when an internal event or an external event EV _ext and updates the times indicated in the vectors; and a command FS M which executes the commands read from the command memory IRAM.

In one embodiment of the gateway according to the invention, a message vector NV additionally has a time difference t between the time of an internal or external event to be triggered by the associated message N and a time of the next internal event EV _mt to be _triggered by the associated message N.

In one embodiment of the gateway according to the invention, the gateway control unit has a counter Z as an internal timer for triggering an internal event EV _mt .

In one embodiment of the gateway according to the invention, the buses are formed by serial buses.

In one embodiment of the gateway according to the invention, each communication module has:

a communication protocol unit connected to the serial bus for conversion between data packets DP and messages, each consisting of a plurality of data words DW;

a message forwarding unit for forwarding messages between at least one message store and the communications protocol unit and buffers;

a plurality of interface units each connected to an associated system bus of the gateway, each interface unit being connected to at least one associated buffer memory buffering a message, a transmission of Data words DW over several system buses and their associated interface units from and to the buffer memories of the interface units at the same time without waiting time.

In one embodiment of the gateway according to the invention, the serial bus is a fieldbus.

In one embodiment of the gateway according to the invention, the fieldbus is a CAN (Controller Area Network) bus.

In one embodiment of the gateway according to the invention, the field bus is a LIN (Local Interconnect Network) bus.

In one embodiment of the gateway according to the invention, the fieldbus is a FlexRay bus.

In one embodiment of the gateway according to the invention, the serial bus is an Ethernet bus.

In one embodiment of the gateway according to the invention, each of the two system buses has an associated system bus master.

In one embodiment of the gateway according to the invention, the message forwarding unit of a communication module signals the receipt of a word-wise transmitted message via the system bus to the system bus master of the system bus.

In one embodiment of the gateway according to the invention, the message routing unit confirms to the system bus master the receipt of a message to be transmitted by means of signals after it has requested the information.

In one embodiment of the gateway according to the invention, a message received from the respective system bus, which is buffered in a buffer memory and forwarded to the message memory by the message forwarding unit, has at least one flag bit for signaling readiness for transmission via the serial bus. In the following, preferred embodiments of the gateway according to the invention are described with reference to the attached figures for explaining characteristics essential to the invention.

Show it:

Figure 1: a communication module according to the prior art;

Figure 2: a gateway according to the prior art;

FIG. 3 shows a block diagram of a possible embodiment of the gateway according to the invention;

FIG. 4 shows a block diagram of a possible embodiment of a communication module within the gateway according to the invention;

FIG. 5 shows a block diagram of a possible embodiment of a gateway control unit contained in the gateway according to the invention;

FIG. 6 shows a diagram for representing a memory content of a vector memory contained in the gateway according to the invention;

Figure 7 is a diagram showing the data content of the instruction memory included in the gateway according to the invention;

FIG. 8 shows a signal diagram to illustrate an example of message forwarding by the gateway according to the invention;

FIG. 9 shows a signal diagram to illustrate a further example for message forwarding by the gateway according to the invention;

FIG. 10 shows a signal diagram to illustrate a further example of message forwarding by the gateway according to the invention;

FIG. 11 shows a signal diagram to illustrate a further example for forwarding messages through the gateway according to the invention; FIG. 12 shows a signal diagram for illustrating a further example for forwarding messages through the gateway according to the invention.

As can be seen from FIG. 3, the gateway 1 according to the invention has a plurality of communication modules 2-i, which can each be connected to a serial bus 3-i. The serial buses 3-i are, for example, a field bus or an Ethernet bus. Data is transmitted as messages via the serial buses 3-i. Transferred data packets or messages include administrative or header data as well as payload data. The inventive gateway 1 according to the embodiment shown in FIG. 3 has a plurality of master units, wherein a first master unit is formed by a gateway control unit 4-1 and a second master unit is formed by a CPU 4-2. The two master units 4-1, 4-2 assume different functions. In the embodiment illustrated in FIG. 3, the gateway control unit 4-1 is responsible for the data transfer between the various communication modules 2-i. The other master unit, by a processor 4-2 consisting of a

Host CPU and an internal memory RAM is formed, performs the actual data processing, for example, a built-in next to the gateway controller function. In the embodiment shown in Figure 3, each master unit 4-1, 4-2 preferably has its own system bus 5-1, 5-2. Each system bus 5-1, 5-2 in turn has its own data, address and control bus. Within the gateway 1, the data is transmitted word by word in one possible embodiment, the length of a data word DW corresponding to the bus width of the respective data bus of the system bus. In one possible embodiment, the communication modules 2-i have a preferably associated interface for each system bus 5-i.

FIG. 4 shows a possible embodiment of a communication module 2-i. The communication module 2-i is used to connect a serial bus 3 via an interface, wherein the communication module 2-i for each internal system bus 5-i of the gateway 1 has its own separate interface 2a, 2b. In the embodiment shown in FIG. 4, the communication module 2-i has a first interface 2a for connection to the system bus 5-1, whose master unit is formed by the gateway control unit 4-1. In addition, the communication module 2-i has a further interface 2b for connection to the system bus 5-2 of the gateway 1, whose bus master is formed by the host CPU of the processor 4-2. Connected to the external serial data bus 3-i is a communication protocol unit 2c of the communication module 2-i. The communication protocol unit 2c carries out a conversion between data packets or messages which are transmitted externally via the serial data bus 3-i and internally sends messages or messages with the help of the message handler, which can each consist of one or more data words DW.

The communication module 2-i in FIG. 4 also contains a message forwarding unit or message handler 2d for forwarding messages between at least one internal message memory or message RAM 2e and the communication protocol unit 2c and various buffer memories 2f, 2g via internal data lines 2h , The storage capacity of a buffer memory 2f, 2g preferably corresponds to the data volume of an internal message to be transmitted, as well as further administration data. The communication module 2-i has a plurality of interface units 2a, 2b, which are each connected to an associated system bus 5-i of the gateway 1. In this case, each interface unit 2a, 2b is connected to at least one associated buffer memory 2f, 2g in which at least one message or message or a message object MO can be buffered.

The access of the gateway control unit 4-1 to a message object MO or a message N takes place via the gateway interface 2a and its associated interface register 2f. The CPU 4-2 accesses messages or message objects via the customer interface 5-2 and its associated interface register 2g. Thus, both of the gateway control unit 4-1 and of the processor unit 4-2 access to all messages or message objects without mutual interference possible.

FIG. 5 shows a possible embodiment of a gateway control unit 4-1 contained in the gateway 1 according to the invention. The gateway control unit 4-1 is connected via the associated system bus 5-1 for exchanging messages with the communication modules 2-1. In this case, it receives from each communication module 2-i the local occurrence of a message N to be routed or of a message object MO to be routed as an external event EV _ext . As can be seen from FIG. 3, each communication module 2-i is connected to at least one display line for displaying an event or an event with the gateway control unit 4-1. In one possible embodiment, the communication module 2-i shown in FIG. 4 has a plurality of parallel message registers for each interface for storing one message per message register. In one possible embodiment, the messages are divided into several groups, for example in m groups. In one possible embodiment, the number of the intended message groups within a communication module is 2-im = 4. The message handler 2d of the communication module 2-i shows, when an external event EV _{ext occurs} , for example the receipt of a message to be forwarded from the gate. way control unit 4-1 via a corresponding display line. In one possible embodiment, a separate display line is provided for each group of messages, for example m = 4 display lines. If the number of communication blocks 2-i N is 2 assuming that all communication blocks 2-i have an identical N, and the number of groups within the communication block is 2-in, then the number of display lines for external events or events is N x m ,

As can be seen from FIG. 5, the gateway control unit 4-1 is connected to the communication modules 2-i via the system bus 5-1 and receives from each communication component 2-i the occurrence of a message to be routed there as an external event EV _ext via a display line. The gateway control unit 4-i contains a vector memory (VRAM) whose memory contents are shown in FIG. In addition, the gateway control unit 4-1 includes an instruction RAM (IRAM) for storing instructions whose memory contents are shown in FIG. The central control element of the gateway control unit 4-1 is formed by a finite state machine (FSM), which is composed of an event FSM and a separate command FS M. Furthermore, the gateway control unit 4-1 contains a status register SR and a counter Z as a timer for triggering internal events EV _mt . The gateway control unit 4-1 is connected to the system bus 5-1 via a system bus interface SBI. The vector memory or VRAM, as shown in FIG. 6, essentially contains three memory areas. Configuration data of the communication modules 2 are located in a first memory area, ie for each communications module 2-i, a communications module vector KBV is stored per message group. The communication module vector KBV stores for the associated communication module 2-i that time ZP which indicates the next expected internal event EV _mt for a message N buffered in the communication module 2-i. In addition, the communication module vector KBV has a vector jump address VSA on a message vector NV for the corresponding message N. In addition, each communication module vector KBV has further configuration data for the corresponding communication module 2-i. A possible configuration date is formed by a CC flag which indicates whether a communication module 2 or communication controller is activated or deactivated. If the communication module 2 has several groups of messages N, a communication module vector KBV is provided for each group of messages within the communication module 2.

The vector memory VRAM within the gateway control unit 4-1 also contains a second memory area in which for each message N or for each message MSG configuration ration data are stored as message vectors NV. For each relevant message or message N, a message vector NV is stored in the vector memory VRAM. For each message N _cached in a communication module 2-i, a corresponding alert vector NV is provided or stored in the VRAM indicating a configurable period ZP of an internal message EV _{ιnt to be triggered} by the associated message N and a command _{jump address} BSA.

In one possible embodiment of the gateway 1 according to the invention, the message vector NV additionally has a time difference Δt between the time ZP of an internal or external event to be triggered by the associated message N and a further time ZP of the next internal event to be triggered by the associated message N.

In addition to the memory areas for the communication module vectors KBV and the second memory area for the message vectors NV, the vector memory VRAM also has a freely available third memory area in which variables are buffered and in which constants and flags are stored. In addition, the freely available third memory area of the vector memory VRAM is used for data exchange with the CPU 4-2.

The message vectors NV stored in the second memory area of the vector memory VRAM have a command jump address BSA, by which at least one command subroutine within the command memory IRAM is addressable. For each message N, a message vector NV is stored in the second memory area of the vector memory VRAM, each having a command jump address BSA to a subroutine within the instruction memory IRAM. Such a command sequence or subroutine is stored in the memory area assigned to the respective message in the IRAM. The size of the storage area is preferably variable. Furthermore, the position of the memory area within the instruction memory IRAM is also variable.

In the gateway control unit 4-1, in addition to the vector memory VRAM and the instruction memory IRAM, a sequence control FSM is provided which has an event FSM and a command FSM. When an internal or an external event occurs, the event FSM of the sequence evaluates the vectors stored in the vector memory VRAM, ie the communication module vectors KBV and the message vectors NV, and updates the times indicated in the respective vectors. In addition, the gateway control unit 4-1 has a configuration or status register SR which inter alia stores the time ZP for the closest expected event of all expected internal events EV _mt for all messages _buffered in the communication modules 2-i ,

The instruction FS M within the sequencer executes the instructions read from the instruction memory IRAM. Upon occurrence of an internal event EV _mt whose time ZP in a status register SR or at the occurrence of an external event EV _ext , the flow control of a communication block 2-i is displayed, the event FSM reads the associated communication block 2-i communication block Vector KBV from the first memory area of the vector memory VRAM. A read communication module vector KBV contains a vector jump address VSA on a message vector NV in the second memory area of the vector memory VRAM. For each communication block 2-i or for each group of messages N within a communication block 2-i, a separate communication block vector KBV is provided. In a sense, this forms a hash table for the message vectors NV in the second memory area of the vector memory VRAM. By means of the vector jump address VSA, the event FSM of the sequence controller reads out the addressed message vector NV from the second memory area of the vector memory VRAM and then addresses, with the command jump address BSA contained therein, a subroutine within the instruction memory IRAM. The addressed instruction (s) are read from the instruction memory IRAM and executed by the instruction FSM within the sequencer, the instruction FSM also including the timing ZP indicated in the vectors, ie the message vectors NV and communication module vectors KBV according to the NV and KBV vectors, preferably updated by the event FSM or instructions executed.

The gateway control unit 4-1 illustrated in FIG. 5 has a counter Z as an internal timer for triggering an internal event.

In the gateway control unit 4-1 according to the invention, a distinction is made between external events EV _ext and internal events EV _mt . External events EV _ext are triggered by the communication modules 2-i, in particular upon receipt of a message N to be relayed or a message packet DP to be forwarded. The internal event EVi _nt are triggered by the timer or time counter Z. These internal events serve, for example, for cyclically sending messages or debouncing or debouncing received message bursts or for sending time-out messages. Messages when an expectation period is exceeded. In a possible embodiment of the gateway 1 according to the invention, the message vector NV stored in the vector memory VRAM has, for example, the following information, namely a reference to the data object to be sent or the message N, one for each relevant message buffer memory within a communication module 2-i Jump address for executing a specific instruction sequence, the next internal event and a difference time for calculating the subsequent internal events, as well as information data for control and status information.

By means of the data stored in the vector memory VRAM, in particular defined points in time ZP, using the counter Z, virtually any time sequence can be implemented by the gateway control unit 4-1 according to the invention in order to transmit data between two or more buses 3 via the gateway 1. In this case, the timer Z or counter is initialized when starting the system, so that the counter divides the CPU clock in a favorable for the entire system time grid. The current counter value of the counter Z is used to check the message objects in the communication module vectors KBV and message vectors NV of the vector memory VRAM to trigger the transmission of a message N. In this case, the count value of the timer Z is compared with the time values stored in the vector table. If the timer value of the counter Z is greater than or equal to the respectively stored time value or time and if the corresponding message N or the message object is a transmission object, the system jumps to the specified address and executes the commands specified there. If the message N or the message object is a receive object, it is checked whether the receive object should have already been received or not. If the receive message object is not received within the expected time, a time-out is triggered by the gateway 1 according to the invention and a corresponding time-out message is issued. Subsequently, time information is updated by the sequential control system, whereby the calculation is based on the previous time specifications with the specified cycle times. By means of the newly calculated times, it is determined when a message N or message should be sent again or the next time-out occurs.

In the case of an immediate or immediate forwarding of a message N, the comparison of the time value specified by the counter Z is not necessary. It is communicated to the gateway control unit 4-1 by the communication module 2-i that a message N has been received by the communication module 2. Subsequently, the sequence control FSM searches in the vector memory VRAM for a corresponding entry, ie a communication block vector KBV associated with the message N. This vector KBV points to a message vector NV in the second memory area of the vector memory VRAM. This contains a command jump address BSA to a routine in which the routing commands are stored.

The evaluation of the time value, which is supplied by the counter Z, for the calculation of the new expected time values or expected times ZP as well as the control of the various communication modules 2-i is taken over by the automatically running sequence control or finite state machine. With the aid of a counter Z and a status register SR, the sequence control FSM checks all message objects or messages to be sent, and additionally checks the reception of external new messages N by the communication blocks 2-i. When an internal event occurs, for example the cyclical transmission of a message or an external event, for example the receipt of a message N to be forwarded by a communication module 2, the configured routing instructions are executed and the various communication modules 2 are activated. As a result of the connection of the communication modules 2 via the customer interface 5-2, it is always possible for the CPU 4-2 in the gateway 1 according to the invention to access messages N in the communication module or bus modules 2-i. The messages N are preferably buffered in the communication module 2-i or in the bus modules of the serial buses 3-i and are not loaded into the gateway control unit 4-i in the automatic route gateway 1 according to the invention in one possible embodiment , A transmission of the messages between the communication modules or bus modules 2-i takes place in a possible embodiment of the gateway 1 according to the invention by a further bus, namely a ring bus, which connects the various communication modules in a ring with each other. The CPU 4-2 can access all the cached message objects or messages N within a communication module 2-i via the interface register 2g, while the gateway control unit 4-2 performs the access via the second interface register 2f.

Figure 8 shows signal flow diagrams to illustrate the operation in a possible embodiment of the gateway according to the invention 1. In the status register SR of the gateway control unit 4-1 is the time ZP cached, at which the next expected event, ie the closest expected event of all expected internal events for all temporarily stored in the communication module 2-i messages N occurs. In the status register SR, the closest internal event or the internal event EV _ιnt to be expected by the gateway control unit 4-1 is thus _buffered . As soon as the timer Z outputs a count, which the The occurrence of this event indicates (t _nxtE vτaiι <TIMER) determines the event FSM within the flow control the associated communication blocks 2-i and evaluates all stored in the vector memory VRAM communication block vectors KBV for the respective group within the corresponding communication block 2-i. In the simple example shown in FIG. 8, the communication module 2 has two messages or message groups, namely a group GRP1 and a group GRP2. The event FSM evaluates in step S1 the time event triggering communication module vector KBV, which is stored in the first memory area of the vector memory VRAM, and finds in the example shown in FIG. 8 the communication block vector KBV for the second group GRP2 cached messages within the communication module 2. In a further step S2, the time event triggering message vector NV is read out and evaluated in the second memory area of the second vector memory VRAM. In the example shown in FIG. 8, the vector triggering the event EV is the vector of the first message N or of the message object (message object 1) within the second group GRP2 of the triggering communication module 2-i.

In a further step S3, the next time event or the next internal event for this message object or message object MO is calculated:

^ nxtEV + \ - Grp _n -MO _m ~ KxIEVt-GrP _n -MO _1n ⁺ ^ GrP _n -MO _1n

This is possible since each message vector NV additionally has a time difference t between the time ZP of an internal event to be triggered by the associated message N or the message object NO and a time ZP of the next internal event to be triggered by the corresponding message N.

In a further step S4, the next time event or the next internal event EVi _n t is searched by the event FSM:

tnextEV-GRPn = minilTIUm (tpxtEV-GRPn-MOm): ITl € [1 ... ITl _max ]

In a further step S5, an update of the time indication t _nxtE vG _RPn in the communication module vector KBV within the first memory area of the vector memory VRAM takes place from the determined times. In a further step S6, the next time event or the next expected internal event can be selected via all groups of stored messages or message objects MO via all communication blocks 2-i. In the example shown in FIG. 8, this is time t _m for the first group GRP within the first communication block.

In a subsequent step S7, in the status register SR, this instant t _{m is} stored as the instant t _{n +} i, the next expected internal event or internal event. As soon as the counter Z reaches this time t _{n +} i, the process illustrated in FIG. 8 begins again, ie steps S1-S7 are carried out again.

FIG. 9 shows two time signal diagrams, wherein the upper signal diagram shows a message or message object MO arriving at the gateway according to the invention, to which second lower time signal diagram shows messages issued by the gateway 1 according to the invention to another serial bus. In the example shown in Figure 9, a message MO received on a first serial bus 3-i is forwarded directly via another serial bus 3-j, with a slight time delay t _GD deia _y occurring. As can be seen in FIG. 9, the transmission cycle time t is _zyk | _Us constant, ie received message objects N (cyclic or spontaneous) are forwarded cyclically.

FIG. 10 shows the cyclic transmission of messages N by the gateway 1 according to the invention, even if the received message objects N are not received cyclically. The last received message N ₁ is transmitted continuously cyclically within a constant cycle time to a bus 3-i.

FIG. 11 shows the immediate forwarding of a message with time-out, ie the absence of an expected message is monitored. As can be seen from FIG. 11, a message N or a message object is received via a first serial bus 3-i and forwarded directly to an output bus. At time t _A , it is determined that the expected message has not arrived, and gateway 1 generates a time out message, which is delivered as an output message to the output bus to indicate the absence of the expected message. For carrying out the process illustrated in FIG. 11, the sequence control does not execute the steps S 1 shown in FIG. 8 when receiving such a message (message correctly received in the time frame) and S 3 when the message N (triggering of the time-out) fails, but only in each case the remaining steps. Figure 12 shows the debouncing of message bursts. In the example illustrated in FIG. 12, the gateway 1 contains a message several times within a predetermined window t _DEB and forwards only the first message of the group to another serial bus 3-i. The remaining messages within the burst are suppressed by the gateway 1. In the function or the corresponding operating mode shown in FIG. 12, in a first pass, a so-called debounce active bit is set as the configuration data in the message vector NV of the vector memory VRAM for receiving a message. Once the Debou nee-active bit is set, the process shown in Figure 8, wherein the step S3 is omitted. Finally, the debounce active bit is reset in the configuration data.

As can be seen from FIGS. 9, 10, 11, 12, the gateway 1 according to the invention is suitable for various operating modes or functions for forwarding or processing messages which are transmitted between different buses 3-i, 3-j. In the gateway 1 according to the invention, the CPU load for automatic checking for timeouts and the required transmission of messages or the combination of several messages is considerably reduced by the gateway control unit 4-1 as a function of the occurring data volume. The sending of the messages or of the message object and their checking for possible time-outs is performed by the gateway control unit 4-1 independently of the processes running in parallel in the CPU 4-2. This achieves much smaller jitter and latency, allowing processes to be started and executed more accurately in the network. In this case, each message object or each message N can be configured independently of other networks and independently of other message objects in the individual communication modules or bus modules. By means of vectors used in the gateway 1 according to the invention, there is a particularly high degree of flexibility with regard to the configurability of the gateway 1 according to the invention. By forming groups of storable messages N within each communication module 2, further interleaving is possible, as a result of which Flexibility is further increased. In addition, the speed of search for messages to be processed is significantly shortened and the compact definition of a communication process minimizes the memory requirements for all message objects. The gateway 1 according to the invention opens up the possibility that external events or events co-determine or control the timing of internal events or internal events. The gateway 1 according to the invention transmits data between fieldbuses or serial buses 3 automatically without burdening the CPU 4-2. In this case, the periodic transmission within a predetermined time frame, the immediate transmission after receiving a message, the check for absence of a message and debouncing messages. The transmission of the messages N takes place without direct control by the CPU. However, the CPU 4-2 always receives access to the forwarded or used message objects or message objects, without interrupting the automatic routing of the messages. The transmission or forwarding of the message objects or the messages N takes place in the gateway 1 according to the invention independently of software latencies and the current load of the CPU 4- 2.

Claims

claims

1. Gateway for automatic routing of messages between buses (3) with:

(A) a plurality of communication modules (2) for buffering and transmitting messages (N) via the buses (3); and with

(B) a gateway control unit (4-1), which is connected via a system bus (5-1) for the exchange of messages (N) with the communication modules (2), and of each communication module (2) the local occurrence of a message to be routed (N) is displayed as an external event (EV _ext ),

wherein the gateway control unit (4-1) comprises:

(bl) a vector memory (VRAM) having a first memory area for storing communication block vectors (KBV), wherein for each communication block (2) a communication block vector (KBV) is provided, the time (ZP) of a next expected internal event (E-V ₁ J for a message (N) latched in the communication module (2) and a vector jump address to a message vector (NV) stored in a second memory area of the vector memory (VRAM), wherein for each in the Communication module (2) cached message (N) a corresponding message vector (NV) is stored, indicating a configurable time (ZP) of an associated message (N) internal event (EV ₁ J and a command jump address;

(b2) an instruction memory (IRAM) for storing instructions addressable by the instruction jump address specified in the message vector (NV); and

(b3) a sequence control (FSM) which, when an internal event occurs (EV, J whose time (ZP) in a message vector (NV) of a nication block (2) cached message (N) is specified, or when an external event (EV _ext ), the sequence control (FSM) by a communication block (2) is displayed, the communication block vector associated with the respective communication block (2) (KBV) read from the first memory area of the vector memory (VRAM) and read the instruction jump address of the addressed message vector (NV) from the second memory area of the vector memory (VRAM) by means of the vector jump address contained therein and then by means of the read command jump address at least one command from the command memory ( IRAM) and executes, where in the vectors (NV, KBV) specified

Times (ZP) to be updated.

2. Gateway according to claim 1, wherein the gateway (1) comprises a processor (4-2) which is connected via a separate second system bus (5-2) with the communication modules (2).

The gateway of claim 1, wherein the scheduler (FSM) of the gateway controller (4-1) comprises:

an event FSM (Finite State Machine) which, upon occurrence of an internal or external event, evaluates the vectors (KBV, NV) stored in the vector memory (VRAM) and updates the times indicated in the vectors; and

an instruction FSM (Finite State Machine) which executes instructions read from the instruction memory (IRAM).

4. Gateway according to claim 1, wherein the message vector (NV) additional a time difference (t) between the time (ZP) of one of the associated message (N) to be triggered internal event and a time (ZP) of the next of the associated message (N ) has triggered internal event.

5. Gateway according to claim 1, wherein the gateway control unit (4-1) has a counter (Z) as an internal timer for triggering an internal event (Ev ₁ J has.

6. Gateway according to claim 1, wherein the gateway control unit (4-1) has a status register (SR) which temporarily stores the time (ZP) for the next expected event of all expected internal events for all in the communication blocks (2) - certs messages (N).

The gateway of claim 1, wherein the buses (3) are serial buses.

8. Gateway according to claim 2, wherein each communication module (2) comprises:

(A) to the serial bus (3) connected communication protocol unit (2c) for conversion between data packets (DP) and messages (MSG), each consisting of a plurality of data words (DW);

(b) a message forwarding unit (2d) for forwarding messages (MSG) between at least one message memory (2e) and the communication protocol unit (2c) and buffer memories (2f, 2g);

(c) a plurality of interface units (2a, 2b) each connected to an associated system bus (5-1, 5-2) of the gateway (1), each interface unit (2a, 2b) having at least one associated one Buffer memory (2f, 2g) which temporarily stores a message (MSG);

wherein a transmission of data words (DW) over a plurality of system buses (5-1, 5- 2) and their associated interface units (2a, 2b) from and to the buffer memories (2f, 2g) of the interface units (2a, 2b) at the same time without waiting time.

9. Gateway according to claim 7, wherein the serial bus (3) is a field bus.

10. The gateway of claim 9, wherein the field bus is a CAN (Controller Area Network) bus.

The gateway of claim 9, wherein the serial bus (3) is an Ethernet bus.

12. Gateway according to claim 2, wherein each of the two system buses (5-1, 5-2) an associated system bus master (4

1, 4-2).

13. Gateway according to claim 8, wherein the message forwarding unit (2d) of a communication module (2) receives the receipt of a system bus (5-1, 5-2) word-wise transmitted message to the system bus master (4-1, 4-2) of the system bus signals.

14. Gateway according to claim 8, wherein the message forwarding unit (2d) of a communication module the system bus master (4-1, 4-2) confirms the receipt of a message to be transmitted by signals, after the latter has requested the information.

15. The gateway as claimed in claim 8, wherein a message received by the respective system bus (5-1, 5-2), which is buffered in a buffer memory (2f, 2g) and sent to the message memory (2e) by the message forwarding unit (2d). is forwarded to signaling a ready to send via the serial bus (3) has at least one flag bit.