DE102005048583A1 - Subscriber and communication controller of a communication system and method for data transmission in a subscriber of the communication system - Google Patents

Abstract

The invention relates to a subscriber (900) of a communication system, the subscriber (900) having a microprocessor (102), a communication controller (750) and a peripheral bus (820), and the microprocessor (102) via the peripheral bus ( 820) is in communication with the communication controller (750) and is connected via the communication controller (750) to a communication connection (101) of the communication system via which messages are transmitted. In order to optimize the connection of the microprocessor (102) to the communication controller (750), it is proposed that the communication controller (750) have an active interface (834) via which the communication controller (750) connects to the peripheral bus (820) and has a logic which enables independent data transmission between the communication controller (750) and the microprocessor (102) via the active interface (834) and the peripheral bus (820).

Description

The The present invention relates to a participant (so-called host) of a Communication system. The participant has a microprocessor (so-called host CPU (Central Processing Unit)), a communication controller and a peripheral bus. The microprocessor is above the Peripheral bus connected to the communication controller and is over the communication controller to a communication link of Communication system connected via which messages are transmitted.

The Invention also relates a communication controller (so-called Communication Controller; CC) a participant (so-called host) of a communication system. Of the participants has a microprocessor (so-called host CPU), the communication controller and a peripheral bus. The communication controller is stopped on the one hand over the peripheral bus communicates with the microprocessor and is otherwise connected to a communication link of the communication system via which Transmit messages become.

Finally, concerns the present invention also provides a method of transmission of data within a subscriber (so-called host) of a communication system. The data is between a microprocessor (host CPU) and a Communication controller over transmit a peripheral bus. Of the Communication controller is connected to a communication link via which Transmit messages become.

The Networking of control units, Sensors and actuators with the help of a communication system and a trained as a bus communication link has in recent years in modern motor vehicles but also in mechanical engineering, especially in the machine tool sector, and in the field of automation, drastically increased. Synergy effects through distribution of functions on several controllers can be achieved. This is called distributed systems. The communication between different participants finds more and more about a trained as a bus system communication system instead. Of the Communication traffic on the bus system, access and reception mechanisms as well as error handling will be over a protocol regulated.

One well-known protocol for this is the FlexRay protocol, where at the moment based on the FlexRay protocol specification v2.0. The FlexRay protocol defines a fast, deterministic and fault tolerant bus system, especially for the use in a motor vehicle. The data transfer according to the FlexRay protocol takes place after a Time Division Multiple Access (TDMA) method. The data transfer over the Communication connection takes place in regularly recurring transmission cycles, each in multiple data frames, also referred to as time slots be subdivided. To the participants or to be transferred Messages are assigned fixed time slots in which they have one have exclusive access to the communication connection. The time slots repeat themselves in the specified transmission cycles, so that the time at which a message is transmitted over the bus can be predicted accurately and the bus access deterministic he follows.

Around the bandwidth for the message transfer FlexRay divides the transmission cycle optimally on the bus system, which can also be referred to as a cycle or bus cycle, into one static and a dynamic part. The fixed time slots are located doing so in the static part at the beginning of a bus cycle. In the dynamic part the time slots are allocated dynamically. This is now the exclusive Bus access only for one short time, for one or more so-called mini slots. Only if within If a minislot takes a bus access, the timeslot becomes the needed Time extended. Thus, bandwidth is only consumed when it is actually needed.

FlexRay communicates via two physically separate lines of the communication link with a maximum data rate of 10 MBit / s (10 MBaud). It is every 5 ms, in some communication systems even every 2.5 ms completed a bus cycle. The two channels correspond to the physical Layer, in particular the OSI (Open System Architecture) layer model. The both channels serve mainly the redundant and thus fault-tolerant transmission of messages, can but also different messages transmitted, which then would double the data rate. FlexRay can also be operated at lower data rates.

Around to realize synchronous functions and bandwidth through small ones distances to optimize between two messages the participants or the distributed components in the communication network a common Time base, the so-called global time. For the clock synchronization will be Transmit synchronization messages in the static part of the cycle, using a special algorithm according to the FlexRay specification Local time of a participant is corrected so that all local Clocks sync to a global clock.

One FlexRay device, also known as FlexRay network node or host can be included a participant or Host processor, a FlexRay or communication controller as well a bus monitoring a so-called Busguardian. It delivers and processes the Subscriber processor the data transmitted via the FlexRay communication controller and transmit the FlexRay communication link become. For Communication in a FlexRay network can be messages or message objects with e.g. up to 254 bytes of data can be configured.

For coupling a FlexRay communication connection, via which messages are transmitted, to a FlexRay subscriber is stored in the DE 10 2005 034 744 which was not yet published at the filing date of the present invention, a FlexRay communication module is used, which is connected via a subscriber interface to the subscriber and via another connection to the communication link. In this case, an arrangement for storing the messages is provided for transmitting the messages between the subscriber and the communication link in the communication module. The transmission is controlled by a state machine.

In The communication block is an interface block provided of two parts, wherein the one component independent of the participant and the other sub-module is subscriber-specific. The participant-specific Partial block, also known as Customer CPU Interface (CIF) is a custom participant in the form of a links user-specific host CPU with the FlexRay communication block. The participant independent Submodule, also referred to as Generic CPU Interface (GIF), represents a generic, that is, general, CPU interface over which by means of corresponding subscriber-specific partial modules, So Customer CPU Interfaces (CIFs), different custom Have host CPUs connected to the FlexRay communication block. This is a problem-free adaptation of the communication module possible to different participants, as dependent From the participant only the subscriber-specific sub-module varies must be while the participant-independent Submodule and the rest of the communication block always trained the same can be. With the help of the communication module, it follows a standard interface for connecting any FlexRay device to a FlexRay communication link, wherein the interface by simple variation of the subscriber-specific Sub-modules to any trained or kind participants flexible. It can the sub-blocks also within one interface block each in software, so each sub-module as a software function, will be realized.

The State machine in the FlexRay communication block can be fixed wired in hardware. The sequences can also be fixed in hardware be wired. Alternatively, the state machine in the communication block via the Subscriber interface also freely programmable by the subscriber be.

The Information preferably contains the access type and / or the Access type and / or the access address and / or the data size and / or control information to the data and / or at least one information for data security.

According to the prior art, the message memory of the FlexRay communication module is preferably designed as a single-ported RAM (Random Access Memory). This RAM memory stores the messages or message objects, ie the actual user data, along with configuration and status data. The exact structure of the message memory of the known communication module can the cited document DE 10 2005 034 744 be removed.

To In the prior art, within the subscriber is the microcontroller, the microprocessor (called host CPU), a memory (e.g., Random Access Memory; RAM) and a core bus between the microprocessor and the memory includes, over a passive and an active interface as a so-called master to the Peripheral bus connected. about the passive interface, the microcontroller can only commands and receive data from other users of the peripheral bus. About the Active interface allows the microcontroller itself data and commands to other participants of the peripheral bus. A connection a subscriber to the peripheral bus via a passive interface is synonymous with a connection of the participant as so-called. Slave. A connection of a subscriber via an active interface corresponds to a connection of the participant as a so-called master. at a known communication system is a communication controller is over a passive interface as a so-called slave connected to the peripheral bus.

Of the Communication controller adjusts the connection of the subscriber Communication link. He has a message memory, in the newly received messages from the communication link filed and messages to be sent on the communication link be read out. The microprocessor can be over the passive interface of the communication controller to the stored message objects access.

Of the Microprocessor configures, controls and controls the communication controller. The microprocessor reads received messages, evaluates them, calculates new messages and writes the messages for shipping via the communication connection. For data transmission within the subscriber transmits the microprocessor the data word by word from the communication controller into the memory of the microcontroller. This occurs in the usual today high clock rates of the microprocessor several wait cycles, during which the microprocessor waits for the end of the data transfer and none can pursue other tasks.

It is also known to relieve the microprocessor of the microcontroller a subscriber of the communication system a DMA (Direct Memory Access) controller via a passive and an active interface as a so-called master to the peripheral bus to join. The DMA controller can handle the data transfer between the memory of the microcontroller and the communication controller. He is configured and started by the microprocessor. Thereafter, the DMA controller transmits data word by word from the communication controller into the memory of the microcontroller. The end of the data transfer is communicated to the microprocessor by means of an interrupt, whereupon the microprocessor de process for the next message starts again. The processing of interrupts generates a large number of CPU commands, through which a large part of the computational and memory resources of the microprocessor is bound. It also increases due to frequent interrupts the possible Jitter (temporal uncertainty regarding the duration of execution) of interrupted Software tasks.

Of the The present invention is therefore based on the object, the data transmission within a subscriber of the communication system between the Microprocessor and the communication controller to optimize, in particular the number of wait cycles in the microprocessor and the interrupt load be reduced.

to solution This task is based on the participants of the aforementioned Art suggested that the communication controller an active Interface, over the communication controller communicates with the peripheral bus, and having a logic which provides independent data transfer between the communication controller and the microprocessor (host CPU) via the active interface and the peripheral bus.

Advantages of invention

Thus, according to the invention proposed, the communication controller not as so-called. Slave, but as master to the peripheral bus. In addition, the communication controller receives an intelligence in the form of a logic that enables him the data transmission between a message memory of the communication controller and to independently coordinate and allocate to a memory of the microcontroller Taxes. The logic allows the communication controller a certain DMA functionality mediated.

The The invention can be applied to arbitrary users of any communication system be used. The invention will be described by way of example below describe a FlexRay Kommunikationssytems. This relation to However, the FlexRay protocol should not be understood as limiting. Of course you can the invention also in participants of a MOST (Media Oriented Systems Transport) -, a CAN (Controller Area Network) -, a TTCAN (Time Triggered CAN) -, a LIN (Local Interconnect Network) - or any other known communication system can be used.

Of the Microprocessor configures, controls and controls the communication controller. The microprocessor already reads in the message memory of the communication controller received and automatically into the memory of the microcontroller copied message objects, evaluates them, calculates new message objects and puts them in the memory of the microcontroller. Also starts the microprocessor transfers to the message memory of the communication controller, in turn automated by the communication controller according to the invention carried out becomes.

In addition to passive interface has the inventive communication controller via a active interface, via the one embedded in the communication controller logic independently both Message objects from the message memory of the communication controller Read and write to the memory of the microcontroller as well Read message objects from the memory and into the message memory can write.

According to an advantageous development of the present invention, it is proposed that the communication controller comprises a message memory for temporarily storing messages from the communication connection or for the communication connection, the logic of the communication controller independently reading out data from the message memory of the communication controller and storing the data in the microprocessor (host CPU), as well as an independent reading of data from the microprocessor (host CPU) and storing the data in the message memory of the communication controller allows.

According to one preferred embodiment of Invention it is proposed that the microprocessor (host CPU) a memory element is assigned, the logic of the communication controller an independent one Reading out data from the communication controller and storing the data in the memory element of the microprocessor (host CPU), as well as an independent read data from the memory element of the microprocessor (host CPU) and storing the data in the communication controller.

According to one particularly advantageous embodiment of the present invention It is proposed that the communication controller a communication block comprising a message memory for caching Messages from the communication link or for the communication link wherein the logic of the communication controller is a self-contained data transmission between the communication module and the microprocessor (host CPU), preferably between the message memory of the communication module and the memory element associated with the microprocessor (host CPU) (RAM), over allows the peripheral bus.

According to one preferred embodiment of Invention, the communication module at least one between buffer memory arranged in the message memory and the peripheral bus, preferably at least one input buffer and at least an output buffer, on, the logic of the communication controller an independent one data transfer between the communication module and the microprocessor (host CPU), preferably between the at least one buffer memory of the communication module and the memory element associated with the microprocessor (host CPU) via which Periphery bus allows.

The Logic in the communication controller advantageously comprises a state machine, preferably a DMA state machine. The State machine is preferably implemented in hardware and in the communication controller hardwired. Of course However, the state machine can also be realized by software.

According to one another embodiment The invention proposes that the communication controller an arbiter, the concurrent accesses of the microprocessor (Host CPU) and the state machine to a message memory of the Communication controller or to a message memory of a FlexRay communication module arbitrated.

advantageously, the communication controller comprises control and / or status registers, on which the microprocessor (host CPU) for configuration, control and / or monitoring the data transmission can access.

Of the Subscriber is preferably part of a FlexRay communication system, in which a data transmission between the subscriber and others to the FlexRay communication link connected FlexRay participants according to the FlexRay protocol.

When another solution The object of the present invention is based on the communication controller of the type mentioned above proposed that the communication controller a active interface, via the communication controller communicates with the peripheral bus, and having a logic which provides independent data transfer between the communication controller and the microprocessor (host CPU) via the active interface and the peripheral bus.

According to one advantageous development of the invention it is proposed that the communication controller is part of a FlexRay communication system is in which a data transfer between the subscriber and others to the FlexRay communication link connected FlexRay participants according to the FlexRay protocol.

When yet another solution The object of the present invention is based on the method of the type mentioned above proposed that a logic of the communication controller for data transfer is caused and the logic then the data transfer between the communication controller and the microprocessor (host CPU) via a active interface of the communication controller and the peripheral bus independent controls.

According to an advantageous embodiment of the invention, it is proposed that the logic of the communication controller is caused by a command of the microprocessor (host CPU) of the subscriber for data transmission. This may be an interrupt command or a targeted to the communication controller start command. Alternatively, it is conceivable that the communication controller or the logic of the communication controller rule moderately checks the content of the message memory or the memory of the microcontroller for new data or checks the contents of certain registers that are set after receiving new data in the message memory and / or memory of the microcontroller, and optionally starts the data transfer.

According to one preferred embodiment of Invention it is proposed that the microprocessor (host CPU) on control and / or status registers of the communication controller accesses and so the data transfer configured, controlled and / or monitored. This reads the Microprocessor control and / or status parameters (depending on the state of the communication controller of this filed there or set be) from the register or sets such parameters (to control of the communication controller) in the register.

advantageously, For example, the logic of the communications controller includes a state machine where concurrent accesses of the microprocessor (host CPU) and the state machine to a message memory of the communication controller or arbitrated to a message memory of a communication block become.

• – Sichtbarmachen der empfangenen Daten in einem Pufferspeicher des Kommunikationscontrollers; und
• – Anlegen einer Kopie der empfangenen Daten in einem konfigurierbaren Adressbereich eines dem Mikroprozessor (Host-CPU) zugeordneten Speicherelements durch Schreibzugriffe über die aktive Schnittstelle.

Preferably, following receipt of new data from the communication link, the logic automatically initiates and controls the following steps:

• Visualizing the received data in a buffer memory of the communication controller; and
• - Creation of a copy of the received data in a configurable address range of the microprocessor (host CPU) associated memory element by write accesses over the active interface.

• – Erkennen eines Befehls oder mindestens eines gesetzten Bits in einem Kontroll- und/oder Statusregister des Kommunikationscontrollers;
• – Auslesen der Daten aus einer konfigurierbaren Adresse des Speicherelements;
• – Anlegen einer Kopie des ausgelesenen Datenobjekts in einem Pufferspeicher des Kommunikationscontrollers; und
• – Initiieren der Übertragung der Daten aus dem Pufferspeicher in einen Botschaftsspeicher des Kommunikationscontrollers bzw. eines Kommunikationsbausteins.

Furthermore, in order to send new data present in a memory element associated with the microprocessor (host CPU), the microprocessor (host CPU) preferably initiates a transfer of the data from the memory element into the communication controller and becomes independent of the logic of the communication controller initiated and controlled the following steps:

• - detecting a command or at least one set bit in a control and / or status register of the communication controller;
• - reading the data from a configurable address of the memory element;
• - Creating a copy of the read data object in a buffer memory of the communication controller; and
• - Initiate the transfer of the data from the buffer memory in a message memory of the communication controller or a communication block.

drawings

following With reference to the figures, further features and advantages of the invention explained in more detail. It demonstrate:

1 a communication module and its connection to a communication connection and a communication or host participant of a FlexRay communication system in a schematic representation;

2 a special embodiment of the communication module 1 as well as its connection in detail;

3 the structure of a message memory of the communication module 2 ;

4 to 6 the architecture and the process of a data access in the direction of the subscriber to the message memory in a schematic representation;

7 to 9 the architecture and process of data accessing from the message storage to the subscriber;

10 the structure of a message manager and finite state machines contained therein in a schematic representation;

11 Components of the communication block 1 and 2 as well as the subscriber and the corresponding data paths controlled by the message administrator in a schematic representation;

12 the access distribution to the message memory with respect to the data paths in 11 ;

13 a subscriber of a communication system according to the invention;

14 a communication controller of the subscriber 13 in detail; and

15 a known from the prior art participants of a Kommunikationsssytems.

description the embodiments

1 schematically shows a flex Ray communications module 100 for connecting a participant or host 102 to a FlexRay communication link 101 So the physical layer of the FlexRay. This is formed, for example, as a FlexRay data bus, which preferably has two transmission lines. This is the FlexRay communication block 100 over a connection 107 with the participant or participant processor 102 and about a connection 106 with the communication connection 101 connected. For problem-free connection on the one hand with respect to transmission times and on the other hand with regard to data integrity, essentially three different arrangements in the FlexRay communication module are schematically distinguished. It serves a first arrangement 105 for storing, in particular clipboard, at least part of the messages to be transmitted. Between the participant 102 and this first arrangement 105 is about the connections 107 and 108 a second arrangement 104 connected. Likewise is between communication connection 101 and the first arrangement 105 a third arrangement 103 about the connections 106 and 109 whereby a very flexible input and output of data as part of messages, in particular FlexRay messages in and out of the first arrangement 105 achievable with guaranteed data integrity at optimal speed.

In 2 is this communication block 100 in a preferred embodiment again shown in more detail. Also shown in more detail are the respective compounds 106 to 109 , For connecting the FlexRay communication block 100 to the FlexRay participant 102 or the host processor contains the second arrangement 104 an input buffer or input buffer 201 (Input Buffer IBF), an output buffer or output buffer 202 (Output buffer OBF) as well as an interface module consisting of two parts 203 and 204 , where the one component 203 participant-independent and the second sub-module 204 is subscriber specific. The subscriber-specific sub-module 204 (Customer CPU Interface CIF) connects a user-specific host CPU 102 So a custom participant 102 with the FlexRay communication block 100 , This is a bidirectional data line 216 , an address line 217 as well as a control input 218 intended. It is also provided with 219 an interrupt or interrupt output. The subscriber-specific sub-module 204 is associated with a subscriber-independent submodule 203 (Generic CPU Interface, GIF), ie the FlexRay communication block or the FlexRay IP module has a generic, ie general, CPU interface 203 , to which there are corresponding subscriber-specific partial modules 204 So CIF Customer CPU Interfaces a large number of different custom host CPUs 102 connect. This must be dependent on the participant 102 only the partial module 204 be varied, which means a much lower cost. The CPU interface 203 and the rest of the communication block 100 can be taken over unchanged.

The input buffer or input buffer 201 and the output buffer or output buffer 202 can be formed in a common memory device or in separate memory devices. The input buffer is used here 201 for caching messages for transmission to a message store 300 , Here is the input buffer block 201 preferably configured so that it can store two complete messages consisting of a respective header segment or header segment, in particular with configuration data and a data segment or payload segment. Where is the input buffer 201 formed in two parts (partial buffer memory and shadow memory), which by alternately writing the two parts of the input buffer memory or by access change the transmission between the subscriber CPU 102 and message storage 300 accelerate. Likewise, the output buffer or output buffer is used 202 (Output buffer OBF) for the caching of messages for transmission from the message memory 300 to the participant CPU 102 , Here is also the output buffer 202 designed so that two complete messages consisting of header segment, in particular with configuration data and data segment, so payload segment, can be stored. Again, the output buffer is 202 divided into two parts, a partial buffer memory and a shadow memory, which also here by alternately reading the two parts of the transmission or by access change the transmission between the host or host CPU 102 and message storage 300 accelerate. This second arrangement 104 consisting of the blocks 201 to 204 is with the first arrangement 105 connected as shown.

The order 105 consists of a message administrator 200 (Message handler MHD) and a message memory 300 (Message RAM). The embassy administrator 200 controls or controls the data transfer between the input buffer memory 201 as well as output buffer memory 202 and the message storage 300 , Likewise, it controls the data transfer in the other direction via the third arrangement 103 , The message storage 300 is preferably designed as a single-ported RAM. This RAM memory stores the messages or embassy objects, ie the actual data, together with configuration and status data. The exact structure of the embassy spei chers 300 is in 3 shown in more detail.

The third arrangement 103 consists of the blocks 205 to 208 , This arrangement corresponds to the two channels of the FlexRay Physical Layer 103 divided into two data paths with two data directions each. This is through the connections 213 and 214 clearly showing the two data directions for channel A with RxA and TxA for receive (RxA) and transmit (TxA) and for channel B with RxB and TxB. With connection 215 is an optional bidirectional control input. The connection of the third arrangement 103 takes place via a first buffer memory 205 for channel B and a second buffer memory 206 for channel A. These two transient buffer RAMs (RAM A and RAM B) serve as latches for data transfer from and to the first device 105 , According to the two channels, these two buffer memory 205 and 206 each with an interface block 207 and 208 connected to the FlexRay protocol controller or bus protocol controller consisting of a transmit / receive shift register and the FlexRay protocol finite state machine. The two buffer memories 205 and 206 thus serve as a buffer for the data transfer between the shift registers of the interface modules or FlexRay protocol controller 207 and 208 and the message storage 300 , Again, advantageously, each buffer memory 205 or 206 the data fields, ie the payload segment or data segment of two FlexRay messages stored.

Also shown in the communication block 100 is with 209 the global time unit (GTU), which is responsible for the representation of the global time grid in the FlexRay, ie the microtick μT and the macrotick MT. Likewise is about the global time unit 209 the fault-tolerant clock synchronization of the cycle counter and the control of the time sequences in the static and dynamic segment of the FlexRay are regulated. With block 210 is the General System Control (SUC), which controls and controls the operation modes of the FlexRay communications controller. These include wakeup, startup, reintegration or integration, normal surgery and passive surgery.

block 211 shows the network and error management (Network and Error Management NEM) as described in the FlexRay protocol specification v2.0. block 212 Finally, the Interrupt Control (INT), which manages the status and error interrupt flags, and the interrupt outputs 219 to the participant CPU 102 controls or controls. The block 212 Also includes an absolute and a relative timer for generating time interruptions or timer interrupts.

For communication in a FlexRay network, message objects or messages (message buffer) can be configured with up to 254 data bytes. The message storage 300 is in particular a message RAM memory (Message RAM), which z. B. can save up to a maximum of 128 message objects. All functions that affect the treatment or management of the messages themselves are the message handler or message handler 200 implemented. These are, for example, the acceptance filtering, transfer of the messages between the two FlexRay protocol controller blocks 207 and 208 and the message storage 300 , that is, the message RAM as well as the control of the transmission order and the provision of configuration data or status data.

An external CPU, ie an external processor of the subscriber 102 , can via the subscriber interface 107 with the participant-specific part 204 directly to the registers of the FlexRay communication block 100 access. It uses a variety of registers. These registers are used to configure the FlexRay protocol controllers, ie the interface blocks 207 and 208 , the message handler (MHD) 200 , the Global Time Unit (GTU) 209 , the general system controller (System Universal Controller SUC) 210 , the Network and Error Management Unit (NEM) 211 , the interrupt controller (interrupt controller INT) 212 and the access to the message RAM, so the message memory 300 to configure and control and also to display the corresponding status. At least parts of these registers are still in the 4 to 6 and 7 to 9 discussed in more detail. Such a described FlexRay communication module 100 enables easy implementation of the FlexRay specification v2.0, which makes it easy to generate an ASIC or a microcontroller with the corresponding FlexRay functionality.

Through the described FlexRay communication module 100 For example, the FlexRay protocol specification, in particular v2.0, can be fully supported and thus, for example, up to 128 messages or message objects can be configured. This results in a flexibly configurable message memory for storing a different number of message objects depending on the size of the respective data field or data area of the message. Thus, thus advantageously embassies or message objects to configure that have different lengths of data fields. The message storage 300 is advantageously designed as FIFO (first in-first out), so that there is a configurable receive FIFO. Each message or message object in memory can be configured as a Receive Buffer, Transmit Buffer, or as part of the configurable Receive FIFO. Likewise, acceptance filtering on frame ID, channel ID and cycle counter in the FlexRay network is possible. Conveniently, the network management is thus supported. Advantageously, maskable module interrupts are also provided.

In 3 is the division of the message memory in detail 300 described. For the functionality of a FlexRay communication controller required according to the FlexRay protocol specification, a message memory is required for the provision of messages to be sent (Transmit Buffer Tx) as well as the storage of messages received without errors (Receive Buffer Rx). A FlexRay protocol allows messages with a data range, ie a payload range from 0 to 254 bytes. As in 2 shown is the message memory 300 Part of the FlexRay communication block 100 , The procedure described below and the corresponding message memory 300 describe the storage of messages to be sent as well as received messages, in particular using a Random Access Memory (RAM), whereby it is possible by the described mechanism to store a variable number of messages in a message memory of predetermined size. The number of storable messages is dependent on the size of the data areas of the individual messages, whereby on the one hand the size of the required memory can be minimized without restricting the size of the data areas of the messages and on the other hand an optimal utilization of the memory takes place. In the following, this variable division of a particular RAM-based message memory is intended 300 for a FlexRay Communication Controller.

For implementation, a message memory with a fixed word length of n bits, for example 8, 16, 32, etc., as well as a predetermined memory depth of m words is given as an example (m, n as natural numbers). This is the message memory 300 divided into two segments, a header segment or header segment HS and a data segment DS (Payload Section, Payload Segment). Thus, a header area HB and a data area DB are created per message. For messages 0, 1 to k (k as natural number), header areas or header areas HB0, HB1 to HBk and data areas DB0, DB1 to DBk are thus created. In a message, therefore, a distinction is made between first and second data, the first data corresponding to configuration data and / or status data relating to the FlexRay message and stored in a header area HB (HB0, HB1, ..., HBk), respectively. The second data, which corresponds to the actual payload data to be transmitted, are correspondingly stored in data areas DB (DB0, DB1, ..., DBk). Thus, for the first data per message a first amount of data (measured in bits, bytes or memory words) and for the second data of a message a second amount of data (also measured in bits, bytes or memory words), the second data size per message may be different , The division between header segment HS and data segment DS is now in the message memory 300 variable, ie there is no given boundary between the areas. The division between the header segment HS and the data segment DS is dependent on the number k of the messages and the second data volume, ie the extent of the actual user data, a message or all k messages together. The configuration data KD0, KD1 to KDk of the respective message is now assigned directly to a pointer element or data pointer DP0, DPI to DPk. In the specific embodiment, each head area HB0, HB1 to HBk is assigned a fixed number of memory words, here two, so that always a configuration data KD (KD0, KD1, ..., KDk) and a pointer element DP (DP0, DP1 , ..., DPk) are stored together in a header area HB. At this head segment HS with the header areas HB whose size or first data size is dependent on the number k of messages to be stored, the data segment DS connects to store the actual message data D0, D1 to Dk. This data segment (or data section) DS depends in its scope of data on the respective data volume of the stored message data, here, for example, in DB0 six words, DB1 a word and DBk two words. The respective pointer elements DP0, DP1 to DPk thus always point to the beginning, ie to the start address of the respective data area DB0, DB1 to DBk, in which the data D0, D1 to Dk of the respective messages 0, 1, to k are stored. This is the division of the message memory 300 between head segment HS and data segment DS variable and depends on the number k of the messages themselves and the respective data volume of a message and thus the entire second data volume. If fewer messages are configured, the header segment HS becomes smaller and the released area in the message memory 300 can be used as an addition to the data segment DS for the storage of data. This variability ensures optimal memory utilization, which also allows the use of smaller memory. The free data segment FDS, in particular its size, also depends on The combination of the number k of messages stored and the respective second data size of the messages is thus minimal and can even be zero.

Next it is also possible to use the first and second pointer elements Data, ie the configuration data KD (KD0, KD1, ..., KDk) and the actual data D (D0, D1, ..., Dk) in a predefinable Sequence, so that the order of the head areas HB0 to HBk in the header segment HS and the order of the data areas DB0 to DBk in the data segment DS is identical in each case. Then could be under circumstances even waive a pointer element.

In a particular embodiment, the message memory is assigned a misrecognition generator, in particular a parity bit generator element and a misrecognition tester, in particular a parity bit test element in order to ensure the correctness of the stored data in HS and DS, by per memory word or per area (HB and / or DB) a checksum just in particular as a parity bit can be stored. Other control identifiers, eg a CRC (Cyclic Redundancy Check) or higher-value identifiers such as ECC (Error Code Correction) are conceivable. Thus, the following advantages are given compared to a defined division of the message memory:
The user can decide in programming whether to use a larger number of messages with a small data field or whether he wants to use a smaller number of messages with a large data field. When configuring messages with differently sized data areas DB, the available memory space is optimally utilized. The user has the option to share a data storage area for different messages.

When implementing the communication controller on an integrated circuit, the size of the message memory 300 by adapting the memory depth (number m of words) of the memory used to the needs of the application, without changing the other functions of the Communication Controller.

In the following, the basis of the 4 to 6 such as 7 to 9 the host CPU access, ie writing and reading configuration data or status data and the actual data on the buffer memory arrangement 201 and 202 , described in more detail. In this case, the aim is to produce a decoupling with regard to the data transmission in such a way that the data integrity can be ensured and at the same time a high transmission speed is ensured. These processes are controlled by the message administrator 200 , which later even closer in the 10 . 11 and 12 is described.

In the 4 . 5 and 6 First, the write accesses to the message memory 300 through the host CPU of the subscriber CPU 102 over the input buffer 201 explained in more detail. In addition shows 4 once again the communication module 100 , for reasons of clarity, only the relevant parts of the communication module 100 are shown. On the one hand, this is the message manager responsible for controlling the processes 200 and two control registers 403 and 404 as shown outside the message administrator 200 in the communication block 100 can be accommodated, but also in the embassy administrator 200 themselves can be included. 403 represents the input request register (Input Buffer Command Request Register) and 404 the input mask register (Input Buffer Command Mask Register). Write accesses of the host CPU 102 on the message storage 300 (Message RAM) thus take place via an intermediate input buffer memory 201 (Input buffer). This input buffer 201 is now divided or doubled, as a partial buffer 400 and a shadow memory associated with the sub-buffer 401 , Thus, as described below, a continuous access of the host CPU 102 on the messages or message objects respectively data of the message memory 300 ensure data integrity and accelerated transmission.

The control of accesses via the input request register 403 and via the input mask register 404 , In the register 403 are in 5 with the numbers from 0 to 31, the respective bit locations in 403 are exemplified here for a width of 32 bits. The same applies to the register 404 and bits 0 to 31 in the mask register 404 out 6 ,

By way of example, the bit positions 0 to 5, 15, 16 to 21 and 31 of the register are obtained 403 with regard to the sequence control a special function. So is in the bit positions 0 to 5 of the register 403 an identifier IBRH (Input Buffer Request Host) can be entered as a message identifier. Likewise, in the bit positions 16 to 21 of the register 403 an identifier IBRS (Input Buffer Request Shadow) can be entered. Similarly, in register 15 of 403 IBSYH and in registry 31 of 403 IBSYS entered as access IDs. Also excellent are the positions 0 to 2 of the register 404 , where in 0 and 1 with LHSH (Load Header Section Host) and LDSH (Load Data Section Host) other identifiers are entered as data identifiers. These data identifiers are here in the simplest form, namely each formed as a bit. In bit 2 of register 404 is with STXRH (Set Transmission X Request Host) a start identifier inscribed. The sequence of write access to the message memory will now be described below 300 via the input buffer 201 described.

The host CPU 102 writes the data of the message to be transferred into the input buffer 201 , The host CPU can do this 102 only the configuration and header data KD of a message for the header segment HS of the message memory 300 or only the actual data D to be transmitted of a message for the data segment DS of the message memory 300 or write both. Which part of a message, that is to say configuration data and / or the actual data, is to be transmitted, is identified by the special data identifiers LHSH and LDSH in the input tag register 404 established. In this case, LHSH (Load Header Section Host) determines whether the header data, ie the configuration data KD, are transmitted and LDSH (Load Data Section Host) determines whether the data D is to be transmitted. Because of the input buffer memory 201 two-part with a partial buffer memory 400 and an associated shadow store 401 is formed and a mutual access is to take place as a counterpart to LHSH and LDSH two more data detection areas are provided, which now on the shadow memory 401 are related. These data identifiers are in bit positions 16 and 17 of the register 404 are labeled with Load Header Section Shadow (LHSS) and Load Data Section Shadow (LDSS). Through this, thus, the transfer process with respect to the shadow memory 401 controlled.

Is now the start bit or the start identifier STXRH (Set Transmission X Request Host) in bit position 2 of the input mask register 404 is set, so after successful transfer of each to be transmitted configuration data and / or actual data in the message memory 300 automatically set a transmission request for the corresponding message object. Ie. The automatic transmission of a transmitting message object is controlled, in particular started, by this start identifier STXRH.

The counterpart to this accordingly for the shadow memory 401 is the start identifier STXRS (Set Transmission X Request Shadow) which is exemplified in bit position 18 of the input tag register 404 is contained and also here in the simplest case just formed as a bit. The function of STXRS is analogous to the function of STXRH, only relative to the shadow memory 401 ,

If the host CPU 102 the message identifier, in particular the number of the message object in the message memory 300 into which the data of the input buffer memory 201 to be transferred to the bit positions 0 to 5 of the input request register 403 So, after IBRH writes, the part cache will 400 of the input buffer 201 and the associated shadow memory 401 reversed or it is the respective access from the host CPU 102 and message storage 300 on the two partial storage 400 and 401 reversed, as indicated by the semicircular arrows. In this case, for example, the data transfer, so the data transfer to the message memory 300 started. The data transmission to the message memory 300 itself takes place from the shadow memory 401 , At the same time, the register areas IBRH and IBRS are exchanged. Likewise exchanged LHSH and LDSH against LHSS and LDSS. In the same way STXRH is exchanged with STXRS. IBRS thus shows the identifier of the message, that is the number of the message object for the one transmission, ie a transfer from the shadow memory 401 is in progress or which message object, so what area in the message memory 300 last data (KD and / or D) from the shadow memory 401 had received. By the identifier (again, for example, 1 bit) IBSYS (Input Buffer Busy Shadow) in bit position 31 of the input request register 403 is displayed whether just a transmission involving the shadow memory 401 he follows. For example, if IBSYS = 1, it will just be out of shadow memory 401 transferred and not at IBSYS = 0. This bit IBSYS, for example, by writing IBRH, so bit positions 0 to 5, in register 403 set to indicate that there is a transfer between the shadow memory 401 and the message storage 300 is in progress. After completion of this data transfer to the message memory 300 IBSYS is reset again.

While the data transfer from the shadow memory 401 the host CPU is currently running 102 the next message to be transferred into the input buffer 201 or in the partial buffer memory 400 write. With the help of another access identifier IBSYH (Input Buffer Busy Host), for example, in bit position 15 of Register 403 the identifier can be further refined. Writes the host CPU 102 just IBRH, so the bit positions 0 to 5 of Register 403 while transferring between the shadow store 401 and the message storage 300 If IBSYS = 1, then IBSYH will be in the input request register 403 set. As soon as the current transfer, ie the current transfer, is completed, the requested transfer (request by STXRH see above) is started and bit IBSYH is reset. The IBSYS bit remains set all the time to indicate that data is in message memory 300 be transferred. All used Bits of all embodiments can also be designed as identifiers with more than one bit. The one-bit solution is advantageous for reasons of memory and processing economy.

The mechanism so described allows the host CPU 102 continuously data in the message memory 300 located message objects consisting of header area HB and data area DB to transfer, provided the access speed of the host CPU 102 on the input buffer 201 is less than or equal to the internal data transfer rate of the FlexRay IP module, ie the communication block 100 ,

In the 7 . 8th and 9 Now the read accesses to the message memory 300 through the host CPU or user CPU 102 via the output buffer or output buffer 202 explained in more detail. In addition shows 7 once again the communication module 100 , for reasons of clarity, only the relevant parts of the communication module here 100 are shown. On the one hand, this is the message manager responsible for controlling the processes 200 and two control registers 703 and 704 who are outside of the embassy administrator as shown 200 in the communication block 100 can be accommodated, but also in the embassy administrator 200 themselves can be included. 703 represents the output request buffer (Output Buffer Command Request Register) and 704 the Output Masking Register (Output Buffer Command Mask Register). Read accesses of the host CPU 102 on the message storage 300 So done via the intermediate output buffer memory 202 (Output buffer). This output buffer 202 is now also divided or doubled designed, as a partial buffer memory 701 and a shadow memory associated with the sub-buffer 700 , Thus, here as described below, a continuous access of the host CPU 102 on the messages or message objects respectively data of the message memory 300 data integrity and accelerated transmission now in the opposite direction from the message memory 300 to the host 102 be guaranteed. The access is controlled via the output request register 703 and via the output mask register 704 , Also in the register 703 with the numbers from 0 to 31 are the respective bit positions in 703 illustrated here by way of example for a width of 32 bits (cf. 8th ). The same applies to the register 704 and the bit positions 0 to 31 in 704 (see. 9 ).

By way of example, bit positions 0 to 5, 8 and 9, 15 and 16 to 21 of the register are obtained 703 with respect to the flow control of the read access a special function. So is in the bit positions 0 to 5 of the register 703 An identifier OBRS (Output Buffer Request Shadow) can be entered as the message identifier. Likewise, in the bit positions 16 to 21 of the register 703 an identifier OBRH (Output Buffer Request Host) can be entered. The access identifier is in bit position 15 of register 703 an identifier OBSYS (Output Buffer Busy Shadow) can be entered. Also excellent are the digits 0 and 1 of the output mask register 704 , where further identifiers are entered as data identifiers in the bit positions 0 and 1 with RDSS (Read Data Section Shadow) and RHSS (Read Header Section Shadow). Further data identifiers are provided, for example, in bit positions 16 and 17 with RDSH (Read Data Section Host) and RHSH (Read Header Section Host). These data identifications are here also exemplary in the simplest form, namely each formed as a bit. In bit position 9 of the register 703 is a start identifier REQ registered. Furthermore, a switchover identifier VIEW is provided, which is exemplified in bit position 8 of register 703 is registered.

The host CPU 102 requests the data of a message object from the message memory 300 by entering the identifier of the desired message, that is to say, in particular, the number of the desired message object, according to OBRS, into bit positions 0 to 5 of the register 703 writes. Again, the host CPU can 102 as in the opposite direction either only the status or configuration and header data KD a message so read from a header area or only the actual data to be transmitted D a message from the data area or both. Which part of the data is to be transferred from the header area and / or data area is thus set comparable to the opposite direction by RHSS and RDSS. That is, RHSS indicates whether the header data should be read, and RDSS indicates whether the actual data should be read.

A start identifier serves for the transmission from the message memory 300 to the shadow memory 700 to start. That is, as an identifier, as in the simplest case, a bit is used, by setting bit REQ in bit position 9 in the output request register 703 the transmission from the message memory 300 to the shadow memory 700 started. The current transmission is again by an access identifier, here again in the simplest case by a bit OBSYS in the register 703 , displayed. In order to avoid collisions, it is advantageous if the REQ bit can only be set if OBSYS is not set, ie no ongoing transmission is currently taking place. This is where the message transfer between the message memory takes place 300 and the shadow store 700 , The actual procedure could be comparable to the opposite direction on the one hand 4 . 5 and 6 beschrie ben are controlled (complementary register occupancy) and done or in a variation by an additional identifier, namely a switchover VIEW in bit 8 of the register 703 , That is, after completion of the transfer, the OBSYS bit is reset and by setting the VIEW bit in the output request register 703 become the partial cache 701 and the associated shadow memory 700 exchanged or the accesses are exchanged and the host CPU 102 can now do that from the message memory 300 requested message object, ie the corresponding message, from the partial buffer memory 701 read. Here, too, are comparable to the Gegenübertragungsrichtung in the 4 are 6 the register cells OBRS and OBRH exchanged. Likewise, RHSS and RDSS are exchanged for RHSH and RDSH. As a protection mechanism, it can also be provided here that the bit VIEW can only be set if OBSYS is not set, ie no ongoing transmission takes place.

Thus read accesses of the host CPU 102 on the message storage 300 via the intermediate output buffer 202 , This output buffer 202 is the same as the input buffer 201 double or two-part design, for continuous access of the host CPU 102 on the message objects in the message memory 300 are guaranteed. Again, the benefits of high data integrity and accelerated transmission are achieved.

By using the described input and output buffers 201 . 202 will ensure that a host CPU 102 despite the module-internal latencies interruption-free on the embassy memory 300 can access.

To ensure this data integrity is the data transfer, especially the forwarding in the communication block 100 , by the embassy administrator 200 (Message handler MHD) made. This is in 10 the embassy administrator 200 shown. The embassy administrator 200 is in its functionality by several state machines or state machines, so finite state machines, so-called finite state machines (FSM) representable. In this case, at least three state machines and in a particular embodiment four finite state machines are provided. A first finite state machine is the IOBF FSM and with 501 referred to (input / output buffer state machine). This IOBF FSM could also be per transmission direction with respect to the input buffer memory 201 or the output buffer 202 split into two finite-state machines: IBF-FSM (Input Buffer FSM) and OBF-FSM (Output Buffer FSM), with which a maximum of five state machines (IBF-FSM, OBF-FSM, TBF1-FSM, TBF2-FSM, AFSM) would be conceivable. However, it is preferable to provide a common IOBF FSM. A second finite-state machine is here in the course of the preferred embodiment in two blocks 502 and 503 split and operate the two channels A and B with respect to the memory 205 and 206 , how to 2 described. In this case, a finite state machine can be provided to serve both channels A and B, or, as in the preferred form, a finite state machine TBF1-FSM with 502 (Transient buffer 1 ( 206 , RAM A) State Machine) for channel A and for channel B a TBF2-FSM with 503 (Transient Buffer 2 ( 205 , RAM B) State Machine).

To control the access of the three finite state machines 501 - 503 in the preferred embodiment, an arbiter finite state machine, the so-called AFSM, with the 500 is designated. The data (KD and / or D) are in a clock generated by a clock means such as a VCO (Voltage Controlled Oscillator), a crystal oscillator, etc., or adapted from this clock in the communication module 100 transfer. The clock T can be generated in the block or be specified from the outside, eg as a bus clock. This arbiter finite state machine AFSM 500 alternately gives one of the three finite state machines 501 - 503 , in particular for one clock period T access to the message memory 300 , That is, the time available will be according to the access requirements of each state machine 501 . 502 . 503 divided into these requesting state machines. If an access request is made by only one finite-state machine, then it receives 100 of the access time, ie all the clocks T. If an access request is made by two state machines, each finite-state machine receives 50% of the access time. Finally, if an access request from three state machines occurs, each of the finite state machines will receive 1/3 of the access time. This optimally utilizes the available bandwidth.

• – Datentransfer vom Eingangspufferspeicher 201 zum ausgewählten Botschaftsobjekt im Botschaftsspeicher 300.
• – Datentransfer vom ausgewählten Botschaftsobjekt im Botschaftsspeicher 300 zum Ausgangspufferspeicher 202.

The first finite-state machine 501 , ie IOBF-FSM, performs the following actions as required:

• - Data transfer from the input buffer memory 201 to the selected message object in the message memory 300 ,
• - Data transfer from the selected message object in the message memory 300 to the output buffer 202 ,

• – Datentransfer vom ausgewählten Botschaftsobjekt im Botschaftsspeicher 300 zum Pufferspeicher 206 von Kanal A.
• – Datentransfer vom Pufferspeicher 206 zum ausgewählten Botschaftsobjekt im Botschaftsspeicher 300.
• – Suche nach dem passenden Botschaftsobjekt im Botschaftsspeicher 300, wobei bei Empfang das Botschaftsobjekt (Receive Buffer) zum Abspeichern einer auf Kanal A empfangenen Botschaft im Rahmen einer Akzeptanzfilterung gesucht wird und beim Senden das nächste auf Kanal A zu sendende Botschaftsobjekt (Transmit Buffer).

The state machine 502 for channel A, TBF1-FSM, performs the following actions:

• - Data transfer from the selected message object in the message memory 300 to the cache 206 from channel A.
• - Data transfer from the buffer memory 206 to the selected message object in the message memory 300 ,
• - Search for the appropriate message object in the message memory 300 in which, on receipt, the message object (receive buffer) for storing a message received on channel A is searched within the framework of acceptance filtering and, when transmitting, the next message object to be sent on channel A (transmit buffer).

Similarly, the action of TBF2-FSM, so the finite state machine for channel B in block 503 , This performs the data transfer from the selected message object in the message memory 300 to the cache 205 from channel B and the data transfer from the buffer memory 205 to the selected message object in the message memory 300 , The search function is analogous to TBF1-FSM for a suitable message object in the message memory 300 in which, on receipt, the message object (receive buffer) for storing a message received on channel B is searched within the framework of acceptance filtering, and the next message or message object (transmit buffer) to be transmitted on channel B is sent during transmission.

In 11 Now again the processes and the transmission paths are shown. The three state machines 501 - 503 control the respective data transfers between the individual parts. It is with 102 again the host CPU is shown using 201 the input buffer and with 202 the output buffer. With 300 the message memory is shown and the two buffers for channel A and channel B with 206 and 205 , The interface elements 207 and 208 are also shown. The first state machine IOBF-FSM, with 501 denotes the data transfer Z1A and Z1B, ie from the input buffer memory 201 to the embassy memory 300 and from the message store 300 to the output buffer 202 , The data transmission takes place via data buses with a word width of 32 bits, for example, although any other bit number is possible. The same applies to the transmission Z2 between the message memory and the buffer memory 206 , This data transfer is performed by TBFI-FSM, ie the state machine 502 for channel A, controlled. The transmission Z3 between message memory 300 and cache 205 is through the state machine TBF2-FSM, ie 503 controlled. Here, too, the data transfer takes place over the upper data buses with an exemplary word width of 32 bits, whereby here too every other bit number is possible. Normally, the transfer of a complete message object via the aforementioned transmission paths requires several clock periods T. Therefore, a distribution of the transmission time based on the clock periods T by the arbiter, so the AFSM 500 , In 11 So the data paths are between those of the message handler 200 controlled memory components shown. To the data integrity of the message memory 300 To ensure stored messages objects should advantageously be exchanged at the same time only on one of the paths shown so Z1A and Z1B and Z2 and Z3 data simultaneously.

In 12 is shown by an example, as the available system clocks T from Arbiter, so the AFSM 500 to which three requesting state machines are split. In Phase 1 (I) access requests are made by state machine 501 and state machine 502 that is, that the entire time is split in half on the two requesting state machines. Relative to the clock periods in phase 1 (I), this means that state machine 501 in the clock periods T1 and T3 receives access and state machine 502 in the clock periods T2 and T4. In Phase 2 (II) access is only through the state machine 501 so that every three clock periods, ie 100% of the access time from T5 to T7, are allocated to IOBF-FSM. In phase 3 (III), access requests are made to all three state machines 501 to 503 , so that a third of the total access time takes place. The arbiter AFSM 500 then distributes the access time, for example, so that in the clock periods T8 and T11, the finite state machine 501 , in the clock periods T9 and T12, the finite-state machine 502 and in the clock periods T10 and T13, the finite state machine 503 Access receives. Finally, in phase 4 (IV), access is through two state machines, 502 and 503 on the two channels A and B of the communication block 100 such that an access distribution of the clock periods T14 and T16 to finite-state machine 502 and in T15 and T17 on finite-state machine 503 he follows.

The arbiter state machine AFSM 500 thus ensures that if more than one of the three state machines 501 - 503 a request for access to the message memory 300 provides access in a clocked and alternating manner to the requesting state machines 501 - 503 is split. This approach represents the integrity of message memory 300 stored message objects, ie data integrity. For example, wants the host CPU 102 over the output buffer 202 read out a message object while a received message is being written in this message object, either the old state or the new state is read out, depending on which request was started first, without the accesses in the message object in the message memory 300 itself collide.

The method described enables the host CPU 102 Any message object in the message memory during operation 300 to read or write without leaving the selected message object for the duration of the host CPU's access 102 from participation in the data log Exchange on both channels of the FlexRay bus 101 locked (Buffer Locking). At the same time, the integrity of the messages in the message memory is buffered by interleaving the accesses 300 stored data and increases the transmission speed, even by exploiting the full bandwidth.

So far, both the subscriber and the microprocessor (the host CPU) of the subscriber with the reference number 102 and represented in the description as equivalents. For the following description of the invention, however, a differentiation is required. In the following, the reference number will therefore be used for the entire FlexRay subscriber 900 introduced while with the reference numeral 102 only the microprocessor (the host CPU) of the subscriber 900 referred to as. For a more detailed explanation, see 15 referred where a known from the prior art participants 900 is shown.

The well-known participant 900 includes a microcontroller 800 , a DMA (Direct Memory Access) controller 810 , a peripheral bus 820 and the FlexRay communication controller 750 , The peripheral bus may be configured as any internal data bus. As peripheral buses often proprietary data buses are used, since the entire with 900 designated component is usually manufactured by one and the same semiconductor manufacturer. So it's just the internal components 800 . 810 and 750 in the component 900 communicate via the peripheral bus.

The use of a DMA controller 810 is optional. There are also participants 900 known in which the data transfer between the microcontroller 800 and the communication controller without a DMA controller 810 works.

The microcontroller 800 includes the microprocessor 102 (Host CPU), a storage element 802 as well as a core bus 804 , This configuration is also referred to as the processor core with "tightly coupled memory" (TCM). Of course, the memory element of the microprocessor 102 also act around an externally attached memory. The microcontroller 800 is over an active interface "a" of the microprocessor 102 and a passive interface "p" of the memory element 802 to the peripheral bus 820 connected. Also the DMA controller 810 is - if available - via an active interface "a" and a passive interface "p" to the peripheral bus 820 connected. The communication controller 750 is in the known participant 900 but only via a passive interface "p" to the peripheral bus 820 connected. In other words, so are the microcontroller 800 and the DMA controller 810 as a master to the periphery bus 820 connected, whereas the communication controller 750 only as a slave to the bus 820 connected.

The microprocessor 102 configures, controls and controls the communication controller 750 , The microprocessor 102 It reads and evaluates messages, calculates new messages, and writes messages for delivery over the communication link 101 , For data transmission within the subscriber 900 without the use of a DMA controller 810 transmits the microprocessor 102 the data word by word from the communication controller 750 (dashed line a) in the memory element 802 of the microcontroller 800 (dashed line f). This occurs at the usual today high clock rates of the microprocessor 102 several wait cycles during which the microprocessor 102 waiting for the end of the data transfer and can pursue no other tasks.

If a DMA controller 810 is used, this can the data transfer between the memory element 802 of the microcontroller 800 and the communication controller 750 carry out. He gets it from the microprocessor 102 configured and started (dashed line b). After that, the DMA controller transmits 810 Data word by word from the communication controller 750 in the store 802 of the microcontroller 800 (dashed line c). The end of the data transfer is the microprocessor 102 notified by means of an interrupt (dashed line e), whereupon the microprocessor 102 the process for the next message begins anew. The processing of interrupts generates a large number of CPU instructions, through which a large part of the computational and memory resources of the microprocessor 102 is bound. In addition, frequent interrupts increase the possible jitter (time duration of the execution time) of interrupted software tasks.

In 13 is an inventive participant 900 of a FlexRay communication system. It can be clearly seen that the communication controller 750 both via a passive interface "p" and via an active interface "a" to the peripheral bus 820 connected. That means the communication controller 750 not only as a slave, but also as a master to the peripheral bus 820 connected. Thus, the communication controller 750 not just commands and data from others to the peripheral bus 820 connected participants (eg microcontroller 800 ), but evaluate received messages (data and commands) and these via the peripheral bus 820 to the microcontroller 800 to ship.

The microprocessor 102 configured, kontrol liert and controls the communication controller 750 (dashed line a). The microprocessor 102 Read already received and automatically in the memory element 802 copied (dashed line b) message objects, evaluates them (dashed line c), calculates new message objects and puts them in the memory element 802 from (dashed line c). In addition, the microprocessor starts 102 the transfer to the embassy memory 300 (dashed line a), in turn, automated by the communication controller 750 is carried out. The message storage 300 stores the message objects (so-called message buffer) together with configuration and status information.

The communication controller 750 can have one in the controller 750 embedded logic autonomously both message objects from the message memory 300 read out and into the memory element 802 write as well as message objects from the memory element 802 read out and in the message memory 300 write (dashed line b).

In 14 is the communication controller according to the invention 750 , like him in a participant 900 according to 14 is used, shown in detail. The FlexRay communication controller 750 includes a FlexRay communication block 100 as described in detail above. The communication module 100 is - as I said - divided into a generic part, which in 14 with the reference number 840 is designated and independent of the connected microcontroller 800 always be the same and in a participant-specific part. The generic part 840 is also referred to as a communication controller core. From the generic part 840 of the communication block 100 are in 14 for example only the generic interface 203 (GIF), the message store 300 as well as the memory 300 upstream input buffer memory 201 and output buffer 202 shown. The input buffer 201 serves to temporarily store messages for transfer to the message memory 300 , The output buffer 202 serves for buffering messages for the transfer from the message memory 300 to the microcontroller 800 , Of course, the communication module 100 out 14 all or just some of the 2 include illustrated elements.

The generic part of the communication block 100 is via the generic interface 203 (GIF) to the subscriber-specific interface 204 (CIF) of the subscriber-specific part of the communication module 100 connected. The generic interface 203 can be accessed via the subscriber-specific interface 204 to various customer-specific host CPUs 102 connect. The logic of the communication controller 750 is in the subscriber-specific interface 204 (CIF) in the form of a state machine 830 educated. The subscriber-specific interface 204 (CIF) connects the peripheral data bus 820 of the microprocessor 102 with the generic interface 203 (GIF) of the FlexRay communication scooter core. With the reference numerals 832 and 834 are the passive interface "p" or the active interface "a" of the communication controller 750 designated. An arbiter 836 arbitrates concurrent accesses of the microprocessor 102 and the state machine 830 on the generic interface 203 (GIF) of the communication controller core 840 , In addition, there is a control and status register 838 provided over which the microprocessor 102 the state machine 830 and thus configure, control and control the data transfer.

• – Sichtbarmachen des empfangenen Botschaftsobjekts in dem Ausgangspufferspeicher 202 des Kommunikationscontrollers 750; und
• – Anlegen einer Kopie des empfangenen Botschaftsobjekts in einem konfigurierbaren Adressbereich des dem Mikroprozessor 102 zugeordneten Speicherelements 802 durch Schreibzugriffe über die aktive Schnittstelle 834.

The state machine controls to actively copy after receiving a message 830 following a triggering signal after receiving a new message from the FlexRay communication connection, the following events occur automatically:

• Visualizing the received message object in the output buffer memory 202 of the communication controller 750 ; and
• - Creating a copy of the received message object in a configurable address range of the microprocessor 102 associated memory element 802 through write accesses via the active interface 834 ,

• – Erkennen eines Befehls oder mindestens eines gesetzten Bits in einem Kontroll- und/oder Statusregister des Kommunikationscontrollers 750 zum Starten der Datenübertragung;
• – Auslesen der Daten aus einer konfigurierbaren Adresse des Speicherelements 802;
• – Anlegen einer Kopie des ausgelesenen Botschaftsobjekts in dem Eingangspufferspeicher 201 des Kommunikationscontrollers 750; und
• – Initiieren der Übertragung der Daten aus dem Pufferspeicher 201 in den Botschaftsspeicher 300 des Kommunikationscontrollers 750 bzw. des Kommunikationsbausteins 100.

For active copying to send a new message in the storage element 802 is present, the microprocessor causes 102 via the control registers 838 a transfer of the message from the storage element 802 in the message memory 300 of the communication controller core 840 , The state machine controls 830 successively the following operations:

• - Detecting a command or at least one set bit in a control and / or status register of the communication controller 750 to start the data transfer;
• - Reading the data from a configurable address of the memory element 802 ;
• - Create a copy of the read message object in the input buffer memory 201 of the communication controller 750 ; and
• Initiate the transfer of the data from the buffer memory 201 in the message memory 300 of the communication controller 750 or the communication block 100 ,

• – Der Mikroprozessor 102 wird im Vergleich zu Zugriffen über einen externen DMA-Controller (vgl. Bezugszeichen 810 in 15) von einer hohen Interruptlast befreit.
• – Eine geringere Interruptlast ermöglicht einen geringeren Taskjitter und damit eine bessere Vorhersagbarkeit des Gesamtsystems.
• – Durch Zugriffe auf Botschaftskopien im Speicherelement 802 ist eine größere Zugriffsbandbreite möglich.
• – Durch die höhere Zugriffsbandbreite hat der Mikroprozessor 102 mehr Rechenzeit für andere Aufgaben zur Verfügung (Latenzzeiten des Prozessors 102 werden verringert).

By using the described active interface 834 together with the logic in the form of the state machine 830 There are the following advantages:

• - The microprocessor 102 is compared to accesses via an external DMA controller (see reference numeral 810 in 15 ) freed from a high interrupt load.
• - A lower interrupt load allows a lower task jitter and thus a better predictability of the whole system.
• - By accessing message copies in the memory element 802 a larger access bandwidth is possible.
• - Due to the higher access bandwidth has the microprocessor 102 more computing time available for other tasks (latency of the processor 102 are reduced).

Claims (18)

Attendees ( 900 ) of a communication system, wherein the subscriber ( 900 ) a microprocessor ( 102 ), a communication controller ( 750 ) and a peripheral bus ( 820 ) and wherein the microprocessor ( 102 ) via the peripheral bus ( 820 ) with the communication controller ( 750 ) and via the communication controller ( 750 ) to a communication link ( 101 ) of the communication system via which messages are transmitted, characterized in that the communication controller ( 750 ) an active interface ( 834 ) via which the communication controller ( 750 ) with the peripheral bus ( 820 ), and has logic which allows independent data transmission between the communication controller ( 750 ) and the microprocessor ( 102 ) over the active interface ( 834 ) and the peripheral bus ( 820 ). Attendees ( 900 ) according to claim 1, characterized in that the communication controller ( 750 ) a message memory for buffering messages from the communication link ( 101 ) or for the communication connection ( 101 ), wherein the logic of the communication controller ( 750 ) an independent reading of data from the message memory of the communication controller ( 750 ) and storing the data in the microprocessor ( 102 ), as well as an independent reading of data from the microprocessor ( 102 ) and storing the data in the message memory of the communication controller ( 750 ). Attendees ( 900 ) according to claim 1 or 2, characterized in that the microprocessor ( 102 ) a memory element ( 802 ), the logic of the communication controller ( 750 ) an independent reading of data from the communication controller ( 750 ) and storing the data in the memory element ( 802 ) of the microprocessor ( 102 ), as well as an independent reading of data from the memory element ( 802 ) of the microprocessor ( 102 ) and storing the data in the communication controller ( 750 ). Attendees ( 900 ) according to one of claims 1 to 3, characterized in that the communication controller ( 750 ) a communication module ( 100 ) having a message memory ( 300 ) for buffering messages from the communication link ( 101 ) or for the communication connection ( 101 ), wherein the logic of the communication controller ( 750 ) an independent data transfer between the communication module ( 100 ) and the microprocessor ( 102 ), preferably between the message memory ( 300 ) of the communication module ( 100 ) and the microprocessor ( 102 ) associated memory element ( 802 ), via the peripheral bus ( 820 ). Attendees ( 900 ) according to claim 4, characterized in that the communication module ( 100 ) at least one between the message memory ( 300 ) and the peripheral bus ( 820 ) arranged buffer memory, preferably at least one input buffer memory ( 201 ) and at least one output buffer memory ( 202 ), wherein the logic of the communication controller ( 750 ) an independent data transfer between the communication module ( 100 ) and the microprocessor ( 102 ), preferably between the at least one buffer memory ( 201 . 202 ) of the communication module ( 100 ) and the microprocessor ( 102 ) associated memory element ( 802 ), via the peripheral bus ( 820 ). Attendees ( 900 ) according to one of claims 1 to 5, characterized in that the logic in the communication controller ( 750 ) a state machine ( 830 ). Attendees ( 900 ) according to claim 6, characterized in that the state machine ( 830 ) is hardwired. Attendees ( 900 ) according to claim 6 or 7, characterized in that the communication controller ( 750 ) an arbiter ( 836 ), the concurrent accesses of the microprocessor ( 102 ) and the state machine ( 830 ) to a message memory ( 300 ) of the communication controller ( 750 ) or a FlexRay communication block ( 100 ) arbitrated. Attendees ( 900 ) according to one of claims 1 to 8, characterized in that the communication controller ( 750 ) Control and / or status register ( 838 ) to which the microprocessor ( 102 ) can access the configuration, control and / or monitoring of data transmission. Attendees ( 900 ) according to one of the claims 1 to 9, characterized in that the participant ( 900 ) A component of a FlexRay communication system is in which a data transmission between the subscriber ( 900 ) and others to the FlexRay communication link ( 101 ) connected FlexRay participants according to the FlexRay protocol. Communication Controller ( 750 ) of a participant ( 900 ) of a communication system, wherein the subscriber ( 900 ) a microprocessor ( 102 ), the communication controller ( 750 ) and a peripheral bus ( 820 ) and wherein the communication controller ( 750 ) on the one hand via the peripheral bus ( 820 ) with the microprocessor ( 102 ) and, on the other hand, to a communication link ( 101 ) of the communication system via which messages are transmitted, characterized in that the communication controller ( 750 ) an active interface ( 834 ) via which the communication controller ( 750 ) with the peripheral bus ( 820 ), and has logic which allows independent data transmission between the communication controller ( 750 ) and the microprocessor ( 102 ) over the active interface ( 834 ) and the peripheral bus ( 820 ). Communication Controller ( 750 ) according to claim 11, characterized in that the communication controller ( 750 ) A component of a FlexRay communication system is in which a data transmission between the subscriber ( 900 ) and others to the FlexRay communication link ( 101 ) connected FlexRay participants according to the FlexRay protocol. Method for transmitting data within a subscriber ( 900 ) of a communication system, wherein the data is transferred between a microprocessor ( 102 ) and a communication controller ( 750 ) via a peripheral bus ( 820 ) and wherein the communication controller ( 750 ) to a communication link ( 101 ), via which messages are transmitted, characterized in that a logic of the communication controller ( 750 ) is initiated for data transmission and then the data transmission between the communication controller ( 750 ) and the microprocessor ( 102 ) via an active interface ( 834 ) of the communication controller ( 750 ) and the peripheral bus ( 820 ) independently controls. Method according to Claim 13, characterized in that the logic of the communications controller ( 750 ) by a command from the microprocessor ( 102 ) of the participant ( 900 ) is initiated for data transmission. Method according to claim 13 or 14, characterized in that the microprocessor ( 102 ) on control and / or status registers ( 838 ) of the communication controller ( 750 ) and so the data transmission is configured, controlled and / or monitored. Method according to one of claims 13 to 15, characterized in that the logic in the communication controller ( 750 ) a state machine ( 830 ), whereby concurrent accesses of the microprocessor ( 102 ) and the state machine ( 830 ) to a message memory ( 300 ) of the communication controller ( 750 ) or a communication block ( 100 ) are arbitrated. Method according to one of claims 13 to 16, characterized in that after receiving new data from the communication link ( 101 ) are initiated and controlled by the logic autonomously by the following steps: visualizing the received data in a buffer memory ( 202 ) of the communication controller ( 750 ); and - applying a copy of the received data in a configurable address range of a microprocessor ( 102 ) associated memory element ( 802 ) by write accesses via the active interface ( 834 ). A method according to any one of claims 13 to 17, characterized in that for sending new data in a microprocessor ( 102 ) associated memory element ( 802 ), from the microprocessor ( 102 ) a transmission of the data from the memory element ( 802 ) in the communication controller ( 750 ) and the logic of the communication controller ( 750 ) independently the following steps are initiated and controlled: detection of a command or at least one set bit in a control and / or status register ( 838 ) of the communication controller ( 750 ); - reading the data from a configurable address of the memory element ( 802 ); - Creating a copy of the read data object in a buffer memory ( 201 ) of the communication controller ( 750 ); and initiating the transfer of the data from the buffer memory ( 201 ) into a message memory ( 300 ) of the communication controller ( 750 ) or a communication block ( 100 ).