EP1987337A1

EP1987337A1 - Manufacturing process for integrated piezoelectric components

Info

Publication number: EP1987337A1
Application number: EP07703486A
Authority: EP
Inventors: Alida Wuertz
Original assignee: Atmel Germany GmbH
Current assignee: Atmel Germany GmbH
Priority date: 2006-02-24
Filing date: 2007-02-16
Publication date: 2008-11-05
Also published as: WO2007098863A1; DE102006008584A1; US20070202628A1

Abstract

Provision is made of a simple method for manufacturing integrated microelectromechanical components, in which first a silicon layer (2) on an isolator layer (1), then a piezoresistive layer (7) on or in the silicon layer (2) and subsequently at least one etching opening (3) for etching at least one hollow space (5) substantially inside the silicon layer (2) are manufactured. The shape of the hollow space (5) in the silicon layer (2) is determined, and the etching process can be reproduced easily, by the arrangement of additional vertical and horizontal etch stop layers. The method is suitable for being integrated in standard manufacturing processes in particular with the circuit components necessary for signal processing.

Description

Manufacturing process for integrated piezo components

The present invention relates to a method for producing integrated micro-electromechanical components according to claim 1 and micro-electro-mechanical components according to claim 16.

Micro-electro-mechanical systems MEMS, with which physical quantities such as pressure, force, acceleration, flow etc. can be converted into an electrical signal, are known. Conversely, it is also known to convert electrical signals, for example, by deflection of a frictional membrane into mechanical motion.

The production of different components such as sensors, micromechanical switches or sound sources is also known using the technique used in semiconductor manufacturing. Under at ^¬ alia sensors are produced, one based on a deformable membrane disposed on the piezo resistors. With these sensors, for example, an absolute pressure in relation to a Festge within a closed cavity below the membrane ^¬ set reference pressure can be detected. Due to the deformation of the membrane, a force is exerted on the piezoelectric bodies, which leads to a charge displacement in the piezoelectric body and thus to a voltage drop or change in resistance across the body.

Conversely, the application of an electrical voltage to a piezoelectric body causes its geometric deformation. The scored Motion is dependent on the polarity of the applied voltage and the direction of the vector of polarization.

Special attention in the production of micro-mechanical components with membranes and piezoresistors therefore find especially the geometry of the membrane and the arrangement, shape and nature of the piezoresistors.

From the Proceedings of SPIE Volume 2642 of the Micromachining and Micro-fabrication Symposium, Oct. 23-24, located in Austin, TX, microelectromechanical sensors based on a deformable silicon nitride diaphragm with polysilicon piezoresistors are known. With the help of the sensors, based on the reference pressure in the cavity below the membrane, an absolute pressure can be measured. All materials and process steps for manufacturing the sensors can be integrated into a CMOS process. In this case, an insulator layer (silicon nitride layer) is first produced on a carrier material. Thereafter, a thick oxide layer (TEOS) and then again a thin oxide layer (BPSG) are applied to the insulator layer, both of which are patterned after application. Subsequently, a nitride layer for the subsequent membrane is applied and also structured. Thereafter, the two oxide layers below the nitride layer are etched in an HF solution to form a cavity below the nitride layer, and then the etch openings are sealed with nitride. Subsequently, the piezoresistive polysilicon is first applied, implanted and patterned and then aluminum is applied and patterned.

The US 6959608B2 discloses a piezoresistive pressure sensor and a method for its production on the basis of an SOI wafer. In this case, first a narrow gap is etched into the silicon and oxide layer, and then the wafer is covered with a nitride layer to fill the gap with nitride. After removing the remaining nitride, a layer of doped, epitaxially grown silicon is deposited to structure resistors and connections. Subsequently, an aluminum layer is deposited and patterned, and thereafter a narrow etch hole is made in the silicon layer to etch a cavity in the oxide layer of the wafer by means of RF. Finally, a layer of oxide (LTO) is applied to the wafer, which simultaneously serves to reseal the etching opening.

A disadvantage of this method is that the etching process within the buried oxide layer can be poorly controlled and reproduced.

The object of the invention is to overcome the disadvantages of the prior art.

This object is achieved by a method of the type mentioned above with the features of claim 1 and by a device according to claim 17. Favorable embodiments are the subject of dependent claims.

Accordingly, the essence of the invention is to carry out the following steps in succession in a method for producing integrated microelectromechanical components. During the processing of a wafer, first of all a silicon layer is deposited on an insulator layer and then on the silicon layer a piezoresistive layer or the silicon layer is doped in subregions for producing a piezoresistive layer. Thereafter, at least one etch opening for etching at least one cavity is fabricated substantially within the silicon layer.

Alternatively, the sequence of steps may also be carried out so that first a silicon layer is deposited on an insulator layer. Then, at least one etching opening for etching at least one cavity in

Essentially produced within the silicon layer and subsequently 7 001344

The piezoresistive layer is deposited on the silicon layer or the silicon layer is doped in subregions for producing the piezoresistive layer.

After the etching, a self-supporting membrane whose thickness and maximum stroke are predetermined by the original thickness of the silicon layer remains above the cavity

These simple manufacturing processes have the advantage that they can be well integrated into standard processes and can be integrated with other circuit components.

According to an advantageous development of the invention, deep trenches, so-called trenches, are preferably produced within the silicon layer, which extend down to the insulator layer and are likewise filled with an insulating material, for example oxide, for the lateral delimitation of the cavity. These serve in the etching of the cavity due to the high selectivity of the etching medium as a lateral Ätzstopps. Furthermore, they also isolate the individual micro-electro-mechanical components from each other. It is therefore particularly advantageous to produce the trenches circumferentially and thus also to determine the shape of the cavities. In this case, it is also possible to arrange the trenches in such a way that several cavities communicate within a micro-electro-mechanical component after the etching.

According to one development of the invention, the silicon layer, which is preferably a polysilicon, is selectively doped in order to obtain piezoresistive regions. Alternatively, a doped, preferably implanted, polysilicon may be provided as the starting material for the piezoresistive layer, or a diffusion-doped polysilicon may be used. Become. It is also possible to use other piezoresistive materials such as lead zirconate titanate ceramics (PZT) or aluminum nitride. Furthermore, the invention provides to structure the piezoresistive layer to produce piezoelectric resistors, by means of which the deflection of the cantilevered membrane can be detected, as they change their electrical resistance under the influence of mechanical stresses. As an alternative to structuring the piezoresistive layer, the piezoelectric resistors can also be produced by selectively doping the poly-silicon, which was used as the starting material for the piezoresistive layer, into partial areas. The individual resistors can be isolated from each other by pn junctions.

A development of the invention provides for depositing a second insulator layer, for example of silicon oxide SiO ₂ or silicon nitride Si ₃ N _4, on the silicon layer before the piezoresistive layer is produced. In this case, there is a very good reproducibility of the etching process, since the insulator layers serve as Ätzstoppschichten. The shape of the cavity is defined laterally by the vertical trenches, at the bottom by the first insulator layer and at the top by the second insulator layer. Thus, the size and geometry of the cavity are determined by the distance and shape of the trenches in the sacrificial layer and the thickness of the silicon layer. In this case, the second insulator layer serves as a self-supporting membrane after the cavity has been fabricated. A further advantage of the second insulator layer is that the piezoresistors which are arranged on it are also isolated from one another. Due to the good control of the sacrificial etching, the properties of the individual components or sensor elements on both the individual wafer and from wafer to wafer and lot to lot are well reproducible.

It is also preferable to close the at least one etching opening again. A development of the invention also provides that during the closing of the etching openings, a defined internal pressure is generated in the cavities, which provides a defined reference pressure in pressure measurements with the micro-electro-mechanical device. A further preferred embodiment of the method provides for the deposition and structuring of a plurality of metallization levels, which are used for electrically contacting the piezoresistive layer, and the deposition of the intervening dielectric layers before the production of a cavity.

It is also advantageous to provide a cover for the protection of the piezoresistive layer as a protective layer, preferably of Si ₃ N ₄ . On the one hand, the cover protects the piezoresistive structures, provided that they consist of a material which would be attacked during the sacrificial etching. On the other hand, the cover serves as a protective layer for the surface of the device from environmental influences in the subsequent application. The protective layer can also be structured in partial areas or removed again in order not to impair the mechanical properties of the membrane.

Furthermore, it is preferable to produce the first insulator layer on a carrier layer, for example a substrate. The starting material for the process according to the invention can thus be an SOI wafer.

According to a further embodiment, four piezo resistors can be connected to form a Wheatstone bridge. By a circuit as half or full bridge (two or four changing resistors) is an improved sensitivity of the device, eg. when used as a sensor, and also allows a temperature compensation. Non-variable resistors can be placed outside the membrane.

MEMS devices with piezoelectric layers are electromechanical converter components. These are capable of mechanical forces like

Pressure, strain or acceleration in an electrical voltage or

Charge transfer (direct piezoelectric effect) and an electrical to convert the voltage into mechanical motion or vibrations (inverse piezoelectric effect). Using these effects opens up the widest possible range of applications in all areas of technology. For example, the conversion of electrical voltages into mechanical movement can be used for piezoelectric actuators, eg translators, bending elements and piezo motors for micro- and nanopositioning, laser tuning, active vibration damping or pneumatic valves, etc. Likewise, the conversion of mechanical forces and accelerations is used for sensors, ignition elements, piezo keyboards, generators or for passive damping. The conversion from acoustic to electrical signals is used primarily in sonic and ultrasonic receivers, in noise analysis or in acoustic emission spectroscopy.

Furthermore, the conversion of electrical signals into vibrations or acoustic signals in sound and ultrasound transmitters, buzzers (Buzzer) or line ultrasound generators use.

Specifically, in voltage level or flow measurements in the Objekterken ^¬, medical diagnostics, in the high-resolution material recognition or sonar and echo sounders, both the direct and the inverse piezoelectric effect can be exploited. In order to obtain a sufficiently large sum signal or a better signal yield, it has proved to be advantageous to interconnect a plurality of microelectromechanical components in a network to form an array.

The invention further provides a microelectromechanical component having an insulator layer, a silicon layer and a patterned piezoresistive layer, wherein a cavity is provided within the silicon layer and a self-supporting membrane is provided above the cavity, on which at least parts of the piezoresistive, structured layer are arranged. According to an advantageous development, the microelectromechanical component has a second insulator layer underneath the structured, piezoresistive layer, which serves as a self-supporting membrane after the cavity arranged in the silicon layer is produced.

It is understood that the features mentioned above and those yet to be explained below can be used not only in the particular combination indicated, but also in other combinations or in isolation, without departing from the scope of the present invention.

The invention will be described in more detail with reference to the figures.

1 a to 1 g each show in a sectional view a sequence of process steps for the production of microelectromechanical components for use as piezoresistive pressure sensor according to a first embodiment.

FIGS. 2 a to 2 g each show in a sectional representation a sequence of process steps for the production of microelectromechanical components for use as a piezoresistive pressure sensor according to a second embodiment.

Fig. 3 shows a plan view of a micro-electro-mechanical device, which can be used as a pressure sensor.

1 a shows a section through a semiconductor material, for example an SOI wafer with a first buried insulator layer 1 on a carrier layer 13. On the insulator layer 1, in turn, a silicon layer 2, which may be monocrystalline as well as polycrystalline, has been deposited , In Fig. 1 b two trenches 11 can be seen, for lateral isolation of the The trench 11 can be filled with oxide on the one hand or can also be embodied as oxide scavenger with a filling of polysilicon or nitride. After the trench 11 has been produced, the trench 11, as in FIG 1 c, a second insulator layer 6, which consists, for example, of silicon nitride Si ₃ N ₄ or silicon oxide SiO _2, is deposited on the silicon layer 2 and the trench 11. According to the Opferatzung, this serves as a micro-mechanical membrane or at least as a part The piezoelectric resistors are structured from a piezoresistive layer 7, which consists for example of doped, mostly implanted polysilicon or another piezoresistive material. In FIG. 1 d, three piezoelectric resistors or parts thereof can be seen , which are usually interconnected. FIG. 1 e shows a protective layer 8 which covers the piezoresistive structures. This protective layer, which may for example also consist of silicon nitride Si ₃ N ₄ , protects the piezoelectric resistances and the surface of the component from later environmental influences on the one hand and on the other hand In the process of processing the wafer, materials such as doped polysilicon which were attacked during the later sacrificial etching are defined. Subsequently, openings 3 for the sacrificial formation for the production of the cavity 5 are defined. It is advantageous to preform these openings early in the process, since the 1g shows the further processing of the wafer in the back-end-of-Lιne (BEOL) Here, one or more metallization layers with intervening insulating dielectric layers 9 are deposited for contacts and Leitbahnen and structured After the electrical contact d he wafer is the BEOL, as can be seen in Figure 1 h, reopened by means of an anisotropic etching and thus also the already defined openings 3 and also the surface of the later sensor exposed. Subsequently, by means of an isotropic etching, the sacrificial layer, im In this case, the silicon layer 2 is removed and a cavity 5 is produced. In FIG. 1, it is clear that the cavity 5 is delimited at the bottom by the insulator layer 1, at the sides by the trenches 1 1 and above by the insulator layer 6, all of which serve as an etching stop layer during the etching. The arrangement of these elements thus defines the size of the cavity and the parameters for the movable membrane. Fig. 1 j shows the closure of the cavity 5 by means of an optionally structured layer 10, which is preferably insulating.

FIGS. 2a to 2id also show the process sequence known from the aforementioned figures. However, as can be seen from FIG. 2 a, prior to the deposition of the second insulator layer 6 on the first conductive layer 2, a further thin sacrificial layer 12 of polysilicon or similar material is deposited in partial regions. When the second insulator layer 6 is applied, this thin sacrificial layer 12 is completely covered and exposed only after the application and structuring of the piezoresistive layer 7 and its covering with a protective layer 8 again at at least one point. Fig. 2f shows the further processing of the wafer. The surface of the later membrane is provided with a cover of one or more insulating layers 9. In the anisotropic etching to expose the access to the sacrificial layer 12, a part of the cover is removed again. In the subsequent isotropic etching, access to the silicon layer 2 is released since the sacrificial layer 12 is completely or partially removed. The lower insulator layer 1, Trenche 1 1 and the second insulator layer 6 serve again as Ätzstoppschicht. FIG. 2i shows the component with a closed membrane, the closure 10 of the etching opening 3 preferably consisting of an insulator.

FIG. 3 shows a plan view of a micro-electro-mechanical component, wherein the covering layer is not shown above the piezo-resistors. On the circular membrane, in which the shutter 10 of the etching openings in the middle, four piezo-resistors are arranged; these are via interconnects 4, which are made of metallization or alternatively doped Poly silicon exist, contacted. However, the shape and arrangement of the piezoelectric resistors are variable. For example, the resistors may be designed such that they have a meandering structure or a meandering outline. Furthermore, it is also possible to arrange each two opposing resistors rotated by 90 °. The vibrational states or forms of the membrane are largely determined by their geometry and mechanoelastic properties.

LIST OF REFERENCE NUMBERS

I insulator layer 2 silicon layer

3 etch hole

4 contacts and interconnects

5 cavity

6 Second insulator layer 7 piezoresistive layer - piezoelectric resistance

8 protective layer

9 BEOL with typical layers

10 closure of the etch hole

I 1 trench 12 sacrificial layer

13 carrier material

Claims

claims

1 . Method of making integrated micro-electro-mechanical devices comprising the steps

Producing a silicon layer (2) on an insulator layer (1),

Producing a piezoresistive layer (7) on or in the silicon layer (2),

• Producing at least one etching opening (3) for etching at least one cavity (5) substantially within the silicon layer (2).

2. Method for the production of integrated micro-electro-mechanical components with the steps

Producing a silicon layer (2) on an insulator layer (1),

Producing a piezoresistive layer (7) on or in the silicon layer (2),

3. The method according to claim 1 or 2 with the step

• Creating a trench (1 1) for lateral delimitation of the cavity (5).

4. The method according to claim 3, characterized in that a circulating trench (1 1) is produced.

5. The method according to any one of the preceding claims, character- ized in that for producing the piezoresistive layer (7) the Silicon layer (2) doped at least in some areas, preferably implanted.

6. The method according to any one of claims 1 to 4, characterized marked, that as a starting material for the piezoresistive layer (7) a doped, preferably implanted polysilicon is provided.

7. The method according to any one of claims 1 to 4, characterized in that at least in partial areas, a diffusion-doped polysilicon is provided as the starting material for the piezoresistive layer (7).

8. The method according to any one of the preceding claims with the step

• Producing a second insulator layer (6) on the silicon layer (2) before producing the piezoresistive layer (7).

9. The method according to any one of the preceding claims with the step

• Producing piezo resistors by structuring the piezoresistive layer (7).

10. The method according to any one of claims 1 to 8 with the step

Producing piezoelectric resistors by selective doping of a silicon layer, which is preferably made of polysilicon.

1 1. Method according to one of the preceding claims, characterized in that the at least one etching opening (3) is closed.

12. The method according to any one of the preceding claims, character- ized in that the electrical contact (4) of the piezoresistive

Layer (7) before producing a cavity (5) is provided.

13. The method according to any one of the preceding claims, characterized in that for the protection of the piezoresistive layer (7) a protective layer (8), preferably made of Si ₃ N _{4 is} provided.

14. The method according to any one of the preceding claims, characterized in that during the closing of the etching openings (3), a defined internal pressure in the cavities (5) is generated.

15. The method according to any one of the preceding claims, characterized in that the insulator layer (1) on a carrier layer (13) is produced.

16. The method according to any one of claims 9 to 15, characterized in that four piezo-resistors are connected to form a Wheatstone bridge.

17. micro-electro-mechanical component having an insulator layer (1), a silicon layer (2) and a structured, piezoresistive layer (7), wherein within the silicon layer (2) has a cavity (5) and above the cavity (5) a cantilevered membrane is provided on the at least parts of the piezoresistive, structured layer (7) are angeord ^¬ net.

i δ. Microelectromechanical component according to claim 13, characterized in that a second insulator layer (6) is arranged below the structured piezoresistive layer (7) as a ^{self-supporting} membrane.