EP1594799A2

EP1594799A2 - Method for producing a micromechanical device and a micromechanical device

Info

Publication number: EP1594799A2
Application number: EP03815817A
Authority: EP
Inventors: Lars Metzger; Frank Fischer
Original assignee: Robert Bosch GmbH
Current assignee: Robert Bosch GmbH
Priority date: 2003-02-11
Filing date: 2003-09-25
Publication date: 2005-11-16
Also published as: WO2004071941A2; JP2006513047A; WO2004071941A3; DE10305442A1; US20060226114A1

Abstract

The invention relates to a method for producing a micromechanical device and to corresponding micromechanical device consisting of a substrate material (10), a membrane (20) and a hollow space (30) formed in the region of membrane (21) between said substrate and membrane. According to said invention holes (40) are embodied first and foremost in the membrane (20) during a first etching stage and afterwards, the hollow space is produced during a second etching stage.

Description

Method for producing a micromechanical device and device

State of the art

The invention is based on a method and a device according to the type of the independent claims. A micromechanical device emerges from the article by D. Moser and H. Baltes "A high sensitivity CMOS gas flow sensor on a thin dielectric membrane" and the journal Sensors and Actuators A 37-38 (1993), pp. 33-37 , in which a thermal decoupling between components and the carrier material (substrate) is realized, the device being manufactured in bulk micromechanics

Backside process necessary. The membrane required for thermal insulation, on which, for example, temperature sensors and heaters are located, is produced from the rear using a volume micromechanical process. The membrane is structured by a wet chemical etching process, for example using KOH. The entire substrate in the area of the membrane has to be etched from the back, which leads to long process times. Since the wet chemical etching solutions attack the functional layers on the front, the wafer must be installed in so-called etching cans so that the front is protected during the etching process. The method known from the prior art is therefore very complex and involves high costs, including the rear side process.

Advantages of the invention

The method according to the invention and the device according to the invention with the features of the independent claims have the advantage that a A method for producing membranes is provided in which only front processes are required. The method according to the invention and the device according to the invention can thus be produced in surface micromechanics (OMM). Furthermore, with the method according to the invention and the device according to the invention, it is possible to effect thermal insulation or thermal decoupling between components on or in the membrane and the carrier material, ie the substrate material. In particular, temperature sensors and / or heating elements for arrangement in or on the membrane are possible as components, but according to the invention any component is possible and conceivable, the production of which can be integrated into the manufacturing process of the device. A thermal

Decoupling is particularly required for thermal sensors such as thermocouples, chemical sensors and air mass sensors. The method and the device according to the invention have the advantage over the prior art that only surface micromechanical processes, i.e. only front-end processes are necessary to manufacture the device. This eliminates the complex rear processes such. B. the KOH etching by means of an etching can for structuring the membrane. Particles and scratches on the front of the wafer are minimized or avoided by eliminating the backside processes, in which the wafer has to be turned over and placed on the front. According to the invention, a surface micromechanical device is used to generate the thermal decoupling

Sacrificial layer technology is used, which has a high selectivity towards thermally insulating materials such as oxides and nitrides as well as towards metals. Silicon in particular is used as the sacrificial layer in the method according to the invention. The area of the sacrificial layer is, according to the invention, first of all by means of a first (anisotropic) etching step, in particular a DRTE etching method

(Deep reactive ion etching) deeply structured and then completely etched laterally in a second (isotropic) etching step, in particular by means of a XeF ₂ , C1F ₃ , BrF process, so that a cavity is created below the membrane. This creates a membrane area, ie the substrate area in which the membrane layer is self-supporting and thus spans the cavity. According to the invention, the membrane layer comprises thermally poorly conductive material, for example silicon oxide or silicon nitride. The combined sacrificial layer etching process according to the invention makes it possible to produce large sacrificial layer depths. The compatibility of the etching media used in the sacrificial layer set with the materials used in the standard CMOS processes that are known and known from the prior art enables them to be used it according to the invention that the manufacture of the device according to the invention and the manufacture of an integrated circuit (IC) manufactured in CMOS technology are integrated together, ie can be carried out in a (multi-step) manufacturing process.

The measures listed in the subclaims permit advantageous developments and improvements of the method and the device listed in the independent claims.

It is particularly advantageous that the holes in the membrane are closed after the second etching step, in particular with a cover layer or a cover. This makes it possible for the structures to be protected, for example, in a subsequent sawing process. According to the invention, a layer made of PECVD oxide or a spin-on glass or also a combination of different layers is particularly suitable as a sealing layer. Furthermore, a cap as a lid can be used as a closure of the holes. It is also particularly advantageous that, before the first etching step, a component to be thermally insulated from the substrate material is produced on or in the membrane. This makes it possible that after the second etching step no further steps producing a component are necessary, and thus in particular no problems arise because, for example, in the

Membranes are present after the two etching steps, into which material to be applied to the membrane could possibly penetrate or which could attack or damage the membrane from its rear. It is also particularly advantageous that the membrane is provided in a particularly well insulated manner from the substrate material. This is achieved according to the invention in particular by a comparatively large height of the cavity which is provided in the membrane area above the substrate material. As a result of various heat transport mechanisms in particular, there is only a small heat transport from the membrane into the substrate material and thus particularly good thermal insulation. It is also particularly advantageous that a silicon substrate, in particular a single crystal, or an SOI / EOI substrate is used as the substrate material

(silicon-on-insulator / epipoly-on-insulator substrate) is provided. The use of a SOI / EOI substrate can be used particularly advantageously according to the invention in that the oxide layer of the SOI / EOI substrate serves as a vertical etching stop during the sacrificial layer etching, as a result of which a defined sacrificial layer thickness can be set. In the case of a SOI / EOI substrate, it is assumed that the layer structure is based on one monocrystalline silicon substrate, an oxide layer and subsequently a silicon layer is applied.

Overall, the method according to the invention allows the simple manufacture of a device according to the invention, in particular of sensor elements, in which a thermal decoupling between temperature sensors and / or heating elements and the carrier material or substrate is necessary. According to the invention, only a few layers and photolithography steps are necessary to carry out the process according to the invention, so that the method can be carried out simply and inexpensively.

drawing

Embodiments of the invention are shown in the drawing and explained in more detail in the following description. Show it

FIG. 1 shows a first embodiment of the substrate material with a first part of a membrane layer in a sectional view,

FIG. 2 shows the first embodiment of the substrate material with the first part of the membrane layer and a component integrated in the membrane layer in a sectional view,

3 shows the first embodiment of the substrate material with a membrane layer and a partially performed first etching step in a sectional view, FIG. 4 shows the first embodiment of the substrate material with a membrane layer and a completely performed first etching step in a sectional view, FIG. 5 shows the first embodiment of the substrate material with a membrane layer and performed first and second etching steps 6 and 7, the first embodiment of the substrate material with a membrane layer and the first and second etching steps carried out completely and a first and second embodiment of a closure of holes in the membrane in a sectional view, FIG. 8 a second embodiment of the substrate material with a membrane layer and the first one carried out completely Etching step in sectional view and Figure 9 shows the second embodiment of the substrate material with membrane layer and performed first and second etching step i n sectional view.

Description of the embodiments FIG. 1 shows a first embodiment of the substrate material 10 with a first part 21 of a membrane layer in a sectional view. The first part 21 of the membrane layer should be under tension and have a certain thermal conductivity. According to the invention, the first part 21 of the membrane layer comprises, in particular, a first partial membrane layer 22, which is provided in particular as an oxide layer. According to the invention, the first partial membrane layer 22 has been produced, for example, as a thermal oxide layer or as a PECVD oxide layer. According to the invention, the first part 21 of the membrane layer further comprises in particular a second partial membrane layer 24, which is provided in particular as a nitride layer. According to the invention, the second partial membrane layer 24 has been produced, for example, as a PECVD nitride layer or as an LPCVD nitride layer. The first part 21 of the membrane layer can, however, be provided in further embodiments of the invention, not shown, in the form of a layer system composed of oxide layers / nitride layers. According to the invention, the layer thicknesses of the first and second partial membrane layers 22, 24 are in the range of approximately 0.5-5 μm. In the first embodiment of the substrate material 10, this in particular comprises a semiconductor material 12, preferably monocrystalline silicon material 12.

FIG. 2 shows the first embodiment of the substrate material 10 with the first part 21 of the membrane layer 20 and a component which is integrated in the membrane layer 20 and is not specifically designated by a reference symbol in a sectional illustration. According to the invention, the component is provided and described by way of example as a thermocouple or temperature sensor, but can be any component that can be integrated in or on a membrane. The thermocouple has, for example, a known platinum resistance or a known Si / Al or also Si / Ge thermopile, which is produced using known methods. To produce a thermopile as a thermocouple, a structured layer, in particular a poly-silicon layer, is first applied to the membrane 20, which comprises a first region 201 and possibly a second region 202. The first region 201 forms a first resistor, which is also referred to below with the reference number 201.

The first and second regions 201, 202 can also be provided completely electrically separate from one another, but can be structured out of the same layer. Subsequent to the application of the first resistor 201, an intermediate oxide layer 203 and a second resistor 204, which according to the invention are made in particular of aluminum material or germanium material, are deposited and structured consists. As a result of the contact between the first and second resistor 201, 204, which is not identified by a reference numeral, a thermocouple is formed from the first and second resistor 201, 204. In order to contact the connections of the thermocouple, bond pads 206 or generally contacting areas 206 are produced, which are made, for example, of aluminum material. In this way, the membrane 20 results from the first part 21 of the membrane layer and the “structure” of the component - in the exemplary embodiment as a thermocouple - on the first part 21 of the membrane layer. However, in another embodiment of the invention, not shown, the membrane 20 could also be constructed in this way be that, for example, the component is provided below the first and second partial membrane layers 22, 24. According to the invention, the substrate material 10 is in any case arranged “below” the membrane layer 20. In principle, this is provided in the same way in all the following figures and is therefore not described repeatedly. The basic structure of the component, for example as a thermocouple, is in principle retained in the other figures, which is why it is not described repeatedly.

FIG. 3 shows the first embodiment of the substrate material 10 with the membrane layer 20 and a partially performed first etching step in a sectional view. To produce the cavity according to the invention, vertical recesses, ie holes, are made in the membrane layer 20 or in the membrane 20 at certain perforation points provided with arrows and the reference numerals 28, 29 in FIG. For this purpose, it is provided according to the invention, in particular, to define the perforation points 28, 29 by means of a photoresist mask 26 shown only in dashed lines in FIG. 3 in that the photoresist mask 26 covers the entire membrane layer 20 except at the perforation points 28, 29. It is then possible to introduce holes 40 into the membrane layer 20 by means of a wet chemical or dry chemical first etching step, ie to drive the holes 40 through the cover oxide layer 205, the intermediate oxide layer 203 and the first and second partial membrane layers 22, 24. For this purpose, the etching process for the first etching step is provided in particular anisotropically. The perforation points 28, 29 and correspondingly also the holes 40 are located at points of the membrane layer 20 at which no parts of the components located on or in the membrane layer 20 can be damaged by the creation of the holes 40. Located in the vertical direction, ie in the direction of the introduction of the holes 40 into the membrane layer 20 which is extended over a large area there is therefore only a region of the substrate 10 provided as a sacrificial layer “below” a perforation point 28, 29. For the perforation points designated by reference numeral 28, this is clearly evident because the corresponding holes 40 do not match the (in FIG. 1 with reference numeral 201 or 204) of the first or second resistance of the thermocouple, for the perforation points designated by reference number 29 this is represented by the side walls of the corresponding holes 40 shown by dotted lines. This is intended to clarify that the holes 40 are suitable for those designated by the reference number 29 provided perforation points not in the sectional plane shown (in which the first and second resistance of the thermocouple is located), but in another sectional plane in which the

Component is not affected by the holes 40.

FIG. 4 shows the first embodiment of the substrate material 10 with a membrane layer 20 and a completely performed first etching step in a sectional view. Compared to FIG. 3, there is only the difference that the first etching step was carried out completely, i.e. the holes 40 are made up to a certain height 44 (or “depth”) in the substrate material 10 starting from the holes 40 made in the membrane layer 20 at the perforation points 28, 29 (cf. description of FIG. 3) for the first part of the first etching step shown in FIG. 3, an anisotropic etching process for deep structuring, in particular one

DRIE etching process used. The height 44 is shown in FIG. 4 by means of a double arrow below the first and second partial membrane layers 22, 24 into the substrate material 10. The height 44 of the holes 40 lies below the membrane layer 20 in the range from 2 μm to 200 μm. The depth structuring essentially specifies the depth (or height) of the sacrificial layer etching process. The holes 40 which are in the

Also referred to below as perforation holes 40, they can have a diameter between 0.5 μm and 500 μm. For applications in which the membrane should have as few holes 40 as possible (for example infrared detectors or mass flow sensors), the holes 40 are preferably smaller than 10 μm. Applications that require a membrane that is structured as strongly as possible (for example thermal conductivity sensors for H2 detection, sensors based on free convection flow for inclination measurement) preferably have holes 40 larger than 100 μm. FIG. 5 shows the first embodiment of the substrate material 10 with the membrane layer 20 and the first and second etching steps carried out in a sectional illustration. Starting from the manufacturing stage of the invention shown in Figure 4 The device is laterally etched by means of an isotropic semiconductor etching process as a second etching step, the trench structure predetermined by the holes 40 and not visible in the area of the membrane layer 20 in the area of the sacrificial layer, ie below the membrane 20. This is shown in FIG. 5 by means of four, double arrows which do not run horizontally and are not designated by a reference number. The access of the etching medium for the second etching step is shown through the holes 40 in FIG. 5 by means of arrows designated with the reference symbol 42. The etching process can be carried out, for example, using a XeF ₂ , C1F ₃ or BrF ₃ process. This creates a cavity 30 in the membrane area 21 between the membrane layer 20 and the non-etched part of the substrate material 10, and the membrane area 21 defines the self-supporting membrane 20 that supports the components or covers the cavity 30 above the cavity 30. The cavity 30 or cavern 30 has a height 31 which, according to the invention, essentially corresponds to the height 44 shown in FIG. 4 of the depth structuring of the holes 40 below the membrane region 20. The thermocouples or more generally located on or in the membrane 20

Components are thermally decoupled or insulated from the substrate material 10 by the cavern 30.

FIGS. 6 and 7 show the first embodiment of the substrate material 10 with the membrane layer 20 and the completely carried out first and second etching step and a first and second embodiment of a closure of the holes 40 in the membrane 20 in a sectional view. 6 shows the first embodiment of a closure of the holes 40 by means of a closure layer 50. FIG. 7 shows the second embodiment of closing the holes 40 by means of a cap 52. This will make the components or others

Structures, in particular on or in the membrane 20, are protected, for example, during the subsequent sawing process for separating a plurality of devices according to the invention which are jointly produced on a substrate wafer. The sealing layer 50 is designed in particular as a PECVD oxide or as a spin-on glass.

FIGS. 8 and 9 show a second embodiment of the substrate material 10 with the membrane layer 20 in a sectional view. FIG. 8 shows the first etching step carried out completely. FIG. 9 shows the first and second etching step carried out completely. In the second embodiment of the A substrate material with a sequence of different layers in the substrate material 10 is used, for example with a silicon-silicon oxide-silicon layer sequence. For example, a (silicon) oxide layer 16 and subsequently a silicon layer 15 are applied to a monocrystalline part 17 of the substrate material 10. The silicon layer 15 can be provided both as a monocrystalline silicon layer 15 or as an “epitaxially applied” polycrystalline silicon layer 15 (so-called EpiPoly silicon layer 15) EOI material spoken, but the manufacturing process is also in its steps in the second embodiment of the

Substrate material 10 analogous to that described in connection with FIGS. 1-7. The only difference is that the oxide layer 16 of the substrate material 10 ensures an etching stop at the end of the first etching step. Thus, by means of the deep structuring method of the first etching step, the holes 40 cannot penetrate deeper than the oxide layer 16 into the substrate material 10, i.e. completely by the as

Sacrificial layer used silicon layer 15 are introduced. This makes it possible to identify the end point of the first etching step. The depth structuring of the holes 40 beyond the membrane layer 20 extends over the height (or depth) designated by the reference symbol 44, which corresponds to the layer thickness of the silicon layer 15. Furthermore, the height 31 of the cavern 30 corresponds to

Thickness of the silicon layer 15 of the substrate material.

Claims

claims

1. A method for producing a micromechanical device with a substrate material (10) and with a membrane (20), characterized in that a cavity (30) is provided in a membrane region (21) between the substrate material (10) and the membrane (20) wherein, to produce the cavity (30), holes (40) are first made in the membrane (20) by means of a first anisotropic etching step and then the cavity (30) is created by means of a second isotropic etching step.

2. The method according to claim 1, characterized in that part of the substrate material (10) is provided as a sacrificial layer, the holes (40) being introduced into the region of the sacrificial layer in the first etching step.

3. The method according to claim 1 or 2, characterized in that the method is CMOS compatible.

4. The method according to any one of the preceding claims, characterized in that during the first etching step

Deep structuring process, in particular a DRIE process (deep reactive ion etch process) is used.

5. The method according to any one of the preceding claims, characterized in that the second etching step by means of a XeF ₂ -, C1F ₃ -, BrF - or SF ₆ - Plasma or wet chemical is carried out using TMAH or KOH or HNO ₃ / HF.

6. The method according to any one of the preceding claims, characterized in that the holes (40) in the membrane (20) after the second

Etching step, in particular with a cover layer (50) or a lid (52), are closed.

7. The method according to any one of the preceding claims, characterized in that before the first etching step a thermally from the substrate material

(10) component to be insulated is generated on or in the membrane (20).

8. Micromechanical device with a substrate material (10) and with a membrane (20), produced by a method according to one of the preceding claims.

9. The device according to claim 8, characterized in that the membrane (20) from the substrate material (10) is provided particularly well thermally insulated.

10. The device according to claim 8 or 9, characterized in that as

Substrate material (10), a silicon substrate or an SOI substrate (silicon-on-insulator substrate) is provided.

11. The device according to claim 10, characterized in that the height (31) of the cavity (30) substantially the height (44) of the holes (40) in

Corresponds to substrate material (10).

12. Device according to one of claims 8-11, characterized in that one or more thermally insulated components, in particular thermocouples or heating elements, is / are provided on or in the membrane (20).