EP1974375A2 - Germanium sur des structures en verre ou verre-ceramique - Google Patents

Germanium sur des structures en verre ou verre-ceramique

Info

Publication number
EP1974375A2
EP1974375A2 EP06849096A EP06849096A EP1974375A2 EP 1974375 A2 EP1974375 A2 EP 1974375A2 EP 06849096 A EP06849096 A EP 06849096A EP 06849096 A EP06849096 A EP 06849096A EP 1974375 A2 EP1974375 A2 EP 1974375A2
Authority
EP
European Patent Office
Prior art keywords
glass
semiconductor
germanium
ceramic
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06849096A
Other languages
German (de)
English (en)
Inventor
Paul S Danielson
Matthew J Dejneka
Kishor P Gadkaree
Josef C Lapp
Linda R Pinckney
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Corning Inc
Original Assignee
Corning Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/415,732 external-priority patent/US7456057B2/en
Application filed by Corning Inc filed Critical Corning Inc
Publication of EP1974375A2 publication Critical patent/EP1974375A2/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C3/00—Glass compositions
    • C03C3/04—Glass compositions containing silica
    • C03C3/062—Glass compositions containing silica with less than 40% silica by weight
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C27/00—Joining pieces of glass to pieces of other inorganic material; Joining glass to glass other than by fusing
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C3/00—Glass compositions
    • C03C3/04—Glass compositions containing silica
    • C03C3/062—Glass compositions containing silica with less than 40% silica by weight
    • C03C3/064—Glass compositions containing silica with less than 40% silica by weight containing boron
    • C03C3/068—Glass compositions containing silica with less than 40% silica by weight containing boron containing rare earths
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C3/00—Glass compositions
    • C03C3/04—Glass compositions containing silica
    • C03C3/076—Glass compositions containing silica with 40% to 90% silica, by weight
    • C03C3/083—Glass compositions containing silica with 40% to 90% silica, by weight containing aluminium oxide or an iron compound
    • C03C3/085—Glass compositions containing silica with 40% to 90% silica, by weight containing aluminium oxide or an iron compound containing an oxide of a divalent metal
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C3/00—Glass compositions
    • C03C3/04—Glass compositions containing silica
    • C03C3/076—Glass compositions containing silica with 40% to 90% silica, by weight
    • C03C3/083—Glass compositions containing silica with 40% to 90% silica, by weight containing aluminium oxide or an iron compound
    • C03C3/085—Glass compositions containing silica with 40% to 90% silica, by weight containing aluminium oxide or an iron compound containing an oxide of a divalent metal
    • C03C3/087—Glass compositions containing silica with 40% to 90% silica, by weight containing aluminium oxide or an iron compound containing an oxide of a divalent metal containing calcium oxide, e.g. common sheet or container glass
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C3/00—Glass compositions
    • C03C3/04—Glass compositions containing silica
    • C03C3/076—Glass compositions containing silica with 40% to 90% silica, by weight
    • C03C3/089—Glass compositions containing silica with 40% to 90% silica, by weight containing boron
    • C03C3/091—Glass compositions containing silica with 40% to 90% silica, by weight containing boron containing aluminium
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C3/00—Glass compositions
    • C03C3/04—Glass compositions containing silica
    • C03C3/076—Glass compositions containing silica with 40% to 90% silica, by weight
    • C03C3/095—Glass compositions containing silica with 40% to 90% silica, by weight containing rare earths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys

Definitions

  • the present invention relates to semiconductor-on-insulator (SOI) structures, such, as semiconductor on glass or glass ceramic, and methods for making same.
  • SOI semiconductor-on-insulator
  • the present invention relates to germanium on glass or glass-ceramic structures (GeOG), and more particularly germanium on expansion-matched glass or glass-ceramic substrates.
  • GeOG germanium on glass or glass-ceramic structures
  • silicon-on-insulator structures have been referred to in the literature as silicon-on-insulator structures and the abbreviation "SOI" has been applied to such structures.
  • SOI semiconductor-on-insulator technology is becoming increasingly important for high performance photovoltaic applications (e.g., solar cells), thin film transistor applications, and displays, such as, active matrix displays.
  • Known silicon-on-insulator wafers consist of a thin layer of substantially single crystal silicon (generally 0.1-0.3 microns in thickness but, in some cases, as thick as 5 microns) on an insulating material.
  • the SOI abbreviation is used herein to refer to semiconductor-on-insulator structures in general, including, but not limited to, both silicon-on-insulator and germanium-on-insulator structures.
  • the SOG abbreviation is used to refer to semiconductor-on-glass structures in general, including, but not limited to, silicon-on-glass (SiOG) and germanium-on-glass structures (GeOG).
  • SiOG silicon-on-glass
  • GeOG germanium-on-glass structures
  • the SOG nomenclature is also intended to include semiconductor-on-glass-ceramic structures, including, but not limited to, silicon-on-glass-ceramic structures.
  • the abbreviation SOI encompasses SOG structures.
  • the various ways of obtaining SOI structures include epitaxial growth of Si on lattice matched substrates.
  • An alternative process includes the bonding of a single crystal silicon wafer to another silicon wafer on which an oxide layer of SiO 2 has been grown, followed by polishing or etching of the top wafer down to, for example, a 0.1 to 0.3 micron layer of single crystal silicon.
  • Further methods include ion-implantation methods in which either hydrogen or oxygen ions are implanted either to form a buried oxide layer in the silicon wafer topped by Si in the case of oxygen ion implantation or to separate (exfoliate) a thin Si layer to bond to another Si wafer with an oxide layer as in the case of hydrogen ion implantation.
  • the former two methods have not resulted in satisfactory structures in terms of cost and/or bond strength and durability.
  • the latter method involving hydrogen ion implantation has received some attention and has been considered advantageous over the former methods because the implantation energies required are less than 50% of that of oxygen ion implants and the dosage required is two orders of magnitude lower.
  • Exfoliation by the hydrogen ion implantation method typically consists of the following steps. A thermal oxide layer is grown on a single crystal silicon wafer. Hydrogen ions are then implanted into this wafer to generate subsurface flaws. The implantation energy determines the depth at which the flaws are generated and the dosage determines flaw density. This wafer is then placed into contact with another silicon wafer (the support substrate) at room temperature to form a tentative bond. The wafers are then heat-treated to about 600 degrees C to cause growth of the subsurface flaws for use in separating a thin layer of silicon from the Si wafer.
  • the resulting assembly is then heated to a temperature above 1 ,000 degrees C to fully bond the Si film with SiO 2 underlayer to the support substrate, i.e., the unimplanted Si wafer.
  • This process thus forms an SOI structure with a thin film of silicon bonded to another silicon wafer with an oxide insulator layer in between.
  • Cost is an important consideration for commercial applications of SOI structures.
  • a major part of the cost of the above-described method and structure has been the cost of the silicon wafer which supports the oxide layer, topped by the Si thin film, i.e., a major part of the cost has been the support substrate.
  • quartz is itself a relatively expensive material.
  • some of the above references have mentioned quartz glass, glass, and glass-ceramics.
  • Other support substrate materials listed in these references include diamond, sapphire, silicon carbide, silicon nitride, ceramics, metals, and plastics.
  • U.S. Patent No.: 5,374,564 discloses a process to obtain a single crystal silicon film on a substrate using a thermal process.
  • a semiconductor material wafer having a planar face is subject to the following steps: (i) implantation by bombardment of a face of the wafer by means of ions creating a layer of gaseous micro-bubbles defining a lower region constituting the mass of the substrate and an upper region constituting the thin film; (ii) contacting the planar face of the wafer with a stiffener constituted by at least one rigid material layer; and (iii) a third stage of heat treating the assembly of the wafer and the stiffener at a temperature above that at which the ion bombardment was carried out and sufficient to create a pressure effect in the micro-bubbles and a separation between the thin film and the mass of the substrate. Due to the high temperature steps, this process does not work with lower cost glass or glass-ceramic substrates.
  • U.S. Patent Application No.: 2004/0229444 discloses a process for producing a SOG structure. The steps include: (i) exposing a silicon wafer surface to hydrogen ion implantation to create a bonding surface; (ii) bringing the bonding surface of the wafer into contact with a glass substrate; (iii) applying pressure, temperature and voltage to the wafer and the glass substrate to facilitate bonding therebetween; and (iv) cooling the structure to a common temperature to facilitate separation of the glass substrate and a thin layer of silicon from the silicon wafer.
  • the SOI formation technique disclosed in U.S. Patent Application No.: 2004/0229444 has been shown to result in a relatively thin semiconductor layer (e.g., about 1-5 urn) bonded to a glass substrate.
  • these silicon or silicon-based alloys/oxide glass or an oxide glass-ceramic based SOI structures may not provide a satisfactory layer semiconductor thickness for other applications; e.g., MOS transistors, optical detectors and other optoelectronic devices, and high performance solar cells/photovoltaic devices.
  • germanium is effective in thin film, high performance/high quantum efficiency applications/devices as a result of germanium's higher carrier (hole and electron) mobility and optical absorption when compared to those of silicon, hi addition to having high electron and hole mobilities, germanium has other advantages such as lower contact resistance and lower dopant activation temperatures than those required by silicon, thus facilitating the formation of shallow junctions.
  • insulator While the "insulator" described in references these studies is generally a buried insulator layer, typically an oxide or nitride, within a semiconducting material (Ge, Si, GaAs, SiC...), glass is disclosed as a possible, non-semiconducting material, substrate.
  • a semiconducting material Ge, Si, GaAs, SiC
  • Glass is disclosed as a possible, non-semiconducting material, substrate.
  • One problem associated with the use of glass as a substrate material when bonded to Ge is the potential thermal expansion mismatch between the Ge film and the substrate to which it is bonded; this phenomenon is particularly problematic in the case of Ge film on a silica glass. Significant expansion mismatches would lead to high film stresses and probable crazing or delamination.
  • GeOI particularly GeOG devices which comprise a glass insulator/substrate that does not exhibit the aforementioned expansion mismatch problem; i.e., a GeOG device in which the substrate possesses thermal expansion characteristics that are compatible with those CTE characteristics of the Ge semiconducting film.
  • One embodiment of the present invention relates to a semiconductor-on-insulator structure including first and second layers which are attached to one another either directly or through one or more intermediate layers.
  • the first layer includes a substantially single crystal germanium semiconductor material while the second layer comprises a glass or a glass-ceramic material having a linear coefficient thermal of expansion (25-300 0 C) which is within the range of +/- 20xl0 '7 /°C of the linear coefficient thermal of expansion of the germanium first layer.
  • the second layer comprises a glass or a glass-ceramic material having a linear coefficient thermal of expansion (25-300 0 C) which is within the range of +/- 10xl0 "7 /°C of the linear coefficient thermal of expansion of the-germanium first layer.
  • FIG. 1 is a block diagram illustrating the structure of a GeOG device in accordance with one or more embodiments of the present invention.
  • FIG. 2 is a flow diagram illustrating process steps that may be carried out to produce the GeOG structure of FIG. 1.
  • FIG. 3 is block diagrams illustrating a process of forming the GeOG structure of FIG. 1 using the process of FIG. 2.
  • FIG. 4 is a block diagram illustrating a process of bonding a glass substrate to the intermediate structure of FIG. 3.
  • FIG. 5 is a schematic cross-sectional view of a GeOG structure according to another embodiment of the present invention.
  • FIG. 6 is TOF-SIMs depth profile of a GeOG structure of the type illustrated in FIG. 4 and made in accordance with the invention described herein. DETAILED DESCRIPTION OF THE PRESENT INVENTION
  • the GeOG structure 100 preferably includes a first layer 102 which comprises a substantially single crystal semiconductor material comprising germanium and a second layer 104 which comprises a glass or a glass-ceramic having a linear coefficient thermal of expansion (25-300°C) which is within the range of +/- 20xl0 "7 /°C of the linear coefficient thermal of expansion of the germanium first layer.
  • the GeOG structure 100 preferably includes a first layer 102 which comprises a substantially single crystal semiconductor material comprising germanium and a second layer 104 which comprises a glass or a glass-ceramic having a linear coefficient thermal of expansion (25-300°C) which is within the range of +/- 10x10 " 7 /°C of the linear coefficient thermal of expansion of the germanium first layer.
  • the GeOG structure 100 has suitable uses in connection with fabricating thin film transistors (TFTs), e.g., for display applications, including organic light-emitting diode (OLED) displays and liquid crystal displays (LCDs), and integrated circuits.
  • TFTs thin film transistors
  • OLED organic light-emitting diode
  • LCDs liquid crystal displays
  • This thin Ge film/glass GeOG structure is particularly suitable for use in and high performance solar cells/photovoltaic devices.
  • the semiconductor material of the layer 102 is preferably in the form of a substantially single-crystal germanium material.
  • the word “substantially” is used in describing the layer 102 to take account of the fact that semiconductor materials normally contain at least some internal or surface defects either inherently or purposely added, such as lattice defects or a few grain boundaries.
  • the word “substantially” also reflects the fact that certain dopants may distort or otherwise affect the crystal structure of the bulk semiconductor.
  • a substantially single-crystal germanium material comprises at least 90% Ge, and thus may include up to 10% include up other constituents and/or dopants, for example Si.
  • the first, Ge semiconductor, layer 102 can have virtually any suitable thickness, though typically less then about 1 ⁇ m in thickness, and is desirably between about 0.05 to 0.5 ⁇ m in thickness for electronic applications and desirably between .1 and lO ⁇ m in thickness for photovoltaic applications.
  • the germanium semiconductor material of the first layer typically exhibits a CTE (25-300 0 C) of about 61xlO '7 /°C.
  • the glass or glass-ceramic substrate 104 is preferably formed from an oxide glass or an oxide glass-ceramic.
  • the embodiments described herein preferably include an oxide glass or glass-ceramic exhibiting a strain point of less than about 1 ,000 degrees C.
  • the strain point is the temperature at which the glass or glass-ceramic has a viscosity of 10 14 ' 6 poise (1O 13 ' 6 Pa.s).
  • the glasses are presently preferred because they are typically simpler to manufacture, thus making them more widely available and less expensive.
  • the glass substrate preferably has a thickness in the range of about 0.1 mm to about 10 mm and most preferably in the range of about 0.5 mm to about 1 mm.
  • insulating layers having a thickness greater than or equal to about 1 micron are desirable, e.g., to avoid parasitic capacitive effects, which may arise when the GeOG structures are operated at high frequencies. In the past, such thicknesses have been difficult to achieve.
  • a GeOG structure having an insulating layer thicker than about 1 micron is readily achieved by simply using a glass substrate 104 having a thickness that is greater than or equal to about 1 micron.
  • the glass or glass-ceramic substrate 104 should be thick enough to support the Ge- semiconductor layer 102 through the process steps of the invention, as well as subsequent processing performed on the GeOG structure 100. Although there is no theoretical upper limit on the thickness of the glass substrate 104, a thickness beyond that needed for the support function or that desired for the ultimate GeOG structure 100 is generally not preferred since the greater the thickness of the glass substrate 104, the more difficult it will be to accomplish at least some of the process steps in forming the GeOG structure 100.
  • the oxide glass or oxide glass-ceramic substrate 104 is preferably silica-based.
  • the amount of SiO 2 in the oxide glass or oxide glass-ceramic is desirably greater than 30 weight % and in some embodiments as high as 70 weight %.
  • Non-silica-based glasses and glass-ceramics may be used in the practice of one or more embodiments of the invention, but are generally less preferred because of their higher cost and/or inferior performance characteristics.
  • the critical feature of the glass regardless of whether it is silica or non-silica based, is that it exhibit a linear coefficient thermal of expansion (25- 300 0 C) which is within the range of +/- 20xl0 "7 /°C of the linear coefficient thermal of expansion of the germanium -which is generally about is 61 x 10 "7 /°C.
  • the linear coefficient thermal of expansion (25-300 0 C) of the glass substrate should be within the range of 50-70x10 "7 /°C and in still further embodiments the linear coefficient thermal of expansion (25-300 0 C) of the glass substrate should match that of germanium and be about 61xl0 "7 /°C
  • the glass or glass-ceramic 104 is preferably transparent in the visible, near UV, and/or IR wavelength ranges, e.g., the glass or glass ceramic 104 is preferably transparent in the 350 run to 2 micron wavelength range .
  • the glass or glass-ceramic substrate 104 is preferably composed of a single glass or glass-ceramic, laminated structures can be used if desired.
  • the layer of the laminate closest to the Ge semiconductor layer 102 preferably has the properties discussed herein for a glass substrate 104 composed of a single glass or glass-ceramic.
  • Layers farther from the Ge semiconductor layer 102 preferably also have those properties, but may have relaxed properties because they do not directly interact with the Ge semiconductor layer 102. In the latter case, the glass or glass-ceramic substrate 104 is considered to have ended when the properties specified for a glass substrate 104 are no longer satisfied.
  • Desirable glasses for use in the present invention include alkali, alkaline earth, or rare earth aluminosilicate or boroaluminosilicate glasses having the aforementioned CTE characteristic of a linear coefficient thermal of expansion (25-300 0 C) which is within the range of +/- 20xl0 "7 /°C of the linear coefficient thermal of expansion of the germanium. Additionally, it is desirable that, due to germanium's relatively low melting point of ⁇ 973°C and thus the recommended bonding temperatures which should generally be below the melting point of germanium. As such glass, glass-based substrates which exhibit a strain point temperatures of at least 500 0 C and up to 900 0 C can be utilized.
  • the glass for use in the instant gennanium-on-glass structures comprises a glass having a composition, calculated in weight percent and calculated from the batch on an oxide basis, of: " 15-45% SiO 2 , 7.5-20% Al 2 O 3 , 15-45 % MgO+CaO+SrO+BaO and up to 55% RE 2 O 3 , RE being selected from the rare earth element group consisting Sc, Y, La 3 Ce, Pr, Nd, Sm, Eu, Gd, Tb-, Dy, Ho, Er, Tm, Yb, Lu and mixtures thereof.
  • the glass for use in the instant germanium-on-glass structures comprises a glass having a composition comprising, calculated in weight percent and calculated from the batch on an oxide basis, of: 55-65% SiO 2 , 8-20% Al 2 O 3 , 0-8% B 2 O 3 ,, and 12-30% MgO+CaO+SrO+BaO+ZnO+TiO 2 -ZrO 2 . It is preferred that the composition above not include any alkali components (Na 2 O K 2 O, Li 2 O), however up to 10% alkali is however acceptable.
  • the glass for use in the instant germanium-on-glass structures comprises a glass having a composition comprising, calculated in weight percent and calculated from the batch on an oxide basis, of: 45-70% SiO 2, 2.5-30% Al 2 O 3 , 0-8% B 2 O 3 ,, 2.5-30% MgO+CaO+SrO+BaO and 1-20% La 2 O 3 +Y 2 O 3 .
  • Examples of representative CTE matching glass compositions suitable for use in the instant invention are given in weight % in Table I below; The skilled artisan can make these and other suitable glass compositions using standard methods.
  • the glasses listed below can be made by mixing the component oxide, halide (e.g., AlCl 3 ), nitrate, and/or carbonate (CaCO 3 ) powders in a ball mill for 1 hour to make a 1 kg batch. The mixed batch can then be loaded into a Pt crucible and melted in a 1550°- 1650 0 C globar furnace overnight, after which time the melted glass can be poured onto a steel plate and annealed between 700 0 C and 800 0 C to alleviate stress.
  • halide e.g., AlCl 3
  • nitrate nitrate
  • CaCO 3 carbonate
  • the properties of these glasses can be tailored by the skilled artisan by modifying the composition.
  • replacing La 2 O 3 with Y 2 O 3 will increase the strain point and decrease the CTE.
  • alkali and alkaline-earth ion-free compositions listed below can add small amounts (e.g., up to a few percent) alkali or alkaline-earth ions to the alkali and alkaline-earth ion-free compositions listed below in order to obtain glasses more suitable for use in the bonding methods described herein below.
  • sodium ions are well-known to be detrimental to silicon transistors, and presumably should be avoided for germanium as well. Larger alkali ions with lower diffusion rates may be acceptable, particularly as the peak processing temperature is 650 0 C or less. Therefore, the glass compositions are most preferably sodium-free. -Low-iron compositions are also preferred.
  • Desirable glass-ceramics for use in the present should exhibit the same .
  • aforementioned CTE characteristic of a linear coefficient thermal of expansion (25-300 0 C) which is within the range of +/- 20xl0 ⁇ 7 /°C of the linear coefficient thermal of expansion of the germanium.
  • the spinel glass-ceramics within the following compositional range can-be formulated to exhibit the necessary +/- 20xl0 '7 /°C CTE property.
  • Representative glass-ceramics for use in the instant germanium-on-glass structures include those disclosed below in Table III.
  • the glass-ceramics disclosed therein formed using standard glass-ceramic formation methods known to those skilled in the art.
  • the glass-ceramics disclosed below could be cerammed at temperatures ranging between 800-1000 0 C for periods ranging between 1-10 hours; the two examples below were cerammed at 800 0 C for lhour, followed by a 900 0 C treatment for 2 hours.
  • FIGS. 2 and 3 illustrate process steps that may be carried out in order to produce an intermediate structure in connection with fabricating the GeOG structure 100 of FIG. 1.
  • an exfoliation layer 122 is formed on a surface of the semiconductor wafer 120 (FIG. 3).
  • the semiconductor wafer 120 is preferably a substantially single -crystal Ge wafer.
  • the exfoliation layer 122 is preferably a relatively thin layer of germanium that may be separated from the Ge semiconductor wafer 120 (which will be discussed later herein).
  • one suitable method includes the use of ion implantation to create a weakened region below the surface of the germanium wafer 120.
  • hydrogen ion implantation may be employed, although other ions or multiples thereof may be employed, such as boron + hydrogen, helium. + hydrogen, or other ions known in the literature for exfoliation.
  • any other known or hereinafter developed technique suitable for forming the exfoliation layer 122 may be employed without departing from the spirit and scope of the present invention.
  • a single step hydrogen implantation alone is used and involves subjecting the Ge wafer to an H ion implant dosage of between lxl0 16 -lxl0 17 ions/cm 2
  • the Ge wafer is subject to multiple ion, low dosage, implant steps.
  • a combination H and He low dosage implantation is utilized and involves first subjecting the Ge wafer to an H ion implant dosage ranging between 1x10 15 to 5x10 16 ions/cm 2 , followed by a Helium implant dosage, again at low dosage level ranging between IxIO 15 to 5x10 16 ions/cm 2 .
  • the germanium wafer 120 is preferably treated to reduce the (e.g., hydrogen) ion concentration on the surface.
  • the semiconductor wafer 120 is preferably washed and cleaned and the exfoliation layer 122 is preferably subject to mild oxidation.
  • the mild oxidation treatments may include treatment in oxygen plasma, ozone treatments, treatment with hydrogen peroxide, hydrogen peroxide and ammonia, hydrogen peroxide and an acid or a combination of these processes. It is expected that during these treatments hydrogen terminated surface groups oxidize to hydroxyl groups, which in turn also makes the surface of the silicon wafer hydrophilic.
  • the treatment is preferably carried out at room temperature for the oxygen plasma and at temperature between 25-150 0 C for the ammonia or acid treatments. Following this treatment, the glass wafer is washed in a detergent followed by distilled water and thereafter further washed with nitric acid and then distilled water.
  • the intermediate structures are brought into direct or indirect contact to achieve the arrangement schematically illustrated in FIG.4.
  • the structure(s) comprising the Ge semiconductor wafer 120, the exfoliation layer 122 and the glass substrate 104 are heated under a differential temperature gradient.
  • the glass substrate 104 is heated to a higher temperature than the Ge semiconductor wafer 120 and exfoliation layer 122.
  • the temperature difference between the glass substrate 102 and the Ge semiconductor wafer 120 is at least 1°C, although the difference may be as high as about 100 to about 150 0 C.
  • This temperature differential is desirable for a glass having a coefficient of thermal expansion (CTE) matched to that of germanium since it facilitates later separation of the exfoliation layer 122 from the semiconductor wafer 120 due to thermal stresses.
  • CTE coefficient of thermal expansion
  • the preferred pressure range is between about 1 to about 50 psi.
  • the glass substrate 104 and the Ge semiconductor wafer 120 are preferably taken to a temperature within about +/- 150° C of the strain point of the glass substrate 104.
  • a voltage is applied across the intermediate assembly, preferably with the Ge semiconductor wafer 120 at the positive electrode and the glass substrate 104 the negative electrode.
  • the application of the voltage potential causes alkali or alkaline earth ions in the glass substrate 104 to move away from the Ge semiconductor/glass interface further into the glass substrate 104.
  • This accomplishes two functions: (i) an alkali or alkaline earth ion free interface is created; and-(-ii) the glass substrate 104 " becomes very reactive and bonds to the Ge semiconductor layer 102 strongly with the application of heat at relatively low temperatures.
  • FIG. 2 after the intermediate assembly is held under these conditions for some time (e.g., approximately 1 hr or less), the voltage is removed and the intermediate assembly is allowed to cool to room temperature.
  • the Ge semiconductor wafer 120 and the glass substrate 102 are then separated, which may include some peeling if they have not already become completely free, to obtain a glass substrate 104 with a thin Ge semiconductor layer 104 bonded thereto as illustrated in FIG. 1.
  • the separation is preferably accomplished via fracture of the exfoliation layer 122 due to thermal stresses.
  • mechanical stresses such as water jet cutting or chemical etching may be used to facilitate the separation .
  • the atmosphere during the bonding (heating and application of voltage) process may be either an inert atomosphere, such as nitrogen and/or argon or simply an ambient air atmosphere.
  • the resulting structure may include the glass substrate 104, and the Ge semiconductor layer 102 bonded thereto. Any unwanted Ge semiconductor material may be removed via polishing techniques, e.g., via CMP or other techniques known in the art to obtain the single crystal germanium layer 102 on the glass substrate 104.
  • Ge semiconductor wafer 120 maybe reused to continue producing other GeOG structures 100.
  • Semiconductor-on-glass structure 300 includes a first layer 302 and a second layer 304, substantially described above.
  • Semiconductor-on-insulator structure 300 includes, in order, the germanium semiconductor material (306); the germanium semiconductor material with an enhanced oxygen content (308); the glass or glass-ceramic having a linear coefficient thermal of expansion (25-300 0 C) which is within the range of +Y- 20xl0 ⁇ 7 /°C of the linear coefficient thermal of expansion of the germanium, with a reduced positive ion concentration for at least one type of positive ion (310); the glass or glass-ceramic material with an enhanced positive ion concentration for at least one type of positive ion (312); and the glass or glass ceramic (314).
  • Example 1 A Germanium wafer ( ⁇ 100>) exhibiting a 100mm diameter and a thickness of 500 microns thick was subjected to a hydrogen ion implantation process which involved utilizing a dosage of 4xlO 16 ions/cm 2 and implantation energy of 100KeV. The wafer was then treated in oxygen plasma, under standard conditions, for a period of 10 minutes so as to oxidize the surface groups.
  • the glass exhibited a 100 mm diameter, a linear thermal CTE matched to that of Germanium, and a strain point of 529°C.
  • the glass wafer was washed with Fischer scientific Contrad 70 detergent in ultrasonic bath for 15 minutes followed by distilled water wash for 15 minutes in ultrasonic bath.
  • the glass wafer was thereafter washed in 10% nitric acid, again followed by distilled water wash. Both these wafers were finally cleaned in a . spin washer dryer with distilled water in the clean room.
  • the two wafers were then brought into contact, ensuring that no air was trapped between the wafers, and then the wafers were introduced into SUSS MICROTEC bonder.
  • the glass wafer was placed on the negative electrode and the silicon wafer was placed on the positive electrode.
  • the two wafers were respectively heated to 525°C (germanium wafer) and 595°C (glass wafer). A potential of 1750Volts was applied across the wafer surface. The voltage was applied for 20 minutes at the end of which the voltage was brought to zero and the wafers were cooled to room temperature. The wafers were then easily separated resulting in a GeOG structure and a Ge wafer for later reuse.
  • An excellent quality GeOG sample was produced via this process. In particular the GeOG sample possessed a strongly adhered thin (0.5 ⁇ m), defect-free germanium film on glass surface.
  • Figure 6 shows the TOF-SiMs analysis indicating the barrier layer formation in the process.

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Abstract

La présente invention concerne une structure de semiconducteur sur isolant qui comprend une première couche et une seconde couche attachées l'une à l'autre directement ou par une ou plusieurs couches intermédiaires. La première couche inclut un semiconducteur fait pratiquement d'un seul cristal de germanium tandis que la seconde couche comprend une matière en verre ou en verre-céramique dont le coefficient de dilatation thermique linéique (25-300 °C) se trouve dans la plage de ± 20 x 10-7 / °C du coefficient de dilatation thermique linéique de la première couche de germanium.
EP06849096A 2006-01-03 2006-12-22 Germanium sur des structures en verre ou verre-ceramique Withdrawn EP1974375A2 (fr)

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US75593406P 2006-01-03 2006-01-03
US11/415,732 US7456057B2 (en) 2005-12-31 2006-05-01 Germanium on glass and glass-ceramic structures
PCT/US2006/049272 WO2007079077A2 (fr) 2006-01-03 2006-12-22 Germanium sur des structures en verre ou verre-ceramique

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US20080070340A1 (en) * 2006-09-14 2008-03-20 Nicholas Francis Borrelli Image sensor using thin-film SOI
EP2332170B1 (fr) 2008-09-26 2019-06-12 Corning Inc. Structures de semi-conducteur sur isolateur à base de verre-céramique et leur procédé de fabrication
US8341976B2 (en) 2009-02-19 2013-01-01 Corning Incorporated Method of separating strengthened glass
JP2012121757A (ja) * 2010-12-08 2012-06-28 Nippon Electric Glass Co Ltd 高屈折率ガラス
CN108658454A (zh) * 2018-07-31 2018-10-16 中南大学 一种低热膨胀系数无碱高铝硼硅酸盐玻璃及其制备方法

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US7176528B2 (en) * 2003-02-18 2007-02-13 Corning Incorporated Glass-based SOI structures
JP4726400B2 (ja) * 2003-05-29 2011-07-20 コニカミノルタオプト株式会社 ガラス基板の製造方法
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WO2007079077A3 (fr) 2007-12-13
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