Classifications

• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M3/00—Conversion of DC power input into DC power output
  • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
  • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
  • H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
  • H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
  • H02M3/073—Charge pumps of the Schenkel-type
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M1/00—Details of apparatus for conversion
  • H02M1/32—Means for protecting converters other than automatic disconnection

Definitions

• the present invention relates to a charge pump circuit and an integrated circuit.
• a charge pump circuit for increasing a DC voltage circuit may include:
• DC-DC up-converter having an array of capacitors arranged to charge-pump to a higher voltage than the circuit voltage, the DC-DC up- converter having an output lead arranged to output the higher voltage, and
• DC-DC down-converter connected to the output lead, the DC-DC down-converter having an array of capacitors and diodes arranged to down- pump the higher voltage.
• the DC-DC up-converter has also diodes that prevent current sinking from the output lead through the DC-DC up-converter.
• the DC-DC down-converter can be activated only when the DC-DC up-converter is disabled.
• the above circuit is therefore not resistant to electrostatic discharge on the output lead because current sinking to a reference potential through the DC-DC up or down-converter is not always possible.
• the invention provides a charge pump circuit having an ESP (Electrostatic Discharge Protection) circuit comprising a series of l ⁇ l series- connected diodes arranged to sink current from the output lead, wherein N is an integer larger than two, each diode having its anode permanently connected to the output lead and its cathode permanently connected to a reference potential, wherein the series includes the diodes of the DC-DC down-converter.
• ESP Electrostatic Discharge Protection
• the DC-DC down-converter increases the discharging speed of the output lead by dynamically pumping charge. This is of great interest when the output lead is connected to, for example, a capacitive load.
• the above DC-DC up-converter is more resistant to electrostatic discharge on the output lead because it includes the ESP circuit.
• this charge pump circuit is decreased because diodes are common to both the DC-DC down-converter and the ESP circuit.
• the DC-DC down-converter comprises several down-pumping stages connected in series between the output lead and the reference potential, each stage having only one diode and only one capacitor, - the number of diodes of the DC-DC down-converter used in the series of the ESP circuit is strictly smaller than N,
• the DC-DC up-converter is a Dickson charge pump circuit
• the capacitors used in the DC-DC up or down-converters are metal-to-metal capacitors.
• the above embodiments of the charge pump circuit present the following advantages: - having a total diode forward bias voltage which is larger than the higher voltage reduces or cancels the leakage current that could flow from the output lead to the reference potential,
• the invention also relates to an integrated circuit having the above charge pump circuit.
• Figure 1 is a schematic diagram of a portion of an integrated circuit having a charge pump circuit
• Figure 2A and 2B are time charts of clock signals used within the charge pump circuit of Figure 1 .
• Figure 3 is a flow chart of a method of operating the charge pump circuit of Figure 1.
• Figure 1 shows an integrated circuit 2. Functions or constructions well-known to a person of ordinary skill in the art will not be described in detail hereinafter. More precisely, Figure 1 shows a portion of the integrated circuit on- chip area in which a charge pump circuit 4 is implemented to increase a DC circuit voltage V d d-
• Circuit 4 has an input lead 6 receiving voltage V d d and an output lead 8 which outputs a higher DC voltage V O u ⁇ - Lead 8 is connected to an on-chip load 10.
• load 10 is a capacitive load having a capacitor 12.
• a DC-DC up-converter 14 is directly connected between leads 6 and 8 so as to charge-pump lead 8 to the higher voltage V O u ⁇ -
• converter 14 is a Dickson charge pump converter. Such a converter is described in, for example, the following reference:
• Converter 14 has M charge pumping stages M 1 series connected between leads 6 and 8.
• Fig. 1 only shows stages M 1 , M 2 , M 3 and M m .
• Each stage M 1 has:
• Input I 1 of first stage M 1 is directly connected to lead 6.
• the other inputs I 1 are directly connected to the output of the preceding stage M 1-1 .
• the output Om of last stage M m is connected to lead 8 through a diode 20 having its cathode directly connected to lead 8.
• Clock inputs Cl 1 are connected to a clock signal generator 24 through a multiplexer 26.
• Generator 24 generates one clock signal ⁇ and one clock signal ⁇ .
• Signals ⁇ and ⁇ have opposite phases, i.e. the signal ⁇ phase is shifted by 180° from the signal ⁇ phase.
• FIGS 2A and 2B illustrate signals ⁇ and ⁇ according to time.
• Clock inputs Cl 1 of stages M 1 having an odd index i are connected to signal ⁇ .
• Clock inputs Cl 1 of stages M 1 having an even index i are connected to signal ⁇ .
• Each stage M 1 includes:
• each capacitor C 1 is smaller than, for example, 5pif. Here, capacity is equal to 1 pif.
• Each capacitor C 1 is a metal-to-metal capacitor.
• the structure of capacitor C 1 is the one disclosed in Fig.2 of the following reference:
• Each diode D 1 has a forward bias voltage V d which is, for example, equal to 0.7V.
• the forward bias voltage is the voltage drop due to the diode when the diode is conducting.
• Circuit 4 has also a DC-DC down-converter 30 which is connected between lead 8 and a reference potential V r ⁇ f .
• Reference potential V r ⁇ f is, for example, ground.
• Converter 30 has an array of capacitors and diodes arranged to down-pump voltage V O u ⁇ -
• Converter 30 has one input 32 directly connected to lead 8 and one output 34 connected to reference potential V r ⁇ f .
• Converter 30 has L down-pumping stages R 1 connected in series between input 32 and output 34. Each stage R 1 has:
• Input l'i is directly connected to input 32 and output O', is directly connected to the anode of a diode 36.
• the cathode of diode 36 is directly connected to output 34.
• the other outputs O', are connected to the input l' l+ i of the next stage R 1+1 .
• stages R 1 , R 2 , R ⁇ _-i and R L are shown in Figure 1.
• Input clock Cl' is connected to signal ⁇ if index i is odd and otherwise connected to signal ⁇ .
• Each stage R 1 has: - only one diode D', having its anode connected to input T 1 and its cathode connected to output O',, and
• Diodes D' are identical to, for example, diodes D 1 .
• capacitor C 1 has a capacity which is smaller than that of capacitor C 1 .
• capacitor C 1 has a capacity which is at least twice smaller than the capacity of capacitor C 1 .
• Output 34 is connected to reference potential V r ⁇ f through a series 40 of K_diodes E 1 .
• K_diodes E 1 For simplicity, only diodes E 1 , E 2 , E 3 , E K -- ⁇ , E ⁇ are shown in
• each diode E 1 is connected to output 34 and each cathode is connected to reference potential V r ⁇ f .
• Diodes E 1 are identical to, for example, diodes D',.
• lead 8 is directly and permanently connected to reference potential V r ⁇ f through a series 42 of N diodes, wherein N is equal to L+K+1. More precisely, series 42 of diodes includes: - the L series-connected diodes D',,
• Diodes D', and diode 36 are common to both converter 30 and the ESP circuit.
• the number N of diodes in the ESP circuit is chosen to comply with the following relation:
• -V OUT is the voltage generated by converter 14, and - Vd is the forward bias voltage of diodes D',, 26 and E 1 .
• Multiplexer 26 is able to sequentially activate converters 14 and 30. More precisely, multiplexer 26 is able to connect signal ⁇ and ⁇ alternately to clock inputs Cl 1 and clock inputs Cl',.
• multiplexer 26 has two controllable interrupters 44 and 46 for connecting and disconnecting each input clock Cl 1 from signals ⁇ and ⁇ .
• Multiplexer 26 has also two controllable interrupters 48 and 50 which are able to connect and disconnect each input clock Cl', from clock signal ⁇ and ⁇ .
• Interrupters 44, 46, 48 and 50 are designed in such a way that, when interrupters 44 and 46 are closed, interrupters 48 and 50 are open, and vice- versa. The switching of interrupters 44, 46, 48 and 50 is controlled through a control input port 52.
• circuit 4 The operation of circuit 4 will now be described with reference to Figure 3.
• step 60 controller 26 closes interrupters 44 and 46 and opens interrupters 48 and 50 to only activate converter 14 and disable converter 30.
• a charge pumping step 62 takes place.
• step 62 converter 14 increases voltage V d d to obtain voltage V O u ⁇ -
• the operation of converter 14 is well-known and will not be described in detail.
• step 64 multiplexer 26 is controlled through port 52 to open interrupters 44 and 46 and close interrupters 48 and 50. In step 64, converter 14 is therefore disabled and converter 30 is activated.
• step 66 When activated, in step 66, converter 30 operates like converter 14 to down-pump voltage V O u ⁇ - Step 66 will therefore not be described in detail.
• step 66 current flows from load 10 to reference potential V r ⁇ f through diodes D',, diode 36 and diodes E 1 .
• Activating converter 30 allows a quicker discharge of load 10 than if only diodes were used.
• step 70 voltage V O u ⁇ becomes larger than N.V d if there is an electrostatic discharge on lead 8.
• diodes D', , diode 36 and diodes E 1 conduct.
• the number L does not need to be equal to number M.
• number L is smaller than number M in order to reduce the on-chip area needed to implement circuit 4.
• the number K of diodes E 1 may be as small as zero.
• DC-DC up-converter 14 can be replaced by a DC-DC up-converter having a different structure.
• a structure similar to that disclosed in Figure 3C of WO98/20401 may be used.
• Converter 14 can also be replaced by a DC-DC up-converter having the structure disclosed in the following article:

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• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Dc-Dc Converters (AREA)

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• 2006
  • 2006-11-27 EP EP06831946A patent/EP1958321A2/de not_active Withdrawn
  • 2006-11-27 WO PCT/IB2006/054447 patent/WO2007063474A2/en not_active Ceased
  • 2006-11-27 CN CNA2006800445102A patent/CN101317320A/zh active Pending
  • 2006-11-27 JP JP2008542897A patent/JP2009517997A/ja not_active Withdrawn

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