EP1935100A2

EP1935100A2 - Rf synthesizer and rf transmitter or receiver incorporating the synthesizer

Info

Publication number: EP1935100A2
Application number: EP06786008A
Authority: EP
Inventors: Soren Peter Larsen
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 2005-09-08
Filing date: 2006-06-30
Publication date: 2008-06-25
Also published as: CN101278486A; WO2007030189A3; GB2430089B; WO2007030189A2; KR100990802B1; KR20080042181A; GB2430089A; GB0518214D0; EP1935100A4

Abstract

An RF (radio frequency) synthesizer (200) includes a VCO (voltage controlled oscillator) (220) operable to provide an output signal at a desired frequency (FVCO) and, coupled to the VCO, a frequency divider operable to receive the output signal of the VCO and to provide an output signal which is divided in frequency relative to the output signal of the VCO, wherein the synthesizer includes an output path (250, 251) which includes the frequency divider (241), whereby the synthesizer is operable to provide an output signal at an output frequency (FVCO/Nx) of the frequency divider. The synthesizer may beneficially include an integrated circuit which incorporates at least part of the VCO. Also described is an RF transmitter or receiver, e.g. for use in a base transceiver station of a mobile communications system, which incorporates the synthesizer.

Description

TITLE: RF SYNTHESIZER AND RF TRANSMITTER OR RECEIVER INCORPORATING THE SYNTHESIZER

FIELD OF THE INVENTION

The present invention relates to an RF (radio frequency) synthesizer and an RF transmitter or receiver incorporating the RF synthesizer. In particular, the invention relates to an RF synthesizer which incorporates a VCO (voltage controlled oscillator) useful in a wireless transmitter or receiver for generating a stable RF signal.

BACKGROUND OF THE INVENTION

Carrier frequency signals in RF communications transmitters are conventionally generated by a frequency synthesizer including a VCO connected in a phase locked loop (PLL). The phase locked loop, including the VCO, provides an appropriate stable output signal at a precisely defined frequency. The VCO usually employs a resonator portion which provides oscillations in a given frequency band which includes the output signal frequency, a tuning portion, e.g. employing one or more voltage controlled devices such as varactors, which provides tuning of the output frequency in accordance with an input control voltage and an amplifier or active portion.

RF synthesizers may also be used in RF receivers to provide accurate reference (local oscillator) frequency signals. In many cases, the receiver and transmitter are combined in a single transceiver unit. In the prior art, synthesizers for high performance applications, e.g. RF high power transmitters or high sensitivity receivers for use in radio base transceiver stations in mobile wireless communications systems, have employed VCOs in which the resonator portion, the tuning portion and the amplifier portion are provided as discrete components. These components are soldered together on a PCB (printed circuit board). This conventional approach has shown several disadvantages. The

VCO parts have to be acquired and handled separately prior to assembly. The VCO is costly to assemble from its constituent parts. The VCO is constructed separately from the PLL circuits and the combination of the two is time consuming and costly to assemble. Assembly of the VCO and its combination with the PLL circuits is an intricate operation which is prone to assembly errors. The VCO suffers from the problem of 'microphonics' in which mechanical vibration of the PCB causes electrical noise in the VCO by piezoelectric modulation. Furthermore, the phase noise performance of the VCO is reduced to an undesirably low level by reduction of the Q- f actor of the resonator portion.

It is known in the prior art to provide VCOs in the form of an integrated circuit. This solves the problems described above obtained with the use of discrete components. However, the problem of reduced phase noise performance described above is increased with such VCOs as a resonator of sufficient Q-factor cannot be realized using current semiconductor technology used in integrated circuit manufacture. This performance reduction is unacceptable for VCO operation frequencies of 1 GHz or less when the VCO output is intended for receiving or transmitting a carrier signal in applications such as radio base transceiver stations.

SUMMARY OF THE INVENTION

According to an embodiment of the present invention in a first aspect there is provided an RF synthesizer as defined in claim 1 of the accompanying claims.

According to an embodiment of the present invention in a second aspect there is provided an RF transmitter as defined in claim 15 of the accompanying claims.

According to an embodiment of the present invention in a second aspect there is provided an RF receiver as defined in claim 16 of the accompanying claims.

Further features of the invention are defined in the accompanying dependent claims and are disclosed in the embodiments of the invention to be described.

By the invention, a novel synthesizer is provided in which the problems of the prior art described earlier may be overcome. The novel synthesizer includes a frequency divider which divides down the output frequency provided by the VCO in an output path of the synthesizer, i.e. a path not included in the PLL. This allows a VCO to be used operating at a frequency much higher than the required output frequency of the synthesizer.

The use of the frequency divider advantageously improves the phase noise performance of the output signal produced by the synthesizer compared with that of the VCO output signal of a prior art synthesizer producing an output signal at the same frequency. This is achieved because the phase noise performance of a signal produced by a VCO can be improved by a factor of 201og_!o(N_x) by applying the frequency division, where N_x is the divisor number by which the VCO output signal frequency is divided to produce the synthesizer output signal frequency. At least part of the VCO of the novel synthesizer may beneficially be provided in the form of an integrated circuit, e.g. a semiconductor chip, which may also include at least part of the PLL circuitry. This has several benefits which include the ability to manufacture the synthesizer more easily and more cheaply and with greater production control thereby overcoming the problems of manufacturing from separate components as in the prior art described above. Such an integrated circuit form of the novel synthesizer does not have the disadvantages of unsatisfactory phase noise performance as obtained with prior art synthesizers in integrated circuit form for operation at frequencies of 1 GHz or less.

Embodiments of the present invention will now be described by way of example with reference to the accompanying drawings, in which:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block circuit illustrating a frequency synthesizer in accordance with an embodiment of the present invention.

FIG. 2 schematically depicts an integrated circuit which includes the components of the synthesizer of FIG. 1 provided in an area of the integrated circuit.

FIG. 3 is a schematic block circuit illustrating a frequency synthesizer in accordance with a further embodiment of the present invention. FIG. 4 schematically depicts an integrated circuit which includes the components of the synthesizer of FIG. 3 provided in an area of the integrated circuit. DESCRIPTION OF EMBODIMENTS OF THE INVENTION

Reference is now made to FIG. 1, which is a schematic block circuit illustration of a frequency synthesizer, generally referenced as 200, embodying the invention. The frequency synthesizer 200 includes a reference oscillator 102, e.g. a crystal oscillator or other known form of stable oscillator, a controller 108, a phase frequency detector 110, a charge pump 117, a loop filter 118, a VCO 220 and a feedback frequency divider 114. The VCO 220 includes as constituent parts a VCO tuning and resonating block or portion 212 and a VCO active block or portion 216. The reference oscillator 102 is connected to the phase frequency detector 110. The feedback frequency divider 114 is connected to the phase frequency detector 110, the controller 108 and the VCO active block 116. The charge pump 117 is connected to the phase frequency detector 110 and the loop filter 118. The loop filter 118 is connected to the VCO tuning and resonating block 212 as well as the charge pump 117. The VCO active block 216 is connected to the VCO tuning and resonating block 212 and to the feedback frequency divider 114. The loop including the VCO 220, the feedback frequency divider 114, the phase frequency detector 110, the charge pump 117 and the loop filter 118 forms a PLL (phase locked loop) 230. The reference oscillator 102 provides a reference signal to the phase frequency detector 110. The feedback frequency divider 114 receives a feedback signal, having a frequency Four, as an output from the VCO active block 216. The feedback frequency divider 114 divides the frequency of this signal by a divisor number M and provides a resultant signal, having a frequency Fouτ/M, to the phase frequency detector 110. The phase frequency detector 110 compares the respective phase and frequency of the reference and feedback signals that it receives and generates an output control signal in response. Typically, the phase frequency detector 110 operates as follows. The phase frequency detector 110 receives two input signals and can produce one of two possible (alternative) output signals. The input signals are the reference signal from the reference oscillator 102 and the (variable) feedback signal from the feedback frequency divider 114. The two possible output signals are in the form of two types of pulse, i.e. a first type of pulse and a second type of pulse, e.g. known respectively as 'Up' and 'Down' pulses, each of variable width. When the reference signal is leading the feedback signal because the frequency of the feedback signal is less than that of the reference signal, the phase frequency detector 110 produces a pulse of the first type, e.g. an 'Up' pulse, to indicate this leading by the reference signal. Conversely, when the reference signal is lagging the feedback signal because the frequency of the feedback signal is greater than that of the reference signal, the phase frequency detector 110 produces a pulse of the second type, e.g. a 'Down' pulse, to indicate this lagging. The pulse width of both the first type of pulse and the second type of pulse is proportional to the phase difference detected between the reference signal and the feedback signal, (thereby causing the phase frequency detector 110 to have a linear phase difference response). The detection of frequency difference as well as phase difference between the two input signals applied to the phase frequency detector 110 is provided by the phase frequency detector 110 for example to allow for correction of the frequency difference that occurs when starting up the PLL 230 or when switching channel frequency of the PLL 230, e.g. when the PLL 230 is used in a radio transmitter, e.g. by changing the value of the number M referred to above.

The phase frequency detector 110 includes an amplifier (not shown) which amplifies the signal provided as an output control signal (a pulse of the first or second type described above, as appropriate). The phase frequency detector 110 provides its output control signal to the charge pump 117 and the loop filter 118. If the charge pump 117 receives a pulse of the first kind from the phase frequency detector 110, it drives current into the loop filter 118. If the charge pump 117 receives a pulse of the second kind from the phase frequency detector 110, it draws current out of the loop filter 118. The loop filter 118, adjusted in this manner by the charge pump 117, converts the signal from the phase frequency detector 110 comprising a series of pulses into a resultant output control voltage V_OUT which is applied as an adjustable bias voltage to the VCO tuning and resonating block 212. Depending on the value of the output control voltage V_OUT it receives, the

VCO tuning and resonating block 212 adjusts an output frequency FQ_UT of a signal it produces to be equal to a desired value. When the PLL 230 becomes stable, the value of V_OU_T ΪS related to the values of the divisor number M and the frequency of the reference signal provided by the reference oscillator 102. The values of these parameters are therefore selected in design of the synthesizer 200 to give a desired output frequency F_OUT- The VCO active block 216 amplifies the signal of frequency F_OUT produced by the VCO tuning and resonating block 212 and provides it as an output signal having a frequency F_OUT to an output path 250 as well as to the feedback frequency divider 114 in the PLL 230.

The loop filter 118 in the synthesizer 200, as well as acting as an integrator, also filters out jitter, e.g. caused by noise of the charge pump 117, and prevents voltage overshoot.

The controller 108 in the synthesizer 200 provides selection and control of the value of the divisor number M and thereby provides adjustment of the value of V_OUT. In one form of the feedback frequency divider 114, the divider 114 may be a variable divider. In this form, the value of M may be varied by rapid switching by the controller 108 according to a pre-defined switching program between a first integer N and a second integer, e.g. N+l. This has the effect of providing an average value of M equal to a value between N and the second integer. In the case where the switching is between successive integers N and N+l, the variable feedback frequency divider is known in the art as a 'fractional-N' divider.

The controller 108 may in practice be a programmed digital signal processor. Where the synthesizer 200 is employed in an RF transceiver the controller 108 may perform other control and signal processing functions of the transceiver.

The VCO 220 operates at a much higher frequency than VCOs of the prior art (for a given output frequency). For example, if the desired output frequency is in the range 100 MHz to 1 GHz, the VCO 220 may be operable to oscillate at a frequency of at least 6 GHz and to produce an output signal having a frequency Fvco at least 6GHz, e.g. in the range 6 GHz to 60 GHz. The output signal produced by the VCO 220 is applied to the output path 250 as well as to the feedback frequency divider 114. The output path 250 has two branches 251 and 252. The branch 251 of the output path 250 includes an output frequency divider 241. The branch 252 of the output path 250 includes an output frequency divider 243. The output frequency dividers 241 and 243 operate in a known manner to divide the frequency Fvco of the output signal from the VCO 220 by fixed numbers Nl and N2 respectively. The number Nl by which the output frequency divider 241 divides the frequency Fvco is different from the number N2 by which the output frequency divider 243 divides the frequency Fvco- The numbers Nl and N2 are preferably integers. The numbers Nl and N2 depend on the value of Fvco and the value of desired output frequencies. For example, where Fvco is 10 GHz, Nl may be 12 and N2 may be 24 giving respectively output signals having frequencies respectively of 10/12 GHz and 10/24 GHz, i.e. frequencies of about 833 MHz and about 416 MHz. The signals of different frequency produced by the output frequency dividers 241 and 243 are delivered to a band selector 245 operating under the control of a controller 247. The band selector 245 provides an output signal having a desired frequency Four by selecting an output signal from either the output frequency divider 241 or from the output frequency divider 243 as appropriate. The controller 108 of the synthesizer 200 may in practice be a programmed digital signal processor. Where the synthesizer 200 is employed in an RF transceiver, the controller 108 may perform other known control and signal processing functions of the transceiver.

The controller 247 in practice may also be a programmed digital signal processor. It may be combined with the controller 108 in a single unit. Where the synthesizer 200 is employed in an RF transceiver, the controller 247 may perform other known control and signal processing functions of the transceiver.

The synthesizer 200 illustrates use of multiple output frequency dividers to produce different output frequencies. In principle, any multiple number of different output frequency dividers may be used. Alternatively, the output path 250 could be connected to a single output frequency divider.

Although the synthesizer 200 has been described above in terms of a single frequency division being applied by each of the output frequency dividers 241 and 243, the required division of the output frequency Fvco of the output signal from the VCO 220 may, as will be apparent to those skilled in the art, be carried out in two or more stages in series. For example, an overall frequency division by 24 may be obtained by successive divisions of by 8 and by 3.

By shifting the frequency of the VCO 220 to a much higher frequency than the frequency of a comparable VCO employed in a prior art synthesizer, the phase noise performance may beneficially be improved in a manner described later. Additionally, production of the VCO 220 in the form of an integrated circuit, e.g. fabricated on a semiconductor chip in a known manner, is greatly facilitated. This is because the dimensions of components needed to operate at the higher frequency are significantly reduced and also the resonator of the VCO resonator tuning and resonating block 212 may be fabricated more easily in integrated circuit form, if necessary avoiding the use of inductors by providing the resonator in the form of an R-C circuit. The integrated circuit incorporating the VCO 220 may also include most of the other components of the synthesizer 200. The reference oscillator 102 and the loop filter 118 are the only components that will normally need to be supplied separately. In other words, all components enclosed by a dashed line 260 in FIG. 1 may be fabricated together in the form of an integrated circuit. In some cases, it may even be possible to include the loop filter 118 in the integrated circuit.

FIG. 2 schematically depicts an integrated circuit 270 which includes the components indicated by dashed line 260 in FIG. 1 shown as an area 280 of the integrated circuit. The integrated circuit optionally may provide one or more other known functions as provided by components in another area 290 of the integrated circuit.

PLL oscillator circuits operating at frequencies of 10 GHz or more fabricated in integrated circuit form are already in wide use in the optical communications industry and the technology for producing such circuits can suitably be adapted to produce the synthesizer 200 using the components indicated by area 280 of the integrated circuit 270.

Another benefit provided by the frequency synthesizer 200 embodying the invention is the frequency division by the output frequency divider 241 and by the output frequency divider 243. Dividing the frequency in this way improves the phase noise performance of the synthesizer 200. In particular, the phase noise performance of the output signal at a frequency F_OUT produced by dividing by a number N_x the frequency of a signal having a frequency Fvco is enhanced by a factor 2Olog₁₀(N_x) compared with the signal of frequency Fvco- It has been found that the following examples of phase noise performance figures may be obtained for the synthesizer 200. In these examples, reference is made in each case to an 'offset'. Ideally power is only present at a single wanted frequency - the carrier. The 'offset' is unwanted power at a given frequency spacing from the wanted signal. For an output frequency of about 800 MHz, the phase noise performance which can be obtained is about -120 dBc (decibels below carrier) at 10 IcHz offset from the carrier, -130 dBc at 25 kHz offset from the carrier, -150 dBc at 500 kHz offset from the carrier and about -170 dBc at 2 MHz offset from the carrier. At an output frequency of about 400 MHz, the phase noise performance which can be obtained is about -125 dBc at 10 kHz offset from the carrier, -135 dBc at 25 kHz offset from the carrier, -150 dBc at 500 kHz offset from the carrier and about -170 dBc at 2 MHz offset from the carrier. These figures are similar to those which are obtained in the prior art using a VCO in discrete component form operating at the required output frequency.

In consequence, the frequency synthesizer 200 provides compatible phase noise performance compared with a prior art synthesizer of conventional form operating at the same frequency; yet the VCO 220 operates at a much higher frequency than such a prior art synthesizer. This allows the prior art synthesizer to be replaced with the synthesizer 200 in which the VCO 220 and other components are in integrated circuit form thereby providing the manufacturing and quality control benefits mentioned above but without significant phase noise performance degradation expected in the prior art. Preferably, the frequency of the reference signal provided by the reference oscillator 102 is at least 100 MHz, e.g. in the range 100 MHz to 200 MHz. In this case, the frequency of the feedback signal from the feedback frequency divider 114 will also be at least 100 MHz when the PLL 230 is locked. Thus, the reference frequency determines the feedback divisor number M if the VCO frequency is fixed. This in turn has influence on the loop bandwidth which may be obtained for the PLL 230. In addition, the noise floor within the loop bandwidth of the PLL 230 is to a large extent determined by the reference frequency. It is highly desirable to minimize the noise floor within the loop bandwidth to optimize the overall phase noise performance of the PLL 230. It has been found that in order to minimize the noise floor, the reference signal frequency should desirably be at least 100 MHz, e.g. from 100 MHz to 200 MHz, preferably between 150 MHz and 170 MHz, when the VCO 230 is operated at 10 GHz. This is also required to obtain a satisfactory value for the loop bandwidth of the PLL 230.

A suitable low noise oscillator for use as the reference frequency oscillator 102 in the synthesizer 200 is the product sold under the trade name Vectron VCCl- B3B-155M52 which produces an output reference frequency signal at 155 MHz.

Reference is now made to FIG. 3, which is a schematic block circuit diagram of a frequency synthesizer, generally referenced as 300, in accordance with a further embodiment of the invention. Components which have the same reference numerals in FIG. 3 as components in the synthesizer 200 of FIG. 1 have the same function as such components and operate in a similar manner. The synthesizer 300 is a modified form of the synthesizer 200. The modification employed in the synthesizer 300 is an example of a phase adjusted PLL to correct for spurious phase errors which is the subject of a copending UK patent application of even date by the present Applicant. The synthesizer 300 includes a further control loop 330 inside the phase locked loop 230. The further control loop 330 includes a phase detector 301 connected to a further loop filter 303 and a phase rotator 305 connected to the further loop filter 303. The phase rotator 305 is located in a path 307 between the VCO 220 and the output path 250 and between the VCO 220 and the feedback frequency divider 114. The phase detector 301 is connected to the feedback frequency divider 114 and to the reference oscillator 102 and receives as input signals a feedback signal from the feedback frequency divider 114 and a reference signal from the reference oscillator 102. The phase detector 301 detects a difference in phase between the feedback signal and the reference signal and provides an output signal indicating the difference in phase to the loop filter 303 which filters and integrates the output signal and provides a control input signal to the phase rotator 305. The purpose of the further control loop 330 including the phase rotator 305 is as follows. When using the feedback frequency divider 114 in the PLL 230 as a variable divider, e.g. operating as a fractional-N divider as described earlier, spurious signals can be present in the spectrum of the output signal produced by VCO 220 as a result of the switches in the value of the divisor number used in the feedback frequency division (between use of a divisor N and another integral divisor such as N+l) by the feedback frequency divider 114. Such spurious signals from variable feedback frequency dividers are known in the art. The phase detector 301 measures any phase error arising in this way in the output signal produced by the VCO 220, and a control signal indicating the phase error is provided by the loop filter 303 to the phase rotator 305. The phase rotator 305 applies a phase change to the output signal provided by the VCO 220. The amount of the phase change applied by the phase rotator 305 is determined adaptively by the control signal applied from the loop filter 303 and is thereby adjusted continuously to be suitable to equalize the detected phase error in the output signal provided by the VCO 220.

The phase rotator 305 may be an analog or digital phase rotator of known form.

Although a simple phase detector is suitable for use as the phase detector 301, a phase frequency detector, e.g. similar to that described earlier (phase frequency detector 110) with reference to FIG. 1, may be used instead. In this case, a charge pump (not shown) is also used, in the manner described for the charge pump 117 in the synthesizer 200 of FIG. 1.

The loop bandwidth of the primary loop, i.e. the phase locked loop 230, in the synthesizer 300 is selected to give maximum phase noise suppression of the output signal produced by the VCO 220. Such a bandwidth is therefore narrow, e.g. in the range 2 kHz to 5 MHz for Fvco = 10 GHz to 20 GHz. In contrast, the loop bandwidth of the secondary loop, i.e. the further control loop 330, is selected to give rapid phase error equalization and suitable system stability. The loop bandwidth of the further control loop 330 is therefore desirably much wider than that of the phase locked loop 230, e.g. is at least 10 MHz, e.g. from 10 MHz to 100 MHz, for F_Vco = 10 GHz to 20 GHz. The bandwidth of the further control loop 330 is desirably at least twice, preferably at least ten times the bandwidth of the phase locked loop 230.

As in the case of the synthesizer 200, components of the synthesizer 300 may be incorporated in an integrated circuit. The integrated circuit may include the additional components of the further control loop 330 except the loop filter 303 which, like the loop filter 118, will normally be supplied separately. In other words, all components enclosed by a dashed line 360 in FIG. 3 may be fabricated together in the form of an integrated circuit. In some cases, it may even be possible to include the loop filter 118 and/or the loop filter 303 in the integrated circuit. FIG. 4 schematically depicts an integrated circuit 370 which includes the components indicated by dashed line 360 in FIG. 3 shown as an area 380 of the integrated circuit 370. The integrated circuit 370 optionally may provide one or more other functions as provided by components in another area 390 of the integrated circuit 370. In the synthesizers 200 and 300 a reference frequency divider (not shown) may be included as an optional component if the frequency of output reference signal provided by the reference oscillator 102 requires division to a suitable scale.

The PLL 230 in the synthesizers 200 and 300 may be modified in a known manner to operate in a digital or a semi-digital form analogous to the analog form shown in FIGS. 1 and 3. For, example, in an analogous digital form the integration function carried out by the charge pump 117 and the loop filter 118 shown in FIGS. 1 and 3 is carried out by a counter (e.g. an 'Up/Down' counter) which counts the pulses it receives from the phase frequency detector 110 by incrementing for 'Up' pulses and decrementing for 'Down' pulses, each increment or decrement being proportional to the received pulse width. The output of the counter is a digital word, for example a 16 bit word, which represents the total number obtained by the incrementing and decrementing procedure for a given sampled frame of the feedback signal. The digital word produced by the counter is then fed to a digital encoder which translates the digital word to a digital control word for use in digital control of the VCO 220. In the semi-digital form the output signal produced by the loop filter 118 may for example be converted to digital form by an A/D (analog to digital) converter which produces as an output a digital signal. The digital signal so produced is fed to a digital encoder which translates the digital word to a digital control word for use in digital control of the VCO 220.

The synthesizers 200 and 300 are suitable for use in RF transceivers, e.g. to provide carrier frequency signals for transmission or to provide local oscillator signals for use in receiver processing. The synthesizers 200 and 300 are particularly suitable for use in transceivers transmitting at a high power level or receiving a high sensitivity level. An example of a high power transmitter level is an output RF power of at least 10 Watts as measured at the radiator (antenna) of the transmitter. An example of a high sensitivity receiver is a receiver having a sensitivity better than - 118 dBm at 3% static BER (Bit Error rate) for a π/4 Differential Quadrature Phase Shift Keyed signal (DQPSK modulation). Such a transceiver may be suitable for use in a base transceiver station of a mobile wireless communication system, e.g. in particular one for operation in accordance with TETRA standards.

Claims

1. An RF (radio frequency) synthesizer including a VCO (voltage controlled oscillator) operable to provide an output signal at a desired frequency and, coupled to the VCO, a frequency divider operable to receive the output signal of the VCO and to provide an output signal which is divided in frequency relative to the output signal of the VCO, wherein the synthesizer includes an output path which includes the frequency divider, wherein the synthesizer is operable to provide an output signal at an output frequency of the frequency divider.

2. An RF synthesizer according to claim 1 wherein the synthesizer includes a phase locked loop including (i) the VCO; (ii) a further frequency divider operable to receive the output signal of the VCO and to provide a feedback signal which is divided in frequency relative to the output signal of the VCO; and (iii) a phase frequency detector operable to receive the feedback signal produced by the further frequency divider and to compare a phase and frequency of the feedback signal with the phase and frequency of a reference signal.

3. An RF synthesizer according to claim 2 wherein the phase frequency detector is operable using a reference frequency in the range of from 100 MHz to 200 MHz.

4. An RF synthesizer according to any one of claims 1 to 3 wherein the output path of the synthesizer includes a plurality of different frequency dividers to provide output signals at different frequencies.

5. An RF synthesizer according to any one preceding claim wherein the frequency divider or at least one of the frequency dividers in the output path includes at least two division stages in series.

6. An RF synthesizer according to any one of the preceding claims including an integrated circuit which includes at least part of the VCO.

7. An RF synthesizer according to claim 6 wherein the integrated circuit also includes at least part of a phase locked loop.

8. An RF synthesizer according to claim 6 or claim 7 wherein the integrated circuit includes at least one frequency divider.

9. An RF synthesizer according to any one of claims 2 to 8 including a further control loop inside the phase locked loop and a phase rotator connected to an output of the VCO and operable to equalize a phase error of an output signal produced by the VCO, the further control loop being connected to the phase rotator to provide a control signal to the phase rotator.

10. An RF synthesizer according to claim 9 wherein the further control loop has a bandwidth which is greater than the bandwidth of the phase locked loop.

11. An RF synthesizer according to claim 10 wherein the bandwidth of the phase locked loop is in the range 2 kHz to 5 MHz and the bandwidth of the further control loop is not less than 10 MHz.

12. An RF synthesizer according to any one of the preceding claims wherein the VCO is operable to oscillate at a frequency of at least 6 GHz.

13. An RF synthesizer according to claim 12 which is operable to produce an output signal at one or more frequencies in the range 100 MHz to 1 GHz.

14. An RF synthesizer according to any one of the preceding claims including an integrated circuit which includes at least part of the VCO and the VCO has a phase noise performance better than -150 dBc for an offset of 500 kHz.

15. An RF transmitter for wireless communications including a RF synthesizer according to any one of the preceding claims.

16. An RF receiver for wireless communications including a RF synthesizer according to any one of the preceding claims 1 to 14.

17. An RF transmitter according to claim 15 or an RF receiver according to claim 16 adapted for use in a base transceiver station for mobile wireless communications.

18. An RF synthesizer according to any one of claims 1 to 14 and substantially as described herein with reference to any one or more of FIGS. 2 to 5 of the accompanying drawings.