EP1934774A1 - Architecture de machine modifiee a mise a jour partielle de la memoire - Google Patents

Architecture de machine modifiee a mise a jour partielle de la memoire

Info

Publication number
EP1934774A1
EP1934774A1 EP06790317A EP06790317A EP1934774A1 EP 1934774 A1 EP1934774 A1 EP 1934774A1 EP 06790317 A EP06790317 A EP 06790317A EP 06790317 A EP06790317 A EP 06790317A EP 1934774 A1 EP1934774 A1 EP 1934774A1
Authority
EP
European Patent Office
Prior art keywords
group
memory
computers
machine
computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06790317A
Other languages
German (de)
English (en)
Other versions
EP1934774A4 (fr
Inventor
John Matthew Holt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Waratek Pty Ltd
Original Assignee
Waratek Pty Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from AU2005905582A external-priority patent/AU2005905582A0/en
Application filed by Waratek Pty Ltd filed Critical Waratek Pty Ltd
Publication of EP1934774A1 publication Critical patent/EP1934774A1/fr
Publication of EP1934774A4 publication Critical patent/EP1934774A4/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/01—Protocols
    • H04L67/10—Protocols in which an application is distributed across nodes in the network
    • H04L67/1095—Replication or mirroring of data, e.g. scheduling or transport for data synchronisation between network nodes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes

Definitions

  • the present invention relates to computing and, in particular, to the simultaneous operation of a plurality of computers interconnected via a communications network.
  • the abovementioned patent specifications disclose that at least one application program written to be operated on only a single computer can be simultaneously operated on a number of computers each with independent local memory.
  • the memory locations required for the operation of that program are replicated in the independent local memory of each computer.
  • each computer has a local memory the contents of which are substantially identical to the local memory of each other computer and are updated to remain so. Since all application programs, in general, read data much more frequently than they cause new data to be written, the abovementioned arrangement enables very substantial advantages in computing speed to be achieved.
  • the stratagem enables two or more commodity computers intercomiected by a commodity communications network to be operated simultaneously running under the application program written to be executed on only a single computer.
  • the genesis of the present invention is a desire to increase of the speed of operation of the multiple computer system by reducing the volume of data which requires to be updated.
  • a multiple computer system in which different portions of at least one application program written to execute on only a single computer execute substantially simultaneously each on a corresponding one of a plurality of computers, each of which has an independent local memory and all of which are interconnected by a communications network, wherein memory locations present in said local memories are categorized into two groups, a first group of memory locations each of which is replicated on each said computer, and a second group of memory locations each of which is present only in the specific one of said computers in which each said second group memory location is physically present, said system comprising memory updating means to update via said communications network any changes made to a memory location of said first group in one computer to all other corresponding memory locations of said other computers, and promotion means to promote from said second group to said first group any memory location of said second group which, as a result of execution of said application program, is now referred top by a memory location of said first group.
  • a single computer adapted to co-operate with at least one other computer in order to carry out the above method or form the above computer system.
  • a computer program product comprising a set of program instructions stored in a storage medium and operable to permit a plurality of computers to carry out the above defined method.
  • a plurality of computers interconnected via a communications network and operable to ensure carrying out of the above described method.
  • Fig. IA is a schematic illustration of a prior art computer arranged to operate JAVA code and thereby constitute a single JAVA virtual machine
  • Fig. IB is a drawing similar to Fig. IA but illustrating the initial loading of code
  • Fig. 1C illustrates the interconnection of a multiplicity of computers each being a JAVA virtual machine to form a multiple computer system
  • Fig. 2 schematically illustrates "n" application running computers to which at least one additional server machine X is connected as a server
  • Fig. 3 is a schematic map of the memory locations in all the multiple machines showing memory locations including classes and objects,
  • Fig. 4 is a table showing the various memory locations of Fig. 3 and their ability to be reached,
  • Fig. 5 is a map similar to Fig. 3 and showing the consequence of memory location X pointing to memory location A,
  • Fig. 6 is the reachability table corresponding to Fig. 5,
  • Fig. 7 is a map similar to Fig. 3 and showing memory location A pointing to new memory location K,
  • Fig. 8 is the reachability table corresponding to Fig. 7,
  • Fig. 9 is a map similar to Fig. 7 but showing the consequence of memory location X pointing to memory location A,
  • Fig. 10 is the reachability table corresponding to Fig. 9, Figs. 11-14 illustrate multiple reachability tables respectively corresponding to the individual reachability tables of Figs. 4, 6, 8 and 10,
  • Fig. 15 illustrates a further memory change
  • Figs. 16 and 17 respectively illustrate the single and multiple reachability tables corresponding to the memory changes of Fig. 15, Fig. 18 illustrates another memory change
  • Figs. 19 and 20 respectively illustrate the single and multiple reachability tables corresponding to the memory changes of Fig. 19,
  • Fig. 21 illustrates a still further memory change
  • Figs. 22 and 23 respectively illustrate the single and multiple reachability tables corresponding to the memory changes of Fig. 21,
  • Fig. 24 illustrates yet another memory change
  • Figs. 25 and 26 respectively illustrate the single and multiple reachability tables corresponding to the memory changes of Fig. 24.
  • MICROSOFT.NET platform and architecture Visual Basic, Visual C, and Visual C++, and Visual C#
  • FORTRAN C, C++, COBOL, BASIC and the like.
  • the code and data and virtual machine configuration or arrangement of Fig IA takes the form of the application code 50 written in the JAVA language and executing within the JAVA virtual machine 61.
  • the intended language of the application is the language JAVA
  • a JAVA virtual machine is used which is able to operate code in JAVA irrespective of the machine manufacturer and internal details of the computer or machine.
  • Fig. IA This conventional art arrangement of Fig. IA is modified in accordance with embodiments of the present invention by the provision of an additional facility which is conveniently termed a “distributed run time” or a “distributed run time system” DRT 71 and as seen in Fig. IB.
  • the application code 50 is loaded onto the Java Virtual Machine(s) Ml, M2,...Mn in cooperation with the distributed runtime system 71, through the loading procedure indicated by arrow 75 or 75 A or 75B.
  • distributed runtime and the “distributed run time system” are essentially synonymous, and by means of illustration but not limitation are generally understood to include library code and processes which support software written in a particular language running on a particular platform. Additionally, a distributed runtime system may also include library code and processes which support software written in a particular language running within a particular distributed computing environment.
  • a runtime system typically deals with the details of the interface between the program and the operating system such as system calls, program start-up and termination, and memory management.
  • a conventional Distributed Computing Environment (DCE) (that does not provide the capabilities of the inventive distributed run time or distributed run time system 71 used in the preferred embodiments of the present invention) is available from the Open Software Foundation.
  • This Distributed Computing Environment (DCE) performs a form of computer-to-computer communication for software running on the machines, but among its many limitations, it is not able to implement the desired modification or communication operations.
  • the preferred DRT 71 coordinates the particular communications between the plurality of machines Ml, M2,...Mn.
  • Fig. 1C shows in modified form the arrangement of the JAVA virtual machines, each as illustrated in Fig. IB.
  • each machine Ml , M2...Mn the communications between each machine Ml , M2...Mn are as indicated by arrows 83, and although physically routed through the machine hardware, are advantageously controlled by the individual DRT's 71/1...71/n within each machine.
  • this may be conceptionalised as the DRT's 71/1, ...71/n communicating with each other via the network or other communications link 53 rather than the machines Ml , M2...Mn communicating directly themselves or with each other.
  • Contemplated and included are either this direct communication between machines Ml, M2...Mn or DRT's 71/1, 71/2...71/n or a combination of such communications.
  • the preferred DRT 71 provides communication that is transport, protocol, and link independent.
  • the one common application program or application code 50 and its executable version (with likely modification) is simultaneously or concurrently executing across the plurality of computers or machines Ml , M2...Mn.
  • the application program 50 is written to execute on a single machine or computer (or to operate on the multiple computer system of the abovementioned patent applications which emulate single computer operation).
  • the modified structure is to replicate an identical memory structure and contents on each of the individual machines.
  • common application program is to be understood to mean an application program or application program code written to operate on a single machine, and loaded and/or executed in whole or in part on each one of the plurality of computers or machines Ml, M2...Mn, or optionally on each one of some subset of the plurality of computers or machines M 1 , M2... Mn.
  • application code 50 This is either a single copy or a plurality of identical copies each individually modified to generate a modified copy or version of the application program or program code. Each copy or instance is then prepared for execution on the corresponding machine. At the point after they are modified they are common in the sense that they perform similar operations and operate consistently and coherently with each other.
  • a plurality of computers, machines, information appliances, or the like implementing embodiments of the invention may optionally be connected to or coupled with other computers, machines, information appliances, or the like that do not implement embodiments of the invention.
  • the same application program 50 (such as for example a parallel merge sort, or a computational fluid dynamics application or a data mining application) is run on each machine, but the executable code of that application program is modified on each machine as necessary such that each executing instance (copy or replica) on each machine coordinates its local operations on that particular machine with the operations of the respective instances (or copies or replicas) on the other machines such that they function together in a consistent, coherent and coordinated manner and give the appearance of being one global instance of the application (i.e. a "meta- application").
  • the copies or replicas of the same or substantially the same application codes are each loaded onto a corresponding one of the interoperating and connected machines or computers.
  • the application code 50 may be modified before loading, or during the loading process, or with some disadvantages after the loading process, to provide a customization or modification of the application code on each machine.
  • Some dissimilarity between the programs or application codes on the different machines may be permitted so long as the other requirements for interoperability, consistency, and coherency as described herein can be maintained.
  • each of the machines Ml, M2...Mn and thus all of the machines Ml,
  • M2...Mn have the same or substantially the same application code 50, usually with a modification that may be machine specific.
  • each application code 50 is modified by a corresponding modifier 51 according to the same rules (or substantially the same rules since minor optimizing changes are permitted within each modifier 51/1, 51/2...51 /n).
  • Each of the machines Ml , M2...Mn operates with the same (or substantially the same or similar) modifier 51 (in some embodiments implemented as a distributed run time or DRT71 and in other embodiments implemented as an adjunct to the application code and data 50, and also able to be implemented within the JAVA virtual machine itself).
  • all of the machines Ml, M2...Mn have the same (or substantially the same or similar) modifier 51 for each modification required.
  • a different modification for example, may be required for memory management and replication, for initialization, for fmalization, and/or for synchronization (though not all of these modification types may be required for all embodiments).
  • the modifier 51 may be implemented as a component of or within the distributed run time 71, and therefore the DRT 71 may implement the functions and operations of the modifier 51.
  • the function and operation of the modifier 51 may be implemented outside of the structure, software, firmware, or other means used to implement the DRT 71 such as within the code and data 50, or within the JAVA virtual machine itself.
  • both the modifier 51 and DRT 71 are implemented or written in a single piece of computer program code that provides the functions of the DRT and modifier. In this case the modifier function and structure is, in practice, subsumed into the DRT.
  • the modifier function and structure is responsible for modifying the executable code of the application code program
  • the distributed run time function and structure is responsible for implementing communications between and among the computers or machines.
  • the communications functionality in one embodiment is implemented via an intermediary protocol layer within the computer program code of the DRT on each machine.
  • the DRT can, for example, implement a communications stack in the JAVA language and use the Transmission Control Protocol/Internet Protocol (TCP/IP) to provide for communications or talking between the machines.
  • TCP/IP Transmission Control Protocol/Internet Protocol
  • a plurality of individual computers or machines Ml, M2...Mn are provided, each of which are interconnected via a communications network 53 or other communications link.
  • Each individual computer or machine is provided with a corresponding modifier 51.
  • Each individual computer is also provided with a communications port which connects to the communications network.
  • the communications network 53 or path can be any electronic signalling, data, or digital communications network or path and is preferably a slow speed, and thus low cost, communications path, such as a network connection over the Internet or any common networking configurations including ETHERNET or INFINIBAND and extensions and improvements, thereto.
  • the computers are provided with one or more known communications ports (such as CISCO Power Connect 5224 Switches) which connect with the communications network 53.
  • Ml, M2, ..., Mn has, say, an internal or local memory capability of 10MB, then the total memory available to the application code 50 in its entirety is not, as one might expect, the number of machines (n) times 10MB. Nor is it the additive combination of the internal memory capability of all n machines. Instead it is either 10MB, or some number greater than 10MB but less than n x 10MB.
  • the size of the smallest memory of any of the machines may be used as the maximum memory capacity of the machines when such memory (or a portion thereof) is to be treated as 'common' memory (i.e. similar equivalent memory on each of the machines Ml ...Mn) or otherwise used to execute the common application code.
  • each machine Ml, M2...Mn has a private (i.e. 'non-common') internal memory capability.
  • the private internal memory capability of the machines Ml, M2, ..., Mn are normally approximately equal but need not be.
  • each machine or computer is preferably selected to have an identical internal memory capability, but this need not be so.
  • the independent local memory of each machine represents only that part of the machine's total memory which is allocated to that portion of the application program running on that machine. Thus, other memory will be occupied by the machine's operating system and other computational tasks unrelated to the application program 50.
  • Non-commercial operation of a prototype multiple computer system indicates that not every machine or computer in the system utilises or needs to refer to (e.g. have a local replica of) every possible memory location.
  • some or all of the plurality of individual computers or machines can be contained within a single housing or chassis (such as so-called “blade servers” manufactured by Hewlett-Packard Development Company, Intel Corporation, IBM Corporation and others) or the multiple processors (eg symmetric multiple processors or SMPs) or multiple core processors (eg dual core processors and chip multithreading processors) manufactured by Intel, AMD, or others, or implemented on a single printed circuit board or even within a single chip or chip set.
  • blade servers manufactured by Hewlett-Packard Development Company, Intel Corporation, IBM Corporation and others
  • the multiple processors eg symmetric multiple processors or SMPs
  • multiple core processors eg dual core processors and chip multithreading processors
  • computers or machines having multiple cores, multiple CPU's or other processing logic.
  • the generalized platform, and/or virtual machine and/or machine and/or runtime system is able to operate application code 50 in the language(s) (possibly including for example, but not limited to any one or more of source-code languages, intermediate-code languages, object-code languages, machine-code languages, and any other code languages) of that platform and/or virtual machine and/or machine and/or runtime system environment, and utilize the platform, and/or virtual machine and/or machine and/or runtime system and/or language architecture irrespective of the machine or processor manufacturer and the internal details of the machine.
  • the platform and/or runtime system can include virtual machine and non-virtual machine software and/or firmware architectures, as well as hardware and direct hardware coded applications and implementations.
  • computers and/or computing machines and/or information appliances or processing systems are still applicable.
  • computers and/or computing machines that do not utilize either classes and/or objects include for example, the x86 computer architecture manufactured by Intel Corporation and others, the SPARC computer architecture manufactured by Sun Microsystems, Inc and others, the Power PC computer architecture manufactured by International Business Machines Corporation and others, and the personal computer products made by Apple Computer, Inc., and others.
  • primitive data types such as integer data types, floating point data types, long data types, double data types, string data types, character data types and Boolean data types
  • structured data types such as arrays and records
  • derived types or other code or data structures of procedural languages or other languages and environments such as functions, pointers, components, modules, structures, reference and unions.
  • This analysis or scrutiny of the application code 50 can take place either prior to loading the application program code 50, or during the application program code 50 loading procedure, or even after the application program code 50 loading procedure (or some combination of these). It may be likened to an instrumentation, program transformation, translation, or compilation procedure in that the application code can be instrumented with additional instructions, and/or otherwise modified by meaning- preserving program manipulations, and/or optionally translated from an input code language to a different code language (such as for example from source-code language or intermediate-code language to object-code language or machine-code language).
  • compilation normally or conventionally involves a change in code or language, for example, from source code to object code or from one language to another language.
  • compilation and its grammatical equivalents
  • the term "compilation” is not so restricted and can also include or embrace modifications within the same code or language.
  • the compilation and its equivalents are understood to encompass both ordinary compilation (such as for example by way of illustration but not limitation, from source-code to object code), and compilation from source-code to source-code, as well as compilation from object-code to object code, and any altered combinations therein. It is also inclusive of so-called “intermediary-code languages” which are a form of "pseudo object-code”.
  • the analysis or scrutiny of the application code 50 takes place during the loading of the application program code such as by the operating system reading the application code 50 from the hard disk or other storage device, medium or source and copying it into memory and preparing to begin execution of the application program code.
  • the analysis or scrutiny may take place during the class loading procedure of the java.lang.ClassLoader.loadClass method (e.g. "java.lang.ClassLoader.loadClassQ").
  • 50 may take place even after the application program code loading procedure, such as after the operating system has loaded the application code into memory, or optionally even after execution of the relevant corresponding portion of the application program code has started, such as for example after the JAVA virtual machine has loaded the application code into the virtual machine via the "java.lang.ClassLoader.loadClass()" method and optionally commenced execution.
  • One such technique is to make the modification(s) to the application code, without a preceding or consequential change of the language of the application code.
  • Another such technique is to convert the original code (for example, JAVA language source-code) into an intermediate representation (or intermediate-code language, or pseudo code), such as JAVA byte code. Once this conversion takes place the modification is made to the byte code and then the conversion may be reversed. This gives the desired result of modified JAVA code.
  • a further possible technique is to convert the application program to machine code, either directly from source-code or via the abovementioned intermediate language or through some other intermediate means. Then the machine code is modified before being loaded and executed.
  • a still further such technique is to convert the original code to an intermediate representation, which is thus modified and subsequently converted into machine code.
  • the present invention encompasses all such modification routes and also a combination of two, three or even more, of such routes.
  • the DRT 71 or other code modifying means is responsible for creating or replicating a memory structure and contents on each of the individual machines Ml, M2...Mn that permits the plurality of machines to interoperate.
  • this replicated memory structure will be identical. Whilst in other embodiments this memory structure will have portions that are identical and other portions that are not. In still other embodiments the memory structures are different only in format or storage conventions such as Big Endian or Little Endian formats or conventions.
  • Such local memory read and write processing operation can typically be satisfied within 10 2 - 10 3 cycles of the central processing unit. Thus, in practice there is substantially less waiting for memory accesses which involves and/or writes. Also, the local memory of each machine is not able to be accessed by any other machine and can therefore be said to be independent.
  • the invention is transport, network, and communications path independent, and does not depend on how the communication between machines or DRTs takes place. In one embodiment, even electronic mail (email) exchanges between machines or DRTs may suffice for the communications.
  • Fig. 2 there are a number of machines Ml , M2, .... Mn, "n” being an integer greater than or equal to two, on which the application program 50 of Fig. 1 is being run substantially simultaneously.
  • These machines are allocated a number 1, 2, 3, ... etc. in a hierarchical order. This order is normally looped or closed so that whilst machines 2 and 3 are hierarchically adjacent, so too are machines "n" and 1.
  • the further machine X can be a low value machine, and much less expensive than the other machines which can have desirable attributes such as processor speed.
  • an additional low value machine (X+ 1) is preferably available to provide redundancy in case machine X should fail.
  • server machines X and X+l are provided, they are preferably, for reasons of simplicity, operated as dual machines in a cluster configuration.
  • Machines X and X+l could be operated as a multiple computer system in accordance with the present invention, if desired. However, this would result in generally undesirable complexity. If the machine X is not provided then its functions, such as housekeeping functions, are provided by one, or some, or all of the other machines.
  • the memory locations which potentially require updating are divided into at least two categories.
  • the first category consists of those memory locations which are accessible by any two or more of the multiple machines and thus should be continuously updated.
  • the second category consists of those memory locations which are accessible only by the local machine where the memory location is physically located. For these memory locations it is undesirable to, firstly, replicate the contents of that memory location on all the other machines, and secondly, to continue to update the contents of the replicated memory locations each time that the original local memory contents change.
  • Memory locations which fall into the two categories are easily able to be distinguished by whether or not there is a pointer pointing to the memory location concerned. There are several mechanisms, or modes, whereby this categorisation and data transfer can take place.
  • each of the multiple machines M 1 , M2, Mn (other than any server machine X if present) has its memory locations schematically illustrated.
  • the contents of the memory location X are the same for each of the machines and each machine is able to both read from, and write to, memory location X. For this reason, the boundary of memory location X is indicated with a double line.
  • the server machine X of Fig. 2 it is convenient for the server machine X of Fig. 2, to maintain a table listing each memory location and the machines which are able to access each memory location in the table.
  • a table is said to be a reachability table and is illustrated in Fig. 4.
  • the first row in the table of Fig. 4 deals with memory location A which is only able to be accessed by machine Mn.
  • the second row in the table of Fig. 4 deals with memory location B which is only able to be accessed by machine Ml.
  • object D is only able to be accessed by machine M2
  • object E is only able to be accessed by machine Mn.
  • the class X is able to be accessed by all of the machines Ml, M2 and Mn.
  • class Xn is said to point to object A.
  • the change in status of object A means that it is now able to be accessed or referenced by all the other machines. For this reason in Fig. 5 it is named object An, is bounded by double lines, and is reproduced in each of the other machines as object Al, A2, etc. Furthermore, an arrow points from each corresponding class Xl, X2, etc to the corresponding referred object Al, A2, etc.
  • the server machine X of Fig. 2 uses the amended reachability table of Fig. 6 to ensure that the contents of object A, if amended by one machine, are transmitted via the network 3 to all the other machines.
  • Figs. 7 and 8 illustrate a further modification.
  • object A in machine Mn as a result of the processing carried out by machine Mn, now points to a new object K.
  • Fig. 8 This new row illustrates that object K is only able to be accessed by machine Mn.
  • Xn now points to object An, as before object A is replicated in each of the other machines.
  • object An itself points to object K, it is necessary for each of the objects K to be replicated in each of the other machines. This gives rise to objects Kl, K2, Kn.
  • each of these objects is accessible by all machines and consequently these objects are indicated by double lines in Fig. 9.
  • the corresponding changes to the reachability table are indicated in Fig. 10 where an object K is now indicated as being accessible by all machines.
  • the reachability data enables structures, assets or resources (ie memory locations) to be divided into two categories or classes.
  • the first category consists of those locations which are able to be accessed by all machines. It is necessary that write actions carried out in respect of such memory locations be distributed to all machines so that all corresponding memory locations have the same content (except for delays due to transmission of updating data).
  • write actions to these memory locations need not be distributed to all the other machines, nor need there be corresponding memory locations on the other machines. As a consequence of this categorisation, a substantial volume of data is not required to be transmitted from one machine to the others and so the volume of traffic on the network 53 is substantially reduced.
  • a single reachability table is provided which is located in, and maintained by, the server machine X.
  • the computer system it is also possible for the computer system to be operated without a server machine X in which case it is desirable for each machine to operate its own reachability table.
  • Figs. 11-14 illustrate individual reachability tables for the individual machines in the circumstances corresponding to Figs. 4,6,8 and 10 respectively.
  • the table for machine Ml has a row for class X and a row for object B.
  • the table for machine M2 has a row for class X and a row for object D.
  • the table for machine Mn has three rows, one for class X, and one for each of objects A and E.
  • Machine Mn can determine that object A requires replication across the other machines by consulting the table entry for class X on machine Mn. In the situation illustrated, machine Mn makes a positive determination for replication by comparing the table entries for object A and class X. If the table entry for object A includes all machines in the table entry for class X, then machine Mn can correctly determine that object A does not need to be further replicated on any other machines. Additionally, no table entries need to be added to, or updated on, other machines.
  • machine Mn updates the table entry for object A to include the set of machines listed in the table entry for class X, and additionally instructs all machines listed in the new table entry for object A to update their local tables for object A with the set of machines listed in the new table entry for object A on machine Mn.
  • machine Mn instructs those machines (ie machines Ml and M2) to add a local table entry for object A and create local replicas in memory of object A and associated references to class X.
  • machine Mn instructs all machines listed in the table entry for objects A and K to update their local tables, and further instructs all machines not originally present in the table entries of objects A and K respectively to create local replicas of objects A and K.
  • the resulting tables for the individual machines are illustrated in Fig. 14.
  • FIG. 15 A further example is illustrated in Fig. 15.
  • an object designated Al and A2 is shared on machines Ml and M2 but is not present on machine Mn.
  • machine M2 during processing of the applications program assigns a reference of object D to object A.
  • the DRT 71/2 examines the table entries for objects D and A on machine M2. This interrogation of the table determines that the table entry for object D does not include all machines in the set of machines listed in the table entry for object A.
  • the table entry for object D on machine M2 is updated to include the machines of the table entry for object A not already present in the table entry for object D, which in this instance is the additional machine Ml.
  • machine M2 instructs machine Ml to create a table entry for object D consisting of the machines listed in the now updated table entry for object D on machine M2, and create a local replica of object D.
  • the resultant changes for a single reachability table, and for multiple reachability tables, are illustrated in Figs. 19 and 20 respectively.
  • FIG. 21 A further example is illustrated in Fig. 21 in which the addition of a reference to object A assigned to class X is executed by machine Ml.
  • the tables for class X and object A are consulted to determine if object A is changing its reachability state. If the table entries for object A include all machines in the table entry for class X, then no additional action is taken. If, however, as is the case in Fig. 21 class X includes machines in its table entry not included in the table entry for object A, then a reachability change is taking place. In accordance with this change, machine Ml updates the entry for class X. Furthermore, machine Ml instructs all other machines to add and/or update their table entry for object A to be the same as the now updated table entry for object A on machine Ml.
  • any machine which was not already present in the table entry for object A is instructed to add that table entry for object A and create a replica in local memory of object A (which in this instance it is only required in machine Mn).
  • machine Ml also knows that object A in turn references object D, and so object D has to inherit the reachability change of object A. Consequently, the table entry for object D is updated to include all machines listed in the now updated table entry of object A.
  • machine Ml also instructs all machines not previously included in the table entry of object D (which in this instance is only machine Mn), to add a table entry for object D with a value equal to the now updated table entry value on machine Ml, and create a replica in local memory of object D. Furthermore, machine Ml instructs all other machines (which in this instance is only machine M2) to update the table entry for object D with the new table entry value updated on machine Ml .
  • the single reachability table and multiple reachability tables which reflect these changes are illustrated in Figs. 22 and 23 respectively.
  • Fig. 24 the position illustrated in Fig. 18 is modified by class X of machine Ml being assigned a reference to object D.
  • the reachability tables of object D and class X are examined by the DRT 71/1 for the possibility of a reachability change having occurred. Consequently, the table entries for object D and class X are compared and if the table entry for object D includes all machines listed in the table entry of class X, then no additional action is required to be taken. Alternatively, if the table entry for object D does not include all machines listed in the table entry for class X then a reachability change has taken place and consequential action is required.
  • machine Ml determines that object D has undergone a reachability change. Consequently, machine Ml firstly updates its table entry for object D to include all machines in the table entry for class X. For each new machine not previously in the set of machines of the table entry for object D, machine Ml instructs each such machine to add a local table entry for object D equal to the now updated machine entry for object D on machine Ml, and create a replica in local memory of object D. For each other machine, machine Ml also instructs the other machine to update its table entry for object D to be equal to the table entry for object D in machine Ml.
  • the single reachability table and multiple reachability tables which reflect these changes are respectively illustrated in Figs. 25 and 26.
  • the unmodified application code may either be replaced with the modified application code in whole, corresponding to the modifications being performed, or alternatively, the unmodified application code may be replaced in part or incrementally as the modifications are performed incrementally on the executing unmodified application code. Regardless of which such modification routes are used, the modifications subsequent to being performed execute in place of the unmodified application code.
  • a global identifier is as a form of 'meta-name' or 'meta-identity' for all the similar equivalent local objects (or classes, or assets or resources or the like) on each one of the plurality of machines Ml, M2...Mn.
  • a global name corresponding to the plurality of similar equivalent objects on each machine (e.g. "globalname7787"), and with the understanding that each machine relates the global name to a specific local name or object (e.g.
  • each machine may, and generally will, store memory values or contents at different memory locations according to its own internal processes.
  • the table, or list, or other data structure in each of the DRTs will have, in general, different local memory locations corresponding to a single memory name or identity, but each global "memory name" or identity will have the same "memory value or content" stored in the different local memory locations. So for each global name there will be a family of corresponding independent local memory locations with one family member in each of the computers. Although the local memory name may differ, the asset, object, location etc has essentially the same content or value. So the family is coherent.
  • tablette or “tabulation” as used herein is intended to embrace any list or organised data structure of whatever format and within which data can be stored and read out in an ordered fashion.
  • memory locations include, for example, both fields and array types.
  • the above description deals with fields and the changes required for array types are essentially the same mutatis mutandis.
  • the present invention is equally applicable to similar programming languages (including procedural, declarative and object orientated languages) to JAVA including Microsoft.NET platform and architecture (Visual Basic, Visual C/C 1"1" , and C#) FORTRAN, 0/C 1+ , COBOL, BASIC etc.
  • object and class used herein are derived from the JAVA environment and are intended to embrace similar terms derived from different environments such as dynamically linked libraries (DLL), or object code packages, or function unit or memory locations.
  • DLL dynamically linked libraries
  • any one or each of these various means may be implemented by computer program code statements or instructions (possibly including by a plurality of computer program code statements or instructions) that execute within computer logic circuits, processors, ASICs, logic or electronic circuit hardware, microprocessors, microcontrollers or other logic to modify the operation of such logic or circuits to accomplish the recited operation or function.
  • any one or each of these various means may be implemented in firmware and in other embodiments such may be implemented in hardware.
  • any one or each of these various means may be implemented by a combination of computer program software, firmware, and/or hardware.
  • any and each of the abovedescribed methods, procedures, and/or routines may advantageously be implemented as a computer program and/or computer program product stored on any tangible media or existing in electronic, signal, or digital form.
  • Such computer program or computer program products comprising instructions separately and/or organized as modules, programs, subroutines, or in any other way for execution in processing logic such as in a processor or microprocessor of a computer, computing machine, or information appliance; the computer program or computer program products modifying the operation of the computer in which it executes or on a computer coupled with, connected to, or otherwise in signal communications with the computer on which the computer program or computer program product is present or executing.
  • Such a computer program or computer program product modifies the operation and architectural structure of the computer, computing machine, and/or information appliance to alter the technical operation of the computer and realize the technical effects described herein.
  • the invention may therefore include a computer program product comprising a set of program instructions stored in a storage medium or existing electronically in any form and operable to permit a plurality of computers to carry out any of the methods, procedures, routines, or the like as described herein including in any of the claims.
  • the invention includes (but is not limited to) a plurality of computers, or a single computer adapted to interact with a plurality of computers, interconnected via a communication network or other communications link or path and each operable to substantially simultaneously or concurrently execute the same or a different portion of an application code written to operate on only a single computer on a corresponding different one of computers.
  • the computers are programmed to carry out any of the methods, procedures, or routines described in the specification or set forth in any of the claims, on being loaded with a computer program product or upon subsequent instruction.
  • the invention also includes within its scope a single computer arranged to co-operate with like, or substantially similar, computers to form a multiple computer system
  • a method of selecting independent memory locations to be substantially simultaneously updated in a multiple computer environment in which different portions of at least one application program written to execute on only a single computer are executed substantially simultaneously each on a corresponding different one of the multiple computers comprising the steps of: (i) selecting a first group of memory locations each of which is replicated on each the computer,
  • the method includes the further step of:
  • the method includes the further step of:
  • the method includes the further step of:
  • the method includes the further step of: (x) maintaining multiple the tables one in each of the multiple computers.
  • the memory locations includes an asset, structure or resource.
  • a multiple computer system in which different portions of at least one application program written to execute on only a single computer execute substantially simultaneously each on a corresponding different one of a plurality of computers, each of which has an independent local memory and all of which are interconnected by a communications network, wherein memory locations present in the local memories are categorized into two groups, a first group of memory locations each of which is replicated on each the computer, and a second group of memory locations each of which is present only in the specific one of the computers in which each the second group memory location is physically present, the system comprising memory updating means to update via the communications network any changes made to a memory location of the first group in one computer to all other corresponding memory locations of the other computers, and promotion means to promote from the second group to the first group any memory location of the second group which, as a result of execution of the application program, is now referred top by a memory location of the first group.
  • the promotion means includes an inheritance means operable to promote from the second group of memory locations any memory location or locations to which a promoted second group memory location itself refers.
  • the promotion means includes a table listing the first group of memory locations.
  • the system has one table for all the plurality of application program executing computers present in a further server computer.
  • the system has a plurality of tables, one in each of the plurality of application program executing computers.
  • the memory locations include an asset, structure or resource.
  • a computer program product comprising a set of program instructions stored in a storage medium and operable to permit a plurality of computers to carry out any of the above method(s).
  • a plurality of computers interconnected via a communications network and operable to ensure carrying out of any of the above method(s).
  • a single computer adapted to co-operate with at least one other computer in order to carry out any of the above method(s) or form the above computer system(s).

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Abstract

Selon cette invention, la mise à jour de certains emplacements de mémoire seulement est effectuée dans un environnement à ordinateurs multiples dans lequel au moins un programme d'applications (50) est exécuté simultanément sur une pluralité d'ordinateurs (M1, M2, ....Mn) comportant chacun une mémoire locale. Les emplacements de mémoire (A, B, D, E, X) dans la mémoire locale sont classés en deux groupes. Le premier groupe d'emplacements de mémoire (X1, X2, ... Xn, A1, A2, ... An) est accessible par d'autres ordinateurs. Le second groupe d'emplacements de mémoire (B, E) est accessible uniquement par l'ordinateur dont la mémoire locale comprend l'emplacement de mémoire. Des modifications des valeurs d'emplacements de mémoire dans le premier groupe seulement sont envoyées à tous les autres ordinateurs. Un mécanisme de promotion est utilisé pour promouvoir des emplacements de mémoire du second groupe dans le premier groupe lorsque l'exécution du programme d'applications signifie qu'un emplacement de mémoire du second groupe est désigné par un emplacement de mémoire dans le premier groupe (autrement dit l'emplacement du premier groupe désigne dorénavant un emplacement du second groupe).
EP06790317A 2005-10-10 2006-10-05 Architecture de machine modifiee a mise a jour partielle de la memoire Withdrawn EP1934774A4 (fr)

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AU2005905582A AU2005905582A0 (en) 2005-10-10 Modified Machine Architecture with Partial Memory Updating
PCT/AU2006/001447 WO2007041762A1 (fr) 2005-10-10 2006-10-05 Architecture de machine modifiee a mise a jour partielle de la memoire

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US9235485B2 (en) * 2013-07-22 2016-01-12 International Business Machines Corporation Moving objects in a primary computer based on memory errors in a secondary computer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995008809A2 (fr) * 1993-09-24 1995-03-30 Oracle Corporation Procede et dispositif de reproduction de donnees
US6324587B1 (en) * 1997-12-23 2001-11-27 Microsoft Corporation Method, computer program product, and data structure for publishing a data object over a store and forward transport

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2656543B2 (ja) * 1988-05-26 1997-09-24 東京電力株式会社 ブロードキャストメモリ方式分散コンピュータシステム
JPH06332869A (ja) * 1993-05-24 1994-12-02 Hitachi Ltd 共有データ管理システム
JP3489157B2 (ja) * 1993-11-26 2004-01-19 株式会社日立製作所 分散共有メモリシステムおよび計算機
JPH0863382A (ja) * 1994-08-19 1996-03-08 Fujitsu Ltd 分散システムにおけるデータ整合性確認方法及びデータ整合性確認装置
US5799306A (en) * 1996-06-21 1998-08-25 Oracle Corporation Method and apparatus for facilitating data replication using object groups
CN1232914C (zh) * 2000-04-26 2005-12-21 计算机合作者思维公司 在分布计算机系统中保持数据完整性的方法与设备
US20040073828A1 (en) * 2002-08-30 2004-04-15 Vladimir Bronstein Transparent variable state mirroring
JP3897028B2 (ja) * 2004-03-19 2007-03-22 日本電気株式会社 情報処理システム、共有データ処理方法、共有データ処理プログラム
KR101209023B1 (ko) * 2004-04-22 2012-12-10 와라텍 피티와이 리미티드 코디네이트된 오브젝트를 갖는 변경 컴퓨터 아키텍쳐

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995008809A2 (fr) * 1993-09-24 1995-03-30 Oracle Corporation Procede et dispositif de reproduction de donnees
US6324587B1 (en) * 1997-12-23 2001-11-27 Microsoft Corporation Method, computer program product, and data structure for publishing a data object over a store and forward transport

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2007041762A1 *

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EP1934774A4 (fr) 2009-04-15
CN101283343B (zh) 2010-05-19
CN101283343A (zh) 2008-10-08
JP2009512028A (ja) 2009-03-19
WO2007041762A1 (fr) 2007-04-19

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